DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/888,811 filed September 18, 2024. Claims 1-20 are currently pending and have been considered below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8-12, 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (Pre-Grant Publication 10,468,379) in view of Brandl (Pre-Grant Publication 2019/0127155).
Regarding claim 1-5, Liu discloses a 3DIC structure comprising:
(a) fabricating die-source IC dies (3Fig. 1b, 30) wherein the dies are formed on a die-source wafer (not shown (Col. 6, Lines 25-30);
(b) forming conductive vias/interconnection (25/28) on a bonding surface of each die-source IC die (30);
(c) singulating the die-source IC dies (Col. 6, Lines 25-30);
(d) The dies are known good dies and therefore have been tested before and/or after singulating the die-source IC dies to determine known-good die-source IC dies (Col. 6, Lines 25-30);
(e) picking known-good die-source IC dies from the singulated dies;
(f) contacting the picked known-good die-source IC dies to corresponding recipient-wafer ICs (Fig. 1c, 20) formed as part of a recipient wafer (10), thereby bonding the known-good die-source IC dies to the corresponding recipient-wafer ICs on the recipient wafer to form 3-D stacked IC dies;
Liu does not explicitly disclose forming alignment structures on a bonding surface of the recipient wafer, the alignment structures shaped and positioned to guide placement of the picked known-good die-source IC dies with respect to the corresponding recipient-wafer ICs. However Brandl discloses a semiconductor device comprising:
Bonding dies (Fig. 1, 1) on a recipient wafer (2) using a pick and place process wherein an alignment structure such as a L-shaped alignment structure (Fig. 4a-4d, 9) or a sloping surface (Fig. 7d-7g, 30) is formed on a bonding surface of the recipient wafer to contact edges of the placed dies and are shaped and positioned to guide placement of the dies with respect to the recipient wafer.
Brandl further discloses the alignment structure can be in the formed of a grid pattern configured to border and contact all sides of the dies (See Fig. 7d) or an edge engagement pattern configured to contact only parts of the edge of the dies (See Fig. 4a-4d).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the an alignment structure on a bonding surface of the recipient wafer because it will achieve reliable and efficient alignment of the dies on the recipient wafer simultaneously and can be aligned automatic due to gravity and the weight of the dies for an alignment structure with an inclining surface (Paragraph [0010, 0013, 0015]).
Regarding claim 8-12, Liu discloses a 3DIC structure comprising:
A die source IC die (Fig. 1b, 30) including a bonding surface and conductive vias/interconnection (25/28).
A recipient wafer (Fig. 1c, 10) IC die (20) including a bonding surface and conductive vias (Fig. 2a, 18) in aligned contact with the bonding surface and conductive vias of the die (30).
Liu does not explicitly disclose forming alignment structures on a bonding surface of the recipient wafer, the alignment structures shaped and positioned to guide placement of the picked known-good die-source IC dies with respect to the corresponding recipient-wafer ICs. However Brandl discloses a semiconductor device comprising:
Bonding dies (Fig. 1, 1) on a recipient wafer (2) using a pick and place process wherein an alignment structure such as a L-shaped alignment structure (Fig. 4a-4d, 9) or a sloping surface (Fig. 7d-7g, 30) is formed on a bonding surface of the recipient wafer to contact edges of the placed dies and are shaped and positioned to guide placement of the dies with respect to the recipient wafer.
Brandl further discloses the alignment structure can be in the formed of a grid pattern configured to border and contact all sides of the dies (See Fig. 7d) or an edge engagement pattern configured to contact only parts of the edge of the dies (See Fig. 4a-4d).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the an alignment structure on a bonding surface of the recipient wafer because it will achieve reliable and efficient alignment of the dies on the recipient wafer simultaneously and can be aligned automatic due to gravity and the weight of the dies for an alignment structure with an inclining surface (Paragraph [0010, 0013, 0015]).
Regarding claim 15-17, Liu further discloses:
The die source IC die (30) can include a substrate (23) and can include the same material or different material as recipient wafer (10) from a compound semiconductor material wafer, silicon based wafer or gallium arsenide wafer (Col. 2, Lines 41-53 & Col. 6, Lines 31-42)
Claim(s) 6 & 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (Pre-Grant Publication 10,468,379) in view of Brandl (Pre-Grant Publication 2019/0127155) as applied to claim 1 & 8 above, and further in view of Kai-yun (Pre-Grant Publication 2014/0051189).
Regarding claim 6 & 13, Liu and Brandl disclose all of the limitations of claim 1 & 8 (addressed above). Neither reference disclose the alignment structure is a corner engagement pattern to contact four corner of the dies. However Kai-yun discloses a multichip stacked package comprising:
Placing chip package (Fig. 1a, 100) on a recipient wafer (210) having component placement regions (Fig. 7b, 213) and alignment marks thereon wherein the alignment mark (217) can be formed in a corner engagement pattern at four corners of the chip package bonded to the recipient wafer (Paragraph [0027]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the alignment structure as a corner-engagement structure because it will ensured the bonded die is securely aligned to the recipient wafer and minimize misalignment during the bonding process.
Claim(s) 7 & 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (Pre-Grant Publication 10,468,379) in view of Brandl (Pre-Grant Publication 2019/0127155) as applied to claim 1 & 8 above, and further in view of Mueller (Pre-Grant Publication 2023/0288822).
Regarding claim 7 & 14, Liu and Brandl disclose all of the limitations of claim 1 & 8 (addressed above). Neither reference disclose the alignment structure is a sparse corner engagement pattern to contact two opposite corner of the dies. However Mueller discloses a die package structure comprising:
A package (Fig. 2a, 204) including a plurality of dies (222) placed on a substrate (202) wherein an alignment mark (208) can be formed in two corners of the package.
It would have been obvious to those having ordinary skill in the art at the time of invention to form the alignment structure as a sparse corner engagement pattern because it will ensured the bonded die/package is securely aligned to the recipient wafer and minimize misalignment during the bonding process as well as allow the location of the package during a visual inspection or identification process (Paragraph [0029]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (Pre-Grant Publication 10,468,379) in view of Brandl (Pre-Grant Publication 2019/0127155) as applied to claim 8 above, and further in view of Pendse (Pre-Grant Publication 2021/0288036)
Regarding claim 20, Liu further discloses:
The recipient wafer can include a silicon on insulator wafer (Col. 2, Lines 31-42) having die/integrated circuit (20) within.
Liu does not explicitly disclose CMOS circuit formed on recipient wafer. However Pendse discloses a semiconductor device comprising:
Singulating a wafer (Fig. 7, 700) to form individual dies (702/704) and bonded the individual dies to a recipient wafer (708) including CMOS circuitry (Paragraph [0122]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the recipient wafer to include CMOS circuits because the CMOS circuitry will serve to communication and control the bonded source die IC (Paragraph [0122]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang (Pre-Grant Publication 2025/0079329) discloses an alignment structure for die pick and place process.
Schulze (Pre-Grant Publication 2025/0022839) discloses a method and system of performing die-to-wafer bonding.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
