DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 08/28/2026 Response.
Claims 1-20 are pending and examined.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,100,455. Although the claims at issue are not identical, they are not patentably distinct from each other because they recite similar limitations of a neural network, which stores weight values in a first subset of memory cells, and stores calibration data obtained from stored weight values of first subset of memory cells in second subset of memory cells.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 11,475,300 to Yao et al. (hereafter Yao).
Regarding independent claim 10, Yao teaches a method, comprising:
inherently receiving, in a device having memory cells, a request for calibration (set the crossbar RAM array in training mode. There appears the device can be placed in training operation for training mode of the learning phase or interference operation for interference mode of the production phase, see 10:54-11:17); and
in response to the request:
applying a sample input to weight data stored in the memory cells to obtain a first result from operations of multiplication and accumulation performed using the memory cells (FIG. 4: applying neuron input values ri1-rin to crossbar RAM array, also see step 301 of FIG. 3); and
comparing the first result to a second result to determine whether to perform operations to calibrate the memory cells for the operations of multiplication and accumulation (FIG. 4: comparing backpropagation update values <C1, C2, … Cm> to preset threshold, also see steps 305 and 307 of FIG. 3).
Regarding dependent claim 11, Yao implicitly teaches wherein each respective memory cell in the memory cells has a threshold voltage programmable in a first mode to perform operations of multiplication and accumulation (when the device is in interference mode, a first RRAM portion is used to store weights for forward calculation) and programmable in a second mode to store data (when the device is in training mode, a second RRAM portion is used as filters to store updated information, see 12:23-27).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over US Yao in view of US 11,749,322 to Troia (hereafter Troia).
Regarding independent claim 1, Yao teaches a device, comprising:
memory cells (FIG. 4: crossbar RAM array on the left);
set the crossbar RAM array in training mode. There appears the device can be placed in training operation for training mode of the learning phase or interference operation for interference mode of the production phase, see 10:54-11:17); and
a circuit (FIG. 4: comprising forward calculation module, backward calculation module, comparison module, update module) configured, in response to the register storing data indicative of the predetermined mode (such as training mode), to:
apply a sample input to weight data stored in the memory cells to obtain a first result from operations of multiplication and accumulation performed using the memory cells (FIG. 4: applying neuron input values ri1-rin to crossbar RAM array, also see step 301 of FIG. 3); and
compare the first result to a second result to determine whether to perform operations to calibrate the memory cells for the operations of multiplication and accumulation (FIG. 4: comparing backpropagation update values <C1, C2, … Cm> to preset threshold, also see steps 305 and 307 of FIG. 3).
Yao does not explicitly teach register to set the device in selected mode.
Troia teaches a neural network comprising a plurality of registers (see FIG. 2), wherein the registers can set the neural network in training mode (i.e. debug mode, see 8:6-9) or interference mode (i.e. observe the output of the layer, see 8:6-9).
Since Yao and Troia are both from the same field of endeavor, the purpose disclosed by Troia would have been recognized in the pertinent art of Yao.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that registers are commonly used to control operations of most neural networks.
Regarding dependent claim 2, Yao teaches wherein each respective memory cell in the memory cells has a threshold voltage programmable in a first mode to perform operations of multiplication and accumulation (when the device is in interference mode, a first RRAM portion is used to store weights for forward calculation) and programmable in a second mode to store data (when the device is in training mode, a second RRAM portion is used as filters to store updated information, see 12:23-27).
Regarding dependent claim 3, Yao teaches wherein the predetermined mode is a mode of calibration check (i.e. training mode).
Regarding dependent claim 4, Yao teaches wherein the circuit is further configured to: program, in the first mode (i.e. interference mode), threshold voltages of a first subset of the memory cells to store the weight data; and perform operations of multiplication and accumulation using the first subset of the memory cells (e.g. loading weights of neurons and synapses into first RRAM portion prior to performing forward calculation in interference mode, see 10:54-11-17).
Regarding dependent claim 5, Yao teaches wherein the circuit is further configured to: program, in the second mode (i.e. training mode), threshold voltages of a second subset of the memory cells to store the second result of applying an operation of multiplication and accumulation to the sample input and the weight data (when the device is in training mode, second RRAM portion is used as filters to store updated information, see 12:23-27).
Regarding dependent claim 6, Yao teaches wherein the circuit is further configured to, before storing the second result in the second subset of the memory cells: apply the sample input to the weight data stored in the first subset of the memory cells to obtain the second result from operations of multiplication and accumulation performed using the first subset of the memory cells (FIG. 4: before storing updating information in filters of second RAM portion, performing a forward calculation from first RAM portion, see 12:23-27).
Regarding dependent claim 7, Yao teaches wherein the respective memory cell in the memory cells is configured to output, when the threshold voltage of the respective memory cell is programmed in the first mode (i.e. interference mode using forward calculation) and the respective memory cell is applied a predetermined read voltage (FIGS. 1 and 4: when one of V1-Vn corresponding to ri1-rin is applied): a predetermined amount of current to represent a weight of one stored in the respective memory cell; or a negligible amount of current to represent a weight of zero stored in the respective memory cell (because RRAM cell turns on/off according to weight value stored therein).
Regarding dependent claim 8, Yao teaches wherein the threshold voltage of the respective memory cell is positioned within a voltage region among a plurality of voltage regions pre-associated with a plurality of values respectively when programmed in the second mode (because in the training mode, second RRAM portion is used as filters to store updated information of first RAM portion).
Regarding dependent claim 12, Yao does not explicitly teach a register to set the device in selected mode of calibration check.
Troia teaches a neural network comprising a plurality of registers (see FIG. 2), wherein the registers can set the neural network in training mode (i.e. debug mode, see 8:6-9) or interference mode (i.e. observe the output of the layer, see 8:6-9).
Since Yao and Troia are both from the same field of endeavor, the purpose disclosed by Troia would have been recognized in the pertinent art of Yao.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that registers are commonly used to control operations of most neural networks.
Regarding dependent claim 13, Yao teaches programming, in the first mode, threshold voltages of a first subset of the memory cells to store the weight data; and performing operations of multiplication and accumulation using the first subset of the memory cells (There appears the device can be placed in training operation for training mode of the learning phase or interference operation for interference mode of the production phase, see 10:54-11:17. When the device is in interference mode, a first RRAM portion is used to store weights for forward calculation).
Regarding dependent claim 14, Yao teaches programming, in the second mode, threshold voltages of a second subset of the memory cells to store the second result of applying an operation of multiplication and accumulation to the sample input and the weight data (when the device is in training mode, a first RRAM portion is used to store weights for forward calculation, and second RRAM portion as filters to store updated information, see 12:23-27).
Regarding dependent claim 15, Yao teaches prior to storing the second result in the second subset of the memory cells: applying the sample input to the weight data stored in the first subset of the memory cells to obtain the second result from operations of multiplication and accumulation performed using the first subset of the memory cells (FIG. 4: before storing updating information in filters of second RAM portion, performing a forward calculation from first RAM portion, see 12:23-27).
Regarding dependent claim 16, Yao teaches wherein the respective memory cell in the memory cells is configured to output, when the threshold voltage of the respective memory cell is programmed in the first mode (i.e. interference mode using forward calculation) and the respective memory cell is applied a predetermined read voltage (FIGS. 1 and 4: when one of V1-Vn corresponding to ri1-rin is applied): a predetermined amount of current to represent a weight of one stored in the respective memory cell; or a negligible amount of current to represent a weight of zero stored in the respective memory cell (because RRAM cell turns on/off according to weight value stored therein).
Regarding dependent claim 17, Yao teaches wherein the threshold voltage of the respective memory cell is positioned within a voltage region among a plurality of voltage regions pre-associated with a plurality of values respectively when programmed in the second mode (because in the training mode, second RRAM portion is used as filters to store updated information of first RAM portion).
Claims 9, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yao in view of Troia in view of US 11,581,039 to Khwa et al. (hereafter Khwa).
Yao and Troia teach, as applied in prior rejection of claim 8, all claimed subject matter except further limitations set forth in the following claims.
Regarding dependent claim 9, Khwa teaches neural network comprising PCRAM cells, wherein the PCRAM cells are configured to operate in SLC mode or MLC mode responsive to a configuration change commands (see FIGS. 4E, 4F and 5B).
Since Yao and Khwa are both from the same field of endeavor, the purpose disclosed by Khwa would have been recognized in the pertinent art of Yao.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that:
in the first mode, i.e. interference mode, the memory cells should be configured to store one bit per cell because the memory cells are to store weight values, wherein weight values require speedy access for forward calculation. Memory cells in SLC mode is known for quick access purpose.
in the second mode, i.e. training mode, the memory cells should be configured to store more than one bit per cell because the memory cells are used as filters to store updated information, wherein updated information may need high storage during the lifetime of the device. Memory cells in MCL mode is known for high storage purpose.
Regarding dependent claim 18, see rejection applied to claim 9 above.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yao in view of US 10,930,365 to Poliakov et al. (hereafter Poliakov).
Regarding independent claim 19, Yao teaches an apparatus, comprising:
FIG. 4: crossbar RAM array on the left); and
FIG. 4: comprising forward calculation module, backward calculation module, comparison module, update module);
wherein the logic circuit is configured to, in response to the apparatus is in a mode of calibration check mode:
apply a sample input to weight data stored in the memory cells to obtain a first result from operations of multiplication and accumulation performed using the memory cells (FIG. 4: applying neuron input values ri1-rin to crossbar RAM array, also see step 301 of FIG. 3); and
compare the first result to a second result to determine whether to perform operations to calibrate the memory cells for the operations of multiplication and accumulation (FIG. 4: comparing backpropagation update values <C1, C2, … Cm> to preset threshold, also see steps 305 and 307 of FIG. 3).
Yao does not teach the strikethrough limitations.
Poliakov teaches a first integrated circuit die having memory cells (FIG. 6: one of the NVM dies ); and a second integrated circuit die having a logic circuit (FIG. 6: die comprising controller 620).
Since Yao and Poliakov are both from the same field of endeavor, the purpose disclosed by Poliakov would have been recognized in the pertinent art of Yao.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that it is matter of design choice to have memory cells and logic circuit on same die or different dies.
Regarding dependent claim 20, Yao teaches . The apparatus of claim 19, wherein each respective memory cell in the memory cells has a threshold voltage programmable in a first mode to perform operations of multiplication and accumulation and programmable in a second mode to store data (There appears the device can be placed in training operation for training mode of the learning phase or interference operation for interference mode of the production phase, see 10:54-11:17. When the device is in interference mode, a first RRAM portion is used to store weights for forward calculation. When the device is in training mode, a second RRAM portion is used as filters to store updated information, see 12:23-27).
Response to Arguments
Applicant's arguments filed 08/28/2026 have been fully considered but they are not persuasive.
The applicant failed to address the claim rejections, noting that U.S. Patent No. 11,473,300 does not list 'Yao' as an inventor.
In response to this argument, the Examiner appears to have made a typographical error. The correct reference should be U.S. Patent No. 11,475,300. This matter could have been resolved via a telephonic interview with the Examiner or by verifying the attached Form PTOL-326.
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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October 7, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
