DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been presented and pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over IM (US 2008/0222378 A1).
Examiner relies on the entire teachings of the IM reference for the following rejection; the examiner kindly advises the applicant to carefully consider the entire teachings of the IM reference to better understand the examiner’s position and the interpretation(s) applied to the claimed invention.
The IM reference teaches functionally equivalent limitations of the claimed limitations, when the examiner applies Broadest Reasonable Interpretation to the claimed invention, as follows:
CLAIMS 1-20
IM REF. TEACHINGS (emphasis added)
1.A memory device comprising:
Fig 4 with accompanying description (100’)
a plurality of memory components comprising a first memory component; and
Fig 4, with accompanying description (101’-104’)
a processing device, operatively coupled to the plurality of memory components via a communication channel, to perform operations comprising:
Figs 4 with accompanying description (200) connected to the (101’-104’) via CH0-CH3
storing a first value in a first memory location of the first memory component, wherein the first memory location is used for
Figs 4-6, par 57, “first register 341 stores the channel ID based on the …received via the first connections pin CI0 and CI1” and/or par 58, “second register 342 receives the module ID”; the examiner notes that the 341 and/or 342 teaches the claimed first memory location of the 101’, which teaches the claimed memory component
selecting a sub-channel of a plurality of sub-channels of the communication channel, wherein each of the plurality of sub-channels corresponds to one or more respective memory components of the plurality of memory components, wherein the first value specifies that a sub-channel selecting function is enabled;
Fig 4-6, teachings of CH0-CH3 of the respective memory 101’-104’; the examiner notes that CH0-CH3 teaches the claimed channels & sub-channels in combination with registers 341 and/or registers 342; see also par 62, “CLK# is used enable or disable in clock signal CLK input to the router 121”; the examiner notes that CLK# performs enablement of 121 of 101’-1040’
receiving, through the communication channel, a command directed to the memory device;
Fig 4-6, teachings of CH0-CH3 of the respective memory 101’-104’; the examiner notes that CH0-CH3 teaches the claimed channels & sub-channels in combination with registers 341 and/or registers 342
responsive to receiving the command, storing, in a second memory location of the first memory component, a second value specified by the command;
Fig 4-6, par 59, “match logic 343 receives the second channel ID and the second Module ID…generated by the combination of a command and an address, which are output from the controller 200”; the examiner notes that the claimed storing second value is obvious from the Match Logic 343 storing the received second channel ID & module ID for performing matching function.
determining that the second value matches a third value stored in a third memory location of the first memory component, wherein the third value specifies a preset value assigned to the first memory component; and executing, by the first memory component, the command.
Figs 4-6, par 57, “first register 341 stores the channel ID based on the …received via the first connections pin CI0 and CI1” and/or par 58, “second register 342 receives the module ID”; the examiner notes that the 341 and/or 342 teaches the claimed first memory location of the 101’, which teaches the claimed memory component
2. The memory device of claim 1, wherein the second value comprises a first identifier of the first sub-channel corresponding to the first memory component.
Obvious from the teachings of Figs 4-6, par 57, “first register 341 stores the channel ID based on the …received via the first connections pin CI0 and CI1” and/or par 58, “second register 342 receives the module ID”; the examiner notes that the 341 and/or 342 teaches the claimed first identifier
3. The memory device of claim 1, wherein the operations further comprise: determining whether the second value matches the third value of a plurality of third values, wherein each third value of the plurality of third values identifies a respective sub-channel of the plurality of sub-channels, and wherein each third value of the plurality of third values is preset.
Obvious from the teachings of Fig 4-6, par 59, “match logic 343 receives the second channel ID and the second Module ID…generated by the combination of a command and an address, which are output from the controller 200”; the examiner notes that the claimed storing second value is obvious from the Match Logic 343 storing the received second channel ID & module ID for performing matching function, the claimed third value is taught by the 341 and/or 342 & the plurality of third values are stored in 341 and/or 343 of 122-124, see fig 5
4. The memory device of claim 3, wherein the operations further comprise: responsive to determining that the second value does not match rest third values of the plurality of third values except the third value, avoid executing the command by rest memory components of the plurality of memory components except the first memory component.
Obvious from the teachings of Fig 4-6, par 59, “match logic 343 receives the second channel ID and the second Module ID…generated by the combination of a command and an address, which are output from the controller 200”; the examiner notes that the claimed storing second value is obvious from the Match Logic 343 storing the received second channel ID & module ID for performing matching function, the claimed third value is taught by the 341 and/or 342 & the plurality of third values are stored in 341 and/or 343 of 122-124, see fig 5
5. The memory device of claim 3, wherein the operations further comprise: responsive to determining that the second value matches the third value of the plurality of third values,
Obvious from the teachings of Figs 4-6, par 57, “first register 341 stores the channel ID based on the …received via the first connections pin CI0 and CI1” and/or par 58, “second register 342 receives the module ID”; the examiner notes that the 341 and/or 342 teaches the claimed first memory location of the 101’, which teaches the claimed memory component
modifying a fourth value stored in a fourth memory location of the first memory component, wherein the fourth value specifies that the sub-channel selecting function is selected for the first memory component.
Obvious from the teachings of par 62, “the status signal SQ is used to inform the controller 200 of the status of the router 121 in response to a status check command output from the controller 200; the examiner notes that the SQ signal is based on a condition, such as the claimed fourth value.
6. The memory device of claim 1, wherein the operations further comprise: storing a fifth value in a fifth memory location of the first memory component, and wherein the fifth value specifies that the first memory component supports the sub-channel selecting function.
Obvious for the Fig 4-6, teachings of CH0-CH3 of the respective memory 101’-104’; the examiner notes that CH0-CH3 teaches the claimed channels & sub-channels in combination with registers 341 and/or registers 342; the examiner notes that the fifth value is stored in 341 and/or 343 of 122-124, see fig 5
7. The memory device of claim 1, wherein the operations further comprise: modifying the first value stored in the first memory location to disable the sub-channel selecting function; and executing, by the plurality of memory components, the command.
Obvious from the teachings of Figs 4-6, par 57, “first register 341 stores the channel ID based on the …received via the first connections pin CI0 and CI1” and/or par 58, “second register 342 receives the module ID”; the examiner notes that the modification of the value can be performed based on memory configuration, see also figure 4, par 45
8. A method comprising: storing, by a processing device, a first value in a first memory location of a first memory component of a plurality of memory components of a memory device, wherein the first memory location is used for selecting a sub-channel of a plurality of sub-channels in a communication channel, wherein each of the plurality of sub-channels corresponds to one or more memory components of the plurality of memory components of the memory device, wherein the first value specifies that a sub-channel selecting function is enabled; receiving, through the communication channel, a command directed to the memory device; responsive to receiving the command, storing, in a second memory location of the first memory component, a second value specified by the command; determining that the second value matches a third value stored in a third memory location of the first memory component, wherein the third value specifies a preset value assigned to the first memory component; and executing, by the first memory component, the command.
The teachings of the claim 1 are similarly, since the claim 7 is not patentable distinct from the claim 1
9. The method of claim 8, wherein the second value comprises a first identifier of the first sub-channel corresponding to the first memory component.
The teachings of the claim 2 are similarly, since the claim 9 is not patentable distinct from the claim 2
10. The method of claim 8, further comprising: determining whether the second value matches the third value of a plurality of third values, wherein each third value of the plurality of third values identifies a respective sub-channel of the plurality of sub-channels, and wherein each third value of the plurality of third values is preset.
The teachings of the claim 3 are similarly, since the claim 10 is not patentable distinct from the claim 3
11. The method of claim 10, further comprising: responsive to determining that the second value does not match rest third values of the plurality of third values except the third value, avoid executing the command by rest memory components of the plurality of memory components except the first memory component.
The teachings of the claim 4 are similarly, since the claim 11 is not patentable distinct from the claim 4
12. The method of claim 10, further comprising: responsive to determining that the second value matches the third value of a plurality of third values, modifying a fourth value stored in a fourth memory location of the first memory component, wherein the fourth value specifies that the sub-channel selecting function is selected for the first memory component.
The teachings of the claim 5 are similarly, since the claim 12 is not patentable distinct from the claim 5
13. The method of claim 8, further comprising: storing a fifth value in a fifth memory location of the first memory component, and wherein the fifth value specifies that the first memory component supports the sub-channel selecting function.
The teachings of the claim 6 are similarly, since the claim 13 is not patentable distinct from the claim 6
14. The method of claim 8, further comprising: modifying the first value stored in the first memory location to disable the sub-channel selecting function; and executing, by the plurality of memory components, the command.
The teachings of the claim 7are similarly, since the claim 14 is not patentable distinct from the claim 7
15. A non-transitory computer readable storage medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising: storing a first value in a first memory location of a first memory component of a plurality of memory components of a memory device, wherein the first memory location is used for selecting a sub-channel of a plurality of sub-channels in a communication channel, wherein each of the plurality of sub-channels corresponds to one or more memory components of the plurality of memory components of the memory device, wherein the first value specifies that a sub-channel selecting function is enabled; receiving, through the communication channel, a command directed to the memory device; responsive to receiving the command, storing, in a second memory location of the first memory component, a second value specified by the command; determining that the second value matches a third value stored in a third memory location of the first memory component, wherein the third value specifies a preset value assigned to the first memory component; and executing, by the first memory component, the command.
The teachings of the claim 1 are similarly, since the claim 15 is not patentable distinct from the claim 1
16. The non-transitory computer readable storage medium of claim 15, wherein the second value comprises a first identifier of the first sub-channel corresponding to the first memory component.
The teachings of the claim 2 are similarly, since the claim 16 is not patentable distinct from the claim 2
17. The non-transitory computer readable storage medium of claim 15, wherein the operations further comprise: determining whether the second value matches the third value of a plurality of third values, wherein each third value of the plurality of third values identifies a respective sub-channel of the plurality of sub-channels, and wherein each third value of the plurality of third values is preset.
The teachings of the claim 3 are similarly, since the claim 17 is not patentable distinct from the claim 3
18. The non-transitory computer readable storage medium of claim 17, the operations further comprise: responsive to determining that the second value does not match rest third values of the plurality of third values except the third value, avoid executing the command by rest memory components of the plurality of memory components except the first memory component.
The teachings of the claim 4 are similarly, since the claim 18 is not patentable distinct from the claim 4
19. The non-transitory computer readable storage medium of claim 17, wherein the operations further comprise: responsive to determining that the second value matches the third value of a plurality of third values, modifying a fourth value stored in a fourth memory location of the first memory component, wherein the fourth value specifies that the sub-channel selecting function is selected for the first memory component.
The teachings of the claim 5 are similarly, since the claim 19 is not patentable distinct from the claim 5
20. The non-transitory computer readable storage medium of claim 15, wherein the operations further comprise: storing a fifth value in a fifth memory location of the first memory component, and wherein the fifth value specifies that the first memory component supports the sub-channel selecting function.
The teachings of the claim 6 are similarly, since the claim 13 is not patentable distinct from the claim 6
The examiner notes that the IM reference does not: 1) expressly or identically uses the term “sub-channel”; and 2) does not expressly or identically disclose memory locations with its stored data. However, such not expressly or disclosed limitations are well-known types or functionally equivalent variations that are obvious substitutions and/or modifications that can easily made by one skilled in the art, when designing a functionally equivalent system(s). As for the claimed 1) sub-channel labeling difference, the CH0-CH4 of figures 4-6 with accompanying description teaches the functionally equivalent limitations of the claimed invention. As for the claimed 2) memory locations with its stored data, one skilled in the art can easily choose, for providing functional equivalent system, to utilize or to store different, but functionally equivalent, types of data & locations for performing or accomplishing equivalent functions of the claimed invention. Therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to come up with the claimed invention from the functionally equivalent teachings of the IM reference for the detailed teachings & reasons discussed above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B SHIN whose telephone number is (571)272-4159. The examiner can normally be reached 8:00-4:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached at 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER B SHIN/Primary Examiner, Art Unit 2181