DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 9,083,360 B2).
Regarding Claim 1 and equivalent method Claim 11, Lee et al. teaches in Figure 1 an apparatus for generating a clock, the apparatus comprising:
a phase locked loop circuit configured to generate, through an oscillator, a first clock signal having a specified frequency (100);
a monitoring circuit configured to monitor a first bit error rate of a first signal received based on the first clock signal, thereby generating a monitoring result (300, as further depicted in Figure 3A including 311); and
a control logic circuit configured to control the phase locked loop circuit based on the monitoring result (300, as further depicted in Figure 3A 312-316), wherein the control logic circuit is configured to:
based on the first bit error rate being equal to or greater than a threshold value, connect a first boosting current source with the, wherein the first boosting current source is included in the phase locked loop circuit oscillator (based in part on 312’s output to control VCO, as further depicted in Figure 10; Figure 10(c): where the current sources, including a first boosting current source, are connected based on control signals Sv1-Svn), and
based on the first bit error rate being less than the threshold value, disconnect a second boosting current source from the oscillator, wherein the second boosting current source is previously connected with the oscillator (based in part on 312’s output to control VCO, as further depicted in Figure 10; Figure 10(c): where the current sources, including a second boosting current source, are connected based on control signals Sv1-Svn).
Regarding Claim 5, Lee et al. further teaches the apparatus, wherein the phase locked loop circuit includes:
a phase detector configured to output a phase difference between the first clock signal and a reference signal (120), and
a loop filter configured to control the oscillator based on the phase difference (140, which is based on the output of 120 through CP 130), and wherein the control logic circuit is configured to control a gain of the loop filter such that the first bit error rate decreases based on the phase difference (as controlled by signal CS_LF).
Allowable Subject Matter
Claims 16-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 16, the prior art does not disclose, teach or suggest an apparatus for generating a clock, the apparatus comprising:
wherein the inductor-capacitor oscillator includes:
a plurality of cells, each cell of the plurality of cells including a plurality of transistors, the plurality of cells being connected with each other in parallel, and
wherein the control logic circuit is configured to, based on the first bit error rate being equal to or greater than a threshold value, connect a first cell from the plurality of cells with the inductor-capacitor tank;
in combination with all the other claimed limitations.
Claims 17-20 are allowed for depending from Claim 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 2-4, 6-10 and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, the prior art does not disclose, teach or suggest the apparatus, wherein the phase locked loop circuit includes:
a plurality of capacitors corresponding to the plurality of boosting current sources, and
wherein the control logic circuit is configured to: based on the first boosting current source being connected with the oscillator, connect a first capacitor corresponding to the first boosting current source with an output node of the oscillator;
in combination with all the other claimed limitations.
Claims 3, 4, and 6-9 are objected to for depending from Claim 2.
Regarding Claim 10, the prior art does not disclose, teach or suggest the apparatus, comprising:
a decoder including a look-up table, the look-up table containing a bit error rate of a signal and a control signal corresponding to the bit error rate, the signal being received in a clock signal, and wherein the control logic circuit is configured to transmit a control signal to the phase locked loop circuit based on the look-up table, and the control signal corresponds to a bit error rate of the first signal received from the monitoring circuit;
in combination with all the other claimed limitations.
Regarding Claim 12, the prior art does not disclose, teach or suggest the method, wherein the phase locked loop circuit includes a plurality of capacitors corresponding to a plurality of boosting current sources, the plurality of boosting current sources including the first boosting current source and the second boosting current source, and wherein the method includes:
based on the first boosting current source being connected to the oscillator, connecting a first capacitor among the plurality of capacitors with an output node of the oscillator, wherein the first capacitor corresponds to the first boosting current source;
in combination with all the other claimed limitations.
Claims 13-15 are objected to for depending from Claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Higashi et al. (US 2008/0252387 B2) teaches oscillator configurations, including LC-VCOs (see Figures 12A and 12B).
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIANA J. CHENG/Primary Examiner, Art Unit 2849