DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 objected to because of the following informality: “at least one of the plurality of third dielectric layers is connected with the first sacrificial layer” In light of the wording of claim 2, the examiner believes the first sacrificial layer is referring to at least one of “the plurality of first sacrificial layers” in the first deck structure, mentioned in claim 2. This does not render the claim indefinite in light of the specification and other claims; however, appropriate correction is required to fix the issue of inconsistent antecedent basis.
Claim 17 objected to because of the following informalities: “wherein the first filling space is located in the second region of the first deck structure, …, the second filling space is located in the second region of the first deck structure”. In light of the specification, especially reference numerals [0047], and Fig 33. The examiner believes the claim was meant to read, “the second filling space is located in the second region of the second deck structure”. This comes from the understanding of the location of 726 second filling space in Fig 33 which is clearly connected to the second connection hole 722 which is clearly in the second deck 720 in Fig 31. The claim will be interpreted with the altered wording of second deck structure for further prosecution; appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 14-15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 14-15, claim 14 states, “wherein removing part of the first deck structure to form the first connection hole further comprises”, as well as “removing part of the second deck structure to form the second connection hole further comprises”. However, these method steps are not present in independent claim 1, and are first mentioned in claim 2 when the method of forming the connection holes is first stated. There is insufficient antecedent basis for this limitation in the claim.
Therefore, for the purpose of examination, the examiner will treat claims 14-15 as dependent on claim 2, rather than claim 1. Appropriate correction of claim dependency and/or proper antecedent basis is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15, 16-17, 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Jin et al. CN 11380987A, hereinafter “Jin”.
Regarding independent claim 1, Jin discloses A fabrication method (method shown in Fig 11A-M) of a memory device (Jin Fig 9A semiconductor device), comprising:
forming a first stack structure (Fig 9A Cell 1) comprising a plurality of first gate layers (gate electrode layers 230) and a plurality of first dielectric layers (interlayer insulating layer 220) stacked alternately along a first direction (alternating stacked vertically on top of each other shown in Fig 9A, stacked in the z-direction);
forming a second stack structure (Fig 9A Cell 2) comprising a plurality of second gate layers (gate electrode layers 230) and a plurality of second dielectric layers (interlayer insulating layers 220) stacked alternately along the first direction (alternating stacked vertically in the z-direction), wherein the second stack structure and the first stack structure are stacked along the first direction (Cell 2 is stacked on top of Cell 1 vertically along the z-direction);
forming a first connection structure (unit contact 235) that is located on a side of the first stack structure and the second stack structure along a second direction (connection structure is located away from the stack structures along the x-direction) and is connected with at least one of the plurality of first gate layers and at least one of the plurality of second gate layers (“the unit contact 235 can be arranged to be electrically connected to the respective gate electrodes 230 in the first memory cell region CELL1 and the second memory cell region CELL2 at the same time” Jin [0095]), wherein the second direction intersects the first direction (x and z-directions intersect, see coordinate system of Fig 9A);
forming a bit line (common bit line 270d) located between the first stack structure and the second stack structure (in Fig 8 270d is between CELL1 and CELL2, and “the semiconductor device 100d may be integrated at a higher density by including the structure of the first memory cell region CELL1 and the second memory cell region CELL2 sharing the common bit line 270d” [Jin 0086], common bit lines also shown in Fig 3B, BL0-2), wherein an extending direction of the bit line intersects the first direction (bit line extends along the y-direction, intersecting the channels traveling in the z-direction [0087]).
Regarding independent claim 16, Jin discloses a fabrication method of a memory device (Jin Fig 9A device), comprising: forming a first stack structure (Fig 9A cell 1) comprising a plurality of first gate layers and a plurality of first dielectric layers stacked alternately along a first direction (gate layers, 230, insulating layers, 220, alternating in vertical direction); forming a second stack structure (Fig 9A cell 2) comprising a plurality of second gate layers and a plurality of second dielectric layers stacked alternately along the first direction (220 and 230 stacked alternating along vertical z-direction), wherein the second stack structure and the first stack structure are stacked along the first direction (cell 2 is stacked on cell 1 in z-direction in Fig 9A); and forming a first connection structure (unit contact plug 235), the first connection structure comprising a connection pillar (pillar 235), at least one first connection layer and at least one second connection layer (Jin Fig 10B, pillar 235 connects to gate layers in cell 1 and cell 2 on the connection regions RP, the bottom RP is the first connection layer, and the top RP in cell 2, is the second connection layer), wherein the connection pillar is located on a side of the first stack structure and the second stack structure along a second direction (Fig 10B, pillar 235 is located away along the x-direction); the first connection layer is parallel to the second direction (RP layers extend in the x-direction); one first connection layer (Fig 10B, RP in the Cell 1 region) is connected with the connection pillar and one of the plurality of first gate layers (“the connection region RP is a region connected to the unit-contact plug 235” and is a part of the gate electrode layer 230 [Jin 0106]); the second connection layer is parallel to the second direction (RP region in cell 2 extends in x-direction); one second connection layer is connected with the connection pillar and one of the plurality of second gate layers (RP in cell 2 connects to pillar 235 and is pate of a single gate layer in the stack of cell 2); and the second direction intersects the first direction (x-direction and z-direction intersect).
Regarding independent claim 18, Jin discloses, a fabrication method of a memory device (Jin Fig 9A device), comprising: forming a first deck structure (Cell 1), wherein a first region of the first deck structure comprises a plurality of first sacrificial layers and a plurality of first dielectric layers stacked alternately along a first direction (Fig 11B 222 and 220 stacked alternating in the z-direction) and adjoins a second region of the first deck structure (extending in the x-direction to the second region), the second region of the first deck structure is located on a side of the first region of the first deck structure along a second direction (in Fig 9A, the second region is where the connection structure 235 is, on the right side of the first region in the x-direction), and the second direction intersects the first direction (x-direction and z-direction intersect); forming a first select gate (Jin Fig 3B SST1_2 second string selection transistor) that is located in the first region of the first deck structure (Fig 10A, first region I, SST1_2 in Fig 3B is located along the channel region of MC1 memory cell 1); forming a bit line in the first region of the first deck structure (Fig 3B bit line BL1), wherein the bit line is connected with the first select gate (SST1_2 connects to BL1), and an extending direction of the bit line intersects the first direction (bit line extends into the page, while the first direction is up and down the page, vertically); forming a second select gate (Fig 3B SST2_2) that is located on a side of the bit line facing away from the first select gate (located on the opposite side of bit line BL1) and is connected with the bit line (SST2_2 connects to BL1); and forming a second deck structure (MC2 memory cell region 2) located on a side of the second select gate away from the first deck structure (located up the page in Fig 3B in the first direction), wherein a first region (leftmost side of Fig 9A, where the channel structures CH are located) of the second deck structure (CELL 2 Fig 9A) comprises a plurality of second sacrificial layers (222 Fig 11A) and a plurality of second dielectric layers (220 Fig 11A) stacked alternately along the first direction (alternating along z-direction) and adjoins a second region of the second deck structure (regions I and II Fig 10A), and the second region of the second deck structure is located on a side of the first region of the second deck structure along the second direction (region II is located away from region I along the x-direction).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Tanaka et al., US 2022/0005824 A1, hereinafter “Tanaka”.
Regarding claim 2, Jin discloses The fabrication method of claim 1, wherein forming the first stack structure comprises:
forming a first deck structure (Jin Fig 11A, lower stack structure GS1), wherein a first region (let Fig 11A show the entire first region) of the first deck structure comprises a plurality of first sacrificial layers (sacrificial gate layer 222) a plurality of first dielectric layers (interlayer insulating layer 220) stacked alternately along the first direction (stacked alternating in the z-direction) and adjoins a second region of the first deck structure (in Fig 9A, let the right side of the memory device by the second region. The first region, on the left, contains the channel elements CH1 in CELL1 and CH2 in CELL2, and the second region contains the interconnect contacts, 235 that connect both cell structures), the second region of the first deck structure is located on a side of the first region of the first deck structure along the second direction (in Fig 9A, the second region is located along the x-direction, the second direction), and the second direction intersects the first direction (x and z-directions intersect);
forming the second stack structure comprises: forming a second deck structure (Jin Fig 11B) located on a side of the bit line away from the first deck structure (___), wherein a first region (let Fig 11B show the entire first region) of the second deck structure comprises a plurality of second sacrificial layers (222) and a plurality of second dielectric layers (220) stacked alternately along the first direction (stacked in z-direction) and adjoins a second region of the second deck structure (second region on the right side of Fig 9A), and the second region of the second deck structure is located on a side of the first region of the second deck structure along the second direction (on the side in the x-direction); however,
Jin does not explicitly disclose the method of forming the connection holes or connection structures where, after forming the first deck structure and before forming the second deck structure, the fabrication method comprises: removing part of the first deck structure to form a first connection hole that is located in the second region of the first deck structure; after forming the second deck structure and before forming the first connection structure, the fabrication method comprises: removing part of the second deck structure to form a second connection hole that is located in the second region of the second deck structure, wherein the second connection hole and the first connection hole jointly constitute a connection hole; after forming the second deck structure and before forming the first connection structure, the fabrication method further comprises: replacing the plurality of first sacrificial layers with the plurality of first gate layers, and replacing the plurality of second sacrificial layers with the second gate layers; and forming the first connection structure comprises: depositing a conductive material in the connection hole to form the first connection structure.
However, in the same field of endeavor, Tanaka discloses a three-dimensional memory device with stairless contact via structures wherein the method comprises: after forming the first deck structure (Tanaka Fig 37, alternating stacks of insulating and sacrificial gate materials, 132 and 142, respectively. The first deck is the stack below the layers 170 and 180) and before forming the second deck structure (second deck is the alternating layers 232 and 242 above the layers 170 and 180 in Fig 14A), the fabrication method comprises:
removing part of the first deck structure to form a first connection hole (Tanaka Fig 11, first deck has been formed, but first via cavities 319 are formed before the formation of the second deck) that is located in the second region of the first deck structure (319 cavities located in region 200, the contact region of the first deck);
after forming the second deck structure (second deck structure formed in Tanaka Fig 13) and before forming the first connection structure, the fabrication method comprises:
removing part of the second deck structure to form a second connection hole (second via cavities 329, being formed in Fig 18K and then filled with sacrificial material to become the second sacrificial via fill structure 328 which are more clearly shown in Fig 19A) that is located in the second region of the second deck structure (328 structures and 329 cavities formed in the second region, contact region 200, of the second deck), wherein the second connection hole and the first connection hole jointly constitute a connection hole (“each of the first sacrificial via fill structure 318 [[formed in the first via cavities 319]] has a top surface that is physically exposed to a respective one of the second via cavities 329” [Tanaka Col 25 lines 23-25]);
after forming the second deck structure and before forming the first connection structure (see Tanaka Fig 24), the fabrication method further comprises:
replacing the plurality of first sacrificial layers (sacrificial material 142 and 242 in the first deck and second deck, respectively) with the plurality of first gate layers (are both replaced with electrically conductive layers 146 and 246, in the first deck and second deck, respectively, see Figs 24-25), and replacing the plurality of second sacrificial layers with the second gate layers (243 replaced with 246 Fig 24-25);
and forming the first connection structure comprises:
depositing a conductive material in the connection hole to form the first connection structure (first and second sacrificial via fill structures 318 and 323 of the first and second deck, respectively, are removed to form the full connection hole, contact via cavities 85 in Fig 28, these holes are filled with conductive material to form the contact via structure 86 in Fig 29 [Tanaka Col 32 lines 1-20]).
Therefore, it would have been obvious to one having ordinary skill in the art to combine the teachings of Jin and Tanaka, to create the device disclosed in Jin, using the connection structure manufacturing method as disclosed in Tanaka, to “simplify the device fabrication method by omitting formation of stepped surfaces (i.e., a staircase region) in the contact region of the alternating stack” [Tanaka Col 40 lines 18-21].
Regarding claim 19, Jin in view of Tanaka discloses The fabrication method of claim 18 (disclosed by Jin discussed above), wherein after forming the first deck structure and before forming the second deck structure, the fabrication method further comprises (steps of forming connection holes in first and second deck as disclosed by Tanaka, discussed above for claim 2): removing part of the first deck structure to form a first connection hole that is located in the second region of the first deck structure (Tanaka Fig 11, first via cavities 319 in second region (region 200) of first deck); after forming the second deck structure, the fabrication method further comprises: removing part of the second deck structure to form a second connection hole that is located in the second region of the second deck structure (second via cavities 329 formed in Tanaka Figs 18K-19A), wherein the second connection hole and the first connection hole jointly constitute a connection hole (cavities 319 and 329 connect to form one connection whole, Tanaka [Col 25 lines 23-25]); replacing the plurality of first sacrificial layers with a plurality of first gate layers (Figs 24-25, layers 142 replaced with 146), and replacing the second plurality of sacrificial layers with a plurality of second gate layers (layers 242 replaces with 246); and forming a first connection structure in the connection hole (contact via structures 86 shown in Tanaka Fig 29), wherein the first connection structure (Jin’s connection structure, 235, in Fig 10B, when modified to be formed by the method of formation as disclosed in Tanaka discloses the connection structures being connected with at least one of the plurality of first gate layers and second gate layers in their respective deck structures) is connected with at least one of the plurality of first gate layers (Jin Fig 10B, connection structure 235 connected to gate layer 230 in CELL1 through connection region RP Jin [0106]) and is connected with at least one of the plurality of second gate layers (235 is connected to two connection regions, RP in CELL1 and RP in CELL2, Fig 10B).
Regarding claim 14, Jin in view of Tanaka discloses, The fabrication method of claim 1 (examiner will interpret claim 14 to depend on claim 2 instead as discussed above), wherein removing part of the first deck structure to form the first connection hole further comprises (Tanaka Fig 11 shows the formation of first via cavities 319 in the first deck structure): forming a first gate slit (Jin Fig 11H OP2, second opening), that is located in the first region of the first deck structure (located next to the channel structures CH1 of the first deck, CELL1); removing part of the second deck structure to form the second connection hole further comprises: forming a second gate slit (Jin Fig 11i, OP2’) that is located in the first region of the second deck structure (OP2’ creates an opening next to the channel structures CH2 in the second deck structure, CELL2), wherein the second gate slit and the first gate slit jointly constitute a gate slit (OP2 and OP2’ constitute one opening through both deck structures between Figs 11H-11i); and replacing the first plurality of sacrificial layers with the plurality of first gate layers and replacing the second plurality of sacrificial layers with the plurality of second gate layers comprises: injecting an etchant into the gate slit (Jin Fig 11i, the sacrificial layers 22 are selectively etched by a wet etching process [Jin 0115]) to remove the first plurality of sacrificial layers and the plurality of second sacrificial layers (all sacrificial layers 22 in CELL1 and CELL2 are etched away in Fig 11i), to form a fifth filling space and a sixth filling space (any of the second tunnel portion LT2, the openings between the interlayer insulating layers 220, may be the fifth and sixth filling spaces); and depositing a gate material in the fifth filling space and the sixth filling space to form the plurality of first gate layers and the plurality of second gate layers (gate layers 230 are formed in Fig 11J when the openings LT2 are filled with conductive material).
Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Tanaka, further in view of Zhang et al. CN 111211129 A hereinafter “Zhang”.
Regarding claim 15, Jin in view of Tanaka discloses, The fabrication method of claim 14 (Jin in view of Tanaka), however, Jin and Tanaka both fail to explicitly disclose a first deck sub-structure, second deck sub-structure, and forming an etching stop layer.
However, in the same field of endeavor, Zhang discloses forming a 3D memory device wherein forming the first deck structure comprises (Zhang Fig 2f first deck structure made of alternating sacrificial layers, 102, and interlayer insulating layers, 103): forming a first deck sub-structure (Fig 2e is first deck sub-structure) that comprises a first gate sub-slit (Zhang Fig 2c, first gate-line slot 1041) and a first channel hole (first channel hole 1051); forming an etching stop layer on the first gate sub-slit and the first channel hole (etch stop layer 106 formed in Fig 2e); and forming a second deck sub-structure that is located on a side of the etching stop layer away from the first gate sub-slit and the first channel hole (second deck sub-structure shown in Fig 2f, above etch stop layer 106), wherein the second deck sub-structure and the first deck sub-structure jointly constitute the first deck structure (full first deck structure shown in Fig 2f); and removing part of the first deck structure to form the first connection hole comprises: forming a second gate sub-slit (Fig 2j, second gate-line slot 1044) and a second channel hole (Fig 2g, second channel hole 1054), wherein the second gate sub-slit and the first gate sub-slit jointly constitute the first gate slit (1041 and 1044 make the first gate slit 1045 in Fig 2k), the second channel hole and the first channel hole jointly constitute a channel hole (channel hole 1055 in Fig 2h is formed by the connecting first channel hole 1051 and second channel hole 1054), and the first gate slit and the channel hole are located in the first region of the first deck structure (first region of first deck structure is the area of the channel structures and gate lines surrounding the channel structures as shown in Zhang Fig 2l).
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of forming the first and second deck structures in the first region of the device of Jin, with the method of formation as clearly disclosed in Zhang “to avoid etching defect problem area” as the storage units are stacked, which therefore “improves the yield and reliability of the device” [Zhang 0024].
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Tanaka and further in view of Tsutsumi et al., US2024/0215243 A1, hereinafter “Sumi”.
Regarding claim 17, Jin discloses The fabrication method of claim 16, wherein forming the first stack structure comprises: forming a first deck structure (Jin Fig 11A, lower stack structure GS1), wherein a first region of the first deck structure comprises a plurality of first sacrificial layers (sacrificial gate layer 222) and a plurality of first dielectric layers (interlayer insulating layer 220) stacked alternately along the first direction (stacked alternating in the z-direction) and adjoins a second region of the first deck structure (Jin Fig 9A, first deck extends out to the connecting portion, or second region, away to the right in the +x-direction), the second region of the first deck structure is located on a side of the first region of the first deck structure along the second direction (+x-direction Fig 9A), and the second direction intersects the first direction (x and z intersect); forming the second stack structure comprises: forming a second deck structure (Jin Fig 11B), wherein the second deck structure and the first deck structure are stacked along the first direction (Fig 9A, Cell 2 on top of Cell 1 in z-direction); a first region of the second deck structure comprises a plurality of second sacrificial layers (Fig 11B 222) and a plurality of second dielectric layers (220) stacked alternately along the first direction; the first region of the second deck structure adjoins a second region of the second deck structure (Fig 10B shows the first and second regions clearly, region I contains the channel structures CH and region II contains the contact plug 235 and pad regions); and the second region of the second deck structure is located on a side of the first region of the second deck structure along the second direction (region II is away from region I along the x-direction Fig 10B); and Jin in view of Tanaka as described above for claim 2 discloses, after forming the first deck structure and before forming the second deck structure (method of forming connection structures as disclosed by Tanaka), the fabrication method further comprises:
removing part of the first deck structure to form a first connection hole (Tanaka Fig 11, first deck has been formed, but first via cavities 319 are formed before the formation of the second deck) that is located in the second region of the first deck structure (319 cavities located in region 200, the contact region of the first deck);
removing part of the second deck structure (Tanaka Fig 18K-19A, second via cavities 329) to form a second connection hole (329) that extends through the second region of the second deck structure (contact region 200), wherein the second connection hole and the first connection hole jointly constitute a connection hole (Tanaka [Col 25 lines 23-25], Fig 28, full contact via cavities 85);
and replacing the plurality of first sacrificial layers (142 Figs 23-25) with the plurality of first gate layers (146), and replacing the second plurality of sacrificial layers (242 Figs 23-25) with the second plurality of gate layers (246); and forming the first connection structure comprises: filling a conductive material in the connection hole to form the first connection structure (Fig 29, contact via structures 86, filled with conductive material Tanaka [Col 32 lines 1-20]), wherein the conductive material filled in the connection hole forms the connection pillar (forms pillar structures 86);
However, neither Jin nor Tanaka disclose the formation of filling spaces in the connection holes described as: forming a first filling space and a second filling space, wherein the first filling space is located in the second region of the first deck structure, the first filling space and the first connection hole are connected, the second filling space is located in the second region of the second deck structure, and the second filling space and the second connection hole are connected; the conductive material filled in the first filling space forms the first connection layer; the conductive material filled in the second filling space forms the second connection layer; the first connection layer is parallel to the second direction; one first connection layer is connected with the connection pillar and one of the plurality of first gate layers; the second connection layer is parallel to the second direction; one second connection layer is connected with the connection pillar and one of the plurality of second gate layers; and the connection pillar, the first connection layer and the second connection layer jointly constitute the first connection structure.
However, in the same field of endeavor, Sumi discloses forming a first filling space and a second filling space (Sumi Fig 43 fin cavity portions 87F), wherein the first filling space is located in the second region of the first deck structure (Fig 29 shows the first deck structure with the fin cavities 87F for the first connection structure 87A, the second region being the word line contact region 300), the first filling space and the first connection hole are connected (Fig 29, 87F portion connected to 87A, first finned contact via cavities), the second filling space is located in the second region of the second (see claim objections above) deck structure (Sumi discloses creating a second deck structure, as shown in Fig 31 above the inter-tier dielectric layer 180, and also creating finned contact via cavities in this second tier/deck, 87B shown in Fig 29, “the single-layer contact via structure 86 comprise first contact via structure 86A … and further comprise second contact via structures 86B in contact with a respective one of the second electrically conductive layers 246 … shown in Fig 31” [Sumi 0193]) , and the second filling space and the second connection hole are connected (second filling space is 87F connected to second connection hole 87B in Fig 29); forming the first connection structure comprises: filling a conductive material (filled with conductive material between Figs 29-30A) in the connection hole (holes 87A and 87B including fins 87F) to form the first connection structure, wherein the conductive material filled in the connection hole forms the connection pillar (connection pillars 86C Fig 30A filled with conductive material);
the conductive material (conductive material deposited in fin contact via cavities [0152]) filled in the first filling space (refer now to Sumi Fig 30A, 86F connected to connection structure 86A) forms the first connection layer (forms the first connection layer in the first tier); the conductive material filled in the second filling space (86F connected to connection structure 86B) forms the second connection layer (forms the second connection layer in the second tier);
the first connection layer is parallel to the second direction (parallel to the x-direction, across the page); one first connection layer is connected with the connection pillar (conductive pillar portion 86C) and one of the plurality of first gate layers (first conductive layer 146 Fig 30A); the second connection layer is parallel to the second direction (also parallel to x-direction, across the page); one second connection layer is connected with the connection pillar (conductive pillar portion 86C) and one of the plurality of second gate layers (second conductive layer 246); and the connection pillar (Fig 30A 86C), the first connection layer (86F connected to 86A) and the second connection layer (86F connected to 86B) jointly constitute the first connection structure (make-up the layer contact via structures 86 [0153]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming connection structures as disclosed in Tanaka with the fin-shaped filling spaces as disclosed in Sumi to “provide a more precise method of forming the contact via structures 86. Thus, formation of contact via cavities 87 which penetrate through or fail to reach the respective electrically conductive layer (146, 246) due to etching non-uniformities can be avoided. The conductive fin portions 86F of the layer contact via structures 86 provide reliable electrical contact…” between the connection structures and gate layers [Sumi 0164].
Allowable Subject Matter
Claims 3-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cui et al. US 10,304,852 B1 disclosing a 3D memory device with through-memory-level contact via structures in Fig 9A
Xiao et al. CN 109103199 B disclosing a 3D stacked memory device with a shared bit line in the interconnection structure and ditch passage columns connecting the gate layers of both stack structures in Fig 4i
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA MICKEY whose telephone number is (571)270-3109. The examiner can normally be reached M-F, 8am to 5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at 571 270 7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TERESA N MICKEY/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights