DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the reply filed 15 December 2025.
Claims 1-20 are pending and have been presented for examination.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 12 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over MIZUKOSHI (U.S. Patent Application Publication #2025/0165181) in view of HU (U.S. Patent #9,251,891) and JEON (U.S. Patent Application Publication #2023/0162810).
1. MIZUKOSHI discloses A memory device comprising: a memory cell array comprising memory cells (see [0065]: memory structure may comprise one or more array of memory cells); and a peripheral circuit coupled to the memory cell array (see [0071]: controller) and configured to: in response to receiving a first operation command, perform a first operation corresponding to a first type of operation on the memory cell array according to first operation setting information (see [0095]-[0098]: memory device initially operates in QLC mode, the memory device can receive a programming command that identifies the operation as a QLC operation, in response to that command, the memory device would perform a QLC programming operation); and in response to receiving a second operation command, obtain second operation setting information from the memory cell array (see HU and JEON below) and perform a second operation corresponding to a second type of operation on the memory cell array according to the second operation setting information (see [0098]-[0102]: while in QLC mode, the memory device can receive a TLC programming command, the controller will fetch the parameters for operating in the TLC mode, then the controller will perform a TLC programming operation), wherein the second type of operation is different from the first type of operation (see [0090]: the operating parameters for QLC modes and TLC modes are different, and therefore the types of operations are different).
MIZUKOSHI does disclose retrieving second operation setting information, however, the setting information is retrieved from a ROM, not the memory cell array (see MIZUKOSHI [0091]: parameters loaded from ROM). HU discloses storing multiple sets of operating parameters in the memory cell array that is being accessed by the controller (see column 3, lines 33-40). These operating parameters are used for accessing SLC or MLC storage, as the read voltages are different (see column 4, lines 7-20). This is similar to MIZUKOSHI, which is also directed to loading operating parameters specific to TLC and QLC storage. HU is able to update these parameters that are stored in the memory (see Column 5, lines 35-65). JEON discloses that when operating parameters are predefined and stored on the memory device, the system cannot account for variations in the memory and may not provide optimal performance. Being able to modify the parameters can improve reliability and performance of the memory device. The parameters disclosed by MIZUKOSHI are stored in a ROM, and are not updatable. Storing the parameters in the memory cell array, as disclosed by HU, and being able to update the parameters, as disclosed by HU and JEON, would improve the reliability and performance of the memory, as disclosed by JEON. A combination of MIZUKOSHI, HU and JEON would result in the parameters being stored in the memory of MIZUKOSHI, and not the ROM.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MIZUKOSHI to store, and obtain, the setting information from the memory array, as disclosed by HU. One of ordinary skill in the art would have been motivated to make such a modification to improve the performance of the memory system by enabling modifications to stored parameters, as taught by JEON. MIZUKOSHI, HU and JEON are analogous/in the same field of endeavor as all references are directed to managing parameter data for a memory system.
2. The memory device of claim 1, wherein the peripheral circuit comprises a cache memory configured to store one of the first operation setting information or the second operation setting information (see [0094]: the parameters are loaded into operating memory of the controller, this would be the cache memory).
3. The memory device of claim 2, wherein a memory area occupied by the first operation setting information has a first address range in the cache memory, a memory area occupied by the second operation setting information has a second address range in the cache memory, and the first address range and the second address range share at least one common address (see [0094]: memory is accessed based on an address, when the parameters are loaded into operating memory the parameters will occupy an address range; the system loads the parameters of TLC or QLC, not both, therefore the address ranges used to store the parameters can overlap as only one set of parameters is present at a time).
4. The memory device of claim 2, wherein the cache memory is configured to be preloaded with the first operation setting information (see [0093]: one set of parameters is loaded as the default, this is considered being preloaded), and wherein the cache memory is configured to store the second operation setting information obtained from the memory cell array (see [0094]: operating parameters loaded into working memory; [0100]: during a transition the necessary operating parameters are loaded).
5. The memory device of claim 1, wherein each of the first operation and the second operation comprises a write operation (see [0098], [0101]: QLC programming operation and TLC programming operation).
6. The memory device of claim 1, wherein the peripheral circuit is configured to: operate a first memory cell according to the first type of operation, the first memory cell is configured to store a first number of bits (see [0063]: program memory cells using QLC mode; [0066]: memory device can be operated in both TLC and QLC mode); and operate a second memory cell according to the second type of operation, the second memory cell is configured to store a second number of bits (see [0063]: program memory cells using TLC mode; [0066]: memory device can be operated in both TLC and QLC mode), and wherein the first number of bits is different from the second number of bits (see [0063]: QLC and TLC modes store different numbers of bits).
7. The memory device of claim 6, wherein the first type of operation is quad-level cell (QLC) operation, and wherein the second type of operation is triple-level cell (TLC) operation (see [0066]: memory device operated in both TLC and QLC mode).
8. The memory device of claim 1, wherein the peripheral circuit is configured to: perform the first operation by applying a first voltage to a first selected word line (see [0087]: memory cells are programmed by applying a voltage); and perform the second operation by applying a second voltage to a second selected word line (see [0087]: memory cells are programmed by applying a voltage), wherein the first voltage and the second voltage are different in at least one of amplitude or pulse width (see [0090]: programming parameters for QLC and TLC are different, this includes program voltage, program voltage bias, verify voltages, etc.).
9. The memory device of claim 1, wherein the memory cell array comprises a configure block (see [0072]: memory structure includes a reserved area, controller accesses the reserved area for programming, read and erase operations), and wherein the first operation setting information and the second operation setting information are stored in different areas of the configure block (see [0090]: the operating parameters can be stored in storage region 1013 or another storage location, this would include the reserved area since MIZUKOSHI has already disclosed that the reserved area can be accessed for programming, it is inherent that the operating information is stored in different areas, it is not possible to store two pieces of data at the same location), and wherein the peripheral circuit is configured to obtain the second operation setting information from the configure block in the memory cell array (see [0099]-[0101]: when transitioning to the TLC mode, the operating parameters are obtained).
10. The memory device of claim 1, wherein the peripheral circuit is configured to: perform first operations corresponding to the first type of operation on memory cells in a same block; and perform second operations corresponding to the second type of operation on memory cells in another same block (see [0063]: memory cells of each block can be programming according to a TLC mode or a QLC mode).
11. The memory device of claim 1, wherein each of the second operation setting information and the first operation setting information respectively comprises at least one of: voltage control information; timing control information; or process control information (see [0090]: programming parameters for QLC and TLC are different, this includes program voltage, program voltage bias, verify voltages, etc.).
12. MIZUKOSHI discloses A memory device comprising: a memory cell array comprising memory cells (see [0065]: memory structure may comprise one or more array of memory cells); and a peripheral circuit coupled to the memory cell array (see [0071]: controller) and configured to: receive an operation command corresponding to a current type of operation (see [0096]-[0098]: receive a QLC programming operation); determine whether the current type of operation is same as a previous type of operation (see [0098]: memory device will remain in QLC mode in response to receiving a QLC program operation); and if the current type of operation is different from the previous type of operation (see [0101]-[0102]: receive a TLC programming operation), obtain current operation setting information for the current type of operation from the memory cell array (see HU and JEON below) and perform a first operation corresponding to the operation command on the memory cell array according to the current type of operation and the current operation setting information (see [0101]-[0102]: memory device transitions from QLC mode to TLC mode by loading the TLC parameters).
MIZUKOSHI does disclose retrieving second operation setting information, however, the setting information is retrieved from a ROM, not the memory cell array (see MIZUKOSHI [0091]: parameters loaded from ROM). HU discloses storing multiple sets of operating parameters in the memory cell array that is being accessed by the controller (see column 3, lines 33-40). These operating parameters are used for accessing SLC or MLC storage, as the read voltages are different (see column 4, lines 7-20). This is similar to MIZUKOSHI, which is also directed to loading operating parameters specific to TLC and QLC storage. HU is able to update these parameters that are stored in the memory (see Column 5, lines 35-65). JEON discloses that when operating parameters are predefined and stored on the memory device, the system cannot account for variations in the memory and may not provide optimal performance. Being able to modify the parameters can improve reliability and performance of the memory device. The parameters disclosed by MIZUKOSHI are stored in a ROM, and are not updatable. Storing the parameters in the memory cell array, as disclosed by HU, and being able to update the parameters, as disclosed by HU and JEON, would improve the reliability and performance of the memory, as disclosed by JEON. A combination of MIZUKOSHI, HU and JEON would result in the parameters being stored in the memory of MIZUKOSHI, and not the ROM.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MIZUKOSHI to store, and obtain, the setting information from the memory array, as disclosed by HU. One of ordinary skill in the art would have been motivated to make such a modification to improve the performance of the memory system by enabling modifications to stored parameters, as taught by JEON. MIZUKOSHI, HU and JEON are analogous/in the same field of endeavor as all references are directed to managing parameter data for a memory system.
13. The memory device of claim 12, wherein the peripheral circuit is configured to: if the current type of operation is same as the previous type of operation, perform a second operation corresponding to the operation command on the memory cell array according to the previous type of operation and previous operation setting information for the previous type of operation (see [0098]: remain in QLC mode).
14. The memory device of claim 12, wherein the peripheral circuit comprises a cache memory (see [0094]: the parameters are loaded into operating memory of the controller, this would be the cache memory), and wherein the peripheral circuit is configured to: preload the cache memory with default operation setting information (see [0093]: one set of parameters is loaded as the default, this is considered being preloaded); and set a type of operation corresponding to the default operation setting information as a default type of operation (see [0093]: memory device can default to TLC or QLC mode, therefore one of the modes is set as a default).
15. The memory device of claim 14, wherein the default type of operation is quad-level cell (QLC) operation or triple-level cell (TLC) operation (see [0093]: memory device can default to TLC or QLC mode).
16. The memory device of claim 14, wherein the memory cell array comprises a configure block (see [0072]: memory structure includes a reserved area, controller accesses the reserved area for programming, read and erase operations), and wherein obtaining the current operation setting information from the memory cell array comprises: obtaining the current operation setting information from the configure block (see [0099]-[0101]: when transitioning to the TLC mode, the operating parameters are obtained); and replacing previous operation setting information in the cache memory with the current operation setting information (see [0098]-[0103]: only one set of parameters are loaded at a time, when the system transitions to another mode, the corresponding set of parameters are loaded, therefore it is considered as being replaced).
17. The memory device of claim 16, wherein the previous operation setting information and the current operation setting information are stored in different areas of the configure block at a time point (see [0090]: the operating parameters can be stored in storage region 1013 or another storage location, this would include the reserved area since MIZUKOSHI has already disclosed that the reserved area can be accessed for programming, it is inherent that the operating information is stored in different areas, it is not possible to store two pieces of data at the same location).
18. The memory device of claim 12, wherein the peripheral circuit comprises a register (see [0094]: operating memory), and wherein the peripheral circuit is configured to: store the previous type of operation in the register, wherein determining whether the current type of operation is same as the previous type of operation comprises comparing the current type of operation with the previous type of operation stored in the register (see [0094]: operating parameters are loaded; [0098]: determine whether to remain in QLC mode or switch modes, the system clearly knows the operating mode in order to make this determination).
19. The memory device of claim 18, wherein the peripheral circuit is configured to: after performing the first operation, set the current type of operation in the register as a new previous type of operation (see [0094]: the operating parameters in the working memory set the type of operation and the current mode, QLC or TLC).
20. MIZUKOSHI discloses A method comprising: receiving, by a peripheral circuit of a memory device (see [0071]: controller), an operation command corresponding to a current type of operation (see [0096]-[0098]: receive a QLC programming operation), wherein the memory device comprises a memory cell array coupled to the peripheral circuit (see [0065]: memory structure may comprise one or more array of memory cells); determining, by the peripheral circuit, whether the current type of operation is same as a previous type of operation (see [0098]: memory device will remain in QLC mode in response to receiving a QLC program operation); and if the current type of operation is different from the previous type of operation (see [0101]-[0102]: receive a TLC programming operation), obtaining current operation setting information for the current type of operation from the memory cell array (see HU and JEON below) and performing a first operation corresponding to the operation command on the memory cell array according to the current type of operation and the current operation setting information (see [0101]-[0102]: memory device transitions from QLC mode to TLC mode by loading the TLC parameters).
MIZUKOSHI does disclose retrieving second operation setting information, however, the setting information is retrieved from a ROM, not the memory cell array (see MIZUKOSHI [0091]: parameters loaded from ROM). HU discloses storing multiple sets of operating parameters in the memory cell array that is being accessed by the controller (see column 3, lines 33-40). These operating parameters are used for accessing SLC or MLC storage, as the read voltages are different (see column 4, lines 7-20). This is similar to MIZUKOSHI, which is also directed to loading operating parameters specific to TLC and QLC storage. HU is able to update these parameters that are stored in the memory (see Column 5, lines 35-65). JEON discloses that when operating parameters are predefined and stored on the memory device, the system cannot account for variations in the memory and may not provide optimal performance. Being able to modify the parameters can improve reliability and performance of the memory device. The parameters disclosed by MIZUKOSHI are stored in a ROM, and are not updatable. Storing the parameters in the memory cell array, as disclosed by HU, and being able to update the parameters, as disclosed by HU and JEON, would improve the reliability and performance of the memory, as disclosed by JEON. A combination of MIZUKOSHI, HU and JEON would result in the parameters being stored in the memory of MIZUKOSHI, and not the ROM.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify MIZUKOSHI to store, and obtain, the setting information from the memory array, as disclosed by HU. One of ordinary skill in the art would have been motivated to make such a modification to improve the performance of the memory system by enabling modifications to stored parameters, as taught by JEON. MIZUKOSHI, HU and JEON are analogous/in the same field of endeavor as all references are directed to managing parameter data for a memory system.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
BONIARDI [2022/0172782] discloses storing operational parameters of a memory within the memory array. [0046]
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132