Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to communication filed on 04/14/2026.
Claims 1-20 are pending.
Claims 7 and 19 are cancelled.
Response to Arguments
5. Applicant arguments filed on 04/14/2026 states claim 7, the current Office Action relies on paragraph 71 of Kasichainula. However, this section only talks about interfaces 716 coupled to memory 718, in which the interfaces 716 can write data to memory 718 or retrieve data from memory 718. Being able to store information or packets in memory 718, though, does not teach or suggest specifically removing the identifier present in a routing field of the data frame, nor is there any teaching or suggestion of removing the identifier from the routing field when the data frame is provided to memory 718 (for access by a host application). That is, Kasichainula does not teach or suggest removing any such information from the data packet, whether storing a data packet in buffer 710 or in memory 718. Claim 7 is incorporated into claim 1. Applicant’s argument is persuasive and the previous rejection claims 1-20 rejection have been withdrawn.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AlA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-3,12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kasichainula (US 20210320886 A1), hereinafter Kasichainula in view of Brunell et al. (US 20080005264 A1) hereinafter Brunell.
Regarding claims 1, 12 and 15, Kasichainula discloses a communication interface for a first node (fig. 1: 700) comprising:
at least a first interface module (fig. 7 :702A) and a second interface module (fig. 7 : 702B) wherein,
the first interface module (fig. 7 : 7 02A) is configured to provide for point-to-point transmission of signaling to a second node (fig. 7: PHY712, fig. 3 host application 302) and receipt of signaling from the second node via one or more first terminals(fig. 7: TX0 RX0) of the first interface module, the first interface module further comprising one or more second terminals (fig.1: primary interface circuitry 730A, secondary interface circuitry 7 32A) for coupling (fig. 7: bridge circuitry 706) to a first processor (fig. 7: interfaces 716; memory 718; (para. [0032] the CPU 106 may execute the host application 122 to cause an execution of a workload (e.g., a computational workload a compute workload, etc.) by hardware of the computing system 102 such as the CPU 106, the first acceleration circuitry 108, the second acceleration circuitry 110, etc. [0092] the first data interface circuitry 702A may route a received data packet to the memory 718 for storage and access by a host application) to communicatively couple the first processor and the first interface module and the second interface module (fig. 7: 702B) is configured to provide for point-to-point transmission of signaling to a third node (fig. 7: PHY 714, fig. 3 switch 304B) and receipt of signaling from the third node via one or more first terminals (fig. 7: TXl, RX1), the second interface module further comprising one or more second terminals (fig. 7: primary interface circuitry 730B, secondary interface circuitry 732B) for coupling (fig. 7: bridge circuitry 706) to the first processor to communicatively couple the first processor and the second interface module ( fig. 7, 702B); and
at least one hardware, interface-to-interface connection (fig. 7: fabric circuitry 704) configured to communicatively couple the first interface module and the second interface module (fig. 7: forwarding path 703); and
a routing module (fig. 7: packet forwarding engine, PFE, circuitry 708; fig. 7 RX parser circuitry 722A, fig. 7 RX parser circuitry 722B) configured to read a data frame derived from said signaling received via the respective one or more first terminals of one of the first interface module and the second interface module and, based on whether or not an identifier present in a routing field of the data frame matches one or more predetermined identifiers (par.[ 0080]-[0087] the PFE circuitry 708 may be configured, programmed, etc., to forward data packets with addresses (e.g., IP addresses and/or IP ports, MAC addresses, etc.) within a redefined address range. For example, data packets that have addresses that fall within the predefined address range and are provided to the first primary port 742 and/or the second primary port 744 may be forwarded to the third secondary port 754 for storage in the buffer 710),
provide for forwarding of at least part of the data frame to either the one or more second terminals for provision to the first processor or forward the data frame to the interface-to-interface connection for retransmission by the other of the first interface module and the second interface module (par. [0092] in response to the first value of the first register of the first daisy chain mode registers 734A and/or the second daisy chain mode registers 734B indicating that a data packet is to be transmitted to a different destination (e.g., data interface circuitry different from the first data interface circuitry 702A and the second data interface circuitry 702B), the first data interface circuitry 702A may route a received data packet to the buffer 710 for storage and transmission by the second data interface circuitry 702B.
In response to a second value of the first register of the first daisy chain mode registers 734A and/ or the second daisy chain mode registers 734B indicating that a data packet has a destination of the network interface circuitry 700, the first data interface circuitry 702A may route a received data packet to the memory 718 for storage and access by a host application. [0129] the first RX parser circuitry 722A may determine that a destination IP address, a destination IP port, a destination MAC address, etc., and/or a combination thereof, of the first data packet (e.g., included in a header of the first data packet) is within an address range (e.g., a destination address range) indicated by a filter rule that the addresses within the address range are selected for packet forwarding. In response to a determination that the destination IP address, a destination IP port, a destination MAC address, etc., is within the address range, the first RX parser circuitry 722A may instruct the first RX multiplexer circuitry 724A to deliver the first data packet from the first MAC circuitry 720A to the first RX queue 726A (FIG.7). The first RX parser circuitry 722A may determine that the destination IP address, the destination IP port, the destination MAC address, etc., and/or a combination thereof, is not within the address range identified for packet forwarding. The first RX parser circuitry 722A may determine that the destination IP address, the destination IP port, the destination MAC address, etc., corresponds to the network interface circuitry 700 and thereby may identify that the destination of the first data packet is the network interface circuitry).
Kasichainula may not explicitly disclose wherein one or more of the first interface module, the second interface module, or the routing module is configured to, when the at least part of the data frame is forwarded to either the one or more second terminals for provision to the first processor, remove the identifier present in the routing field.
However, Brunell discloses wherein one or more of the first interface module, the second interface module, or the routing module is configured to, when the at least part of the data frame is forwarded to either the one or more second terminals for provision to the first processor, remove the identifier present in the routing field (para. [0026] the anonymizer component 120 can recognize and strip communications of unnecessary identifying information. For example, the anonymizer component 120 can strip communications of all identifying indicia and retag them with other information in an attempt to disguise identity. [0059] At reference numeral 810, a network-based communication is received. Context information associated with a source and/or the communication is received or retrieved and analyzed at 820. At reference numeral 830, a determination is made as to whether the communication should be filtered based on the context. If yes, the method proceeds to 840 where the communication is anonymized in one or more of various manners e.g., stripping or modifying IP address, headers…, for instance depending on the context. For example, the communication may be anonymized in such a manner that minimized adverse effects of communication functionality. Subsequently, the method continues at 850 where the anonymized communication is transmitted to a target destination).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula and include wherein one or more of the first interface module, the second interface module, or the routing module is configured to, when the at least part of the data frame is forwarded to either the one or more second terminals for provision to the first processor, remove the identifier present in the routing field using the teaching of Brunell. One would have been motivated to do so in order to anonymized incoming or outgoing data packets so that sensitive information is provided to communication party in secure manner. Hence adverse effects on communication functionality can be prevented by not allowing outside entities to learn the information.
Regarding claim 2, claim 1 is incorporated. Kasichainula further discloses wherein the routing module comprises a first routing module comprising part of the first interface module and a second routing module comprising part of the second interface module, wherein the first routing module is configured to read the data frame derived from said signaling received via the one or more first terminals of the first interface module and, based on whether or not the identifier present in the routing field of the data frame matches one or more predetermined identifiers, forward the data frame to either the one or more second terminals of the first interface module for provision to the first processor or forward the data frame to the interface-to-interface connection for retransmission by the second interface module to the third node; and the second routing module is configured to read the data frame derived from said signaling received via the one or more first terminals of the second interface module and, based on whether or not the identifier present in the routing field of the data frame matches one or more predetermined identifiers, forward the data frame to either the one or more second terminals of the second interface module for provision to the first processor or forward the data frame to the interface-to-interface connection for retransmission by the first interface module to the second node (see Fig. 7 -first routing module -7 RX parser circuitry 722A; second routing module, Fig. 7 RX parser circuitry 722B. Para. [0077]-[0078] output(s) of the second MAC circuitry 720B. Output(s) of the second MAC circuitry 720B is/are coupled to the input(s) of the second RX parser circuitry 722B. Output(s) of the second MAC circuitry 720B is/are coupled to input(s) of the second RX multiplexer circuitry 724B. Output(s) of the second RX parser circuitry 722B is/are coupled to input(s) (e.g., control input(s), selection input(s), etc.) of the second RX multiplexer circuitry 724B. see also para. [0129] (FIG. 7), the first RX parser circuitry 722A may determine that the first data packet has an address that comports, complies, and/or otherwise invokes a filtering rule. The first RX parser circuitry 722A may determine that a destination IP address, a destination IP port, a destination MAC address, etc., and/or a combination thereof, of the first data packet (e.g., included in a header of the first data packet) is within an address range (e.g., a destination address range) indicated by a filter rule that the addresses within the address range are selected for packet forwarding. In response to a determination that the destination IP address, a destination IP port, a destination MAC address, etc., is within the address range, the first RX parser circuitry 722A may instruct the first RX multiplexer circuitry 724A to deliver the first data packet from the first MAC circuitry 720A to the first RX queue 726A (FIG. 7). The first RX parser circuitry 722A may determine that the destination IP address, the destination IP port, the destination MAC address, etc., and/or a combination thereof, is not within the address range identified for packet forwarding. In some such examples, the first RX parser circuitry 722A may determine that the destination IP address, the destination IP port, the destination MAC address, etc., corresponds to the network interface circuitry 700 and thereby may identify that the destination of the first data packet is the network interface circuitry 700 and is not to be forwarded to another network device. (see also [0080]-[0083]).
Regarding claim 3, claim 1 is incorporated. Kasichainula further discloses wherein the routing module comprises a register and an interface for programming the register with the one or more predetermined identifiers, wherein the predetermined identifiers allow the routing module to determine if information of the data frame is intended for one or more applications executed by the first processor (para. [0080] a first data packet received at the first physical layer 712 may be provided to the first MAC circuitry 720A by RX0, the first RX parser circuitry 722A may retrieve the first data packet or copy thereof from the first MAC circuitry 720A. The first RX parser circuitry 722A and/or the second RX parser circuitry 722B may each implement a snoop filter. For example, the first RX parser circuitry 722A and/or the second parser circuitry 722B may implement filtering of data packet(s), or portion(s) thereof, based on match(es) or miss-match(es) of fields in the packet(s) by utilizing filter rule(s). For example, the first parser circuitry 722A and/or the second parser circuitry 722B may implement a first filter rule of routing received data packet(s) with a destination address of {01:02:03:04:05:06} from a first ingress port (e.g., RX0 of the first data interface circuitry 702A) to an egress port (e.g., TX1 of the second data interface circuitry 702B). In some such examples, the first parser circuitry 722A may instruct the first RX multiplexer circuitry 724A to provide the first data packet to the first RX queue 726A in response to a determination that the first data packet is to be forwarded).
9. Claims 4-6 and 16-18 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kasichainula et al. in view of Brunell et al. and further in view of Lopez et al. (US 20180227229 A1) hereinafter Lopez.
Regarding claims 4 and 16, claim 1 is incorporated. Kasichainula in view of Brunell may not explicitly disclose wherein the routing module is configured to: receive a message from the first processor via the one or more second terminals and, based on a predetermined rule, populate the routing field of the data frame generated to encapsulate the message and provide for transmission of the data frame as said signaling via the respective one or more first terminals. However, Lopez discloses wherein the routing module is configured to: receive a message from the first processor via the one or more second terminals and, based on a predetermined rule, populate the routing field of the data frame generated to encapsulate the message and provide for transmission of the data frame as said signaling via the respective one or more first terminals (para. [0042] application-based forwarding device 108 can be implemented as part of or independently as a router, a gateway device, a switch such as a programmable layer 2 switch and/or a hub. According to one embodiment, application-based forwarding device 108 can identify an application associated with a packet based on, for instance, the IP header information of the packet, wherein the content of the IP header can be extracted and parsed to determine the application with which the packet is associated. [0045] based on the forwarding rule, a forwarding action can be performed using the egress interface associated with the identified forwarding rule. The forwarding rule can also indicate, for instance, if IP packets of the flow need to be encapsulated/processed prior to being forwarded by means of Internet Protocol Secure (IPSec), Generic Routing Encapsulation (GRE),…the forwarding rules can also indicate whether the IP packets are to be sent as an L2 shunt to an L2 reflector device (see also Figs. 4-6)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula in view of Brunell and include receive a message from the first processor via the one or more second terminals and, based on a predetermined rule, populate the routing field of the data frame generated to encapsulate the message and provide for transmission of the data frame as said signaling via the respective one or more first terminals using the teaching of Lopez. One would have been motivated to do so in order to provide deterministic low latency packet forwarding for daisy chaining of network devices in an efficient manner.
Regarding claims 5 and 17, claim 1 is incorporated. Kasichainula in view of Brunell may not explicitly disclose, wherein the routing module is configured to: receive a message from the first processor via the one or more second terminals and, based on information provided by an application executed by the first processor, populate the routing field of the data frame with a specific identifier, the data frame generated to encapsulate the message, and provide for transmission of the data frame as said signaling via the respective one or more first terminals However, Lopez discloses receive a message from the first processor via the one or more second terminals and, based on information provided by an application executed by the first processor, populate the routing field of the data frame with a specific identifier, the data frame generated to encapsulate the message, and provide for transmission of the data frame as said signaling via the respective one or more first terminals (para. [0042] application-based forwarding device 108 can be implemented as part of or independently as a router, a gateway device, a switch such as a programmable layer 2 switch and/or a hub. According to one embodiment, application-based forwarding device 108 can identify an application associated with a packet based on, for instance, the IP header information of the packet, wherein the content of the IP header can be extracted and parsed to determine the application with which the packet is associated. [0045] based on the forwarding rule, a forwarding action can be performed using the egress interface associated with the identified forwarding rule. The forwarding rule can also indicate, for instance, if IP packets of the flow need to be encapsulated/processed prior to being forwarded by means of Internet Protocol Secure (IPSec), Generic Routing Encapsulation (GRE),…the forwarding rules can also indicate whether the IP packets are to be sent as an L2 shunt to an L2 reflector device (see also Figs. 4-6)).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula in view of Brunell and include receive a message from the first processor via the one or more second terminals and, based on information provided by an application executed by the first processor, populate the routing field of the data frame with a specific identifier, the data frame generated to encapsulate the message, and provide for transmission of the data frame as said signaling via the respective one or more first terminals using the teaching of Lopez. One would have been motivated to do so in order to provide deterministic low latency packet forwarding for daisy chaining of network devices in an efficient manner.
Regarding claims 6 and 18, claim 1 is incorporated. Kasichainula in view of Brunell may not explicitly disclose, wherein the routing module is configured to: receive a message from the first processor via the one or more second terminals and, based on information provided by an application executed by the first processor, populate the routing field of the data frame with a specific identifier, the data frame generated to encapsulate the message, and provide for transmission of the data frame as said signaling via the respective one or more first terminals. However Lopeze discloses receive a message from the first processor via the one or more second terminals and, based on information provided by an application executed by the first processor, populate the routing field of the data frame with a specific identifier, the data frame generated to encapsulate the message, and provide for transmission of the data frame as said signaling via the respective one or more first terminals (see para. [0042], [0045] and Fig. 4-6)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula in view of Brunell and include receive a message from the first processor via the one or more second terminals and, based on information provided by an application executed by the first processor, populate the routing field of the data frame with a specific identifier, the data frame generated to encapsulate the message, and provide for transmission of the data frame as said signaling via the respective one or more first terminals using the teaching of Lopez. One would have been motivated to do so in order to provide deterministic low latency packet forwarding for daisy chaining of network devices in an efficient manner.
10. Claims 8-11,13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kasichainula et al. in view of Brunell et al. and further in view of f Dees et al. “Inter-Processor Communication with SIPI/LFAST on the MPC57xx and S32Vxxx families” hereinafter Dees.
Regarding claim 8, claim 1 is incorporated. Kasichainula in view of Brunell may not explicitly disclose wherein the first interface module and the second interface module each include an Asynchronous Serial Transmission Interface block for providing said transmission and receipt of the signaling. However, Dees disclose wherein the first interface module and the second interface module each include an Asynchronous Serial Transmission Interface block for providing said transmission and receipt of the signaling (see pages 1-2 and figs. 1-2, the actual physical layer is implemented with the LFAST physical communication interface. As implied in the name of the interface, the LFAST physical layer is an asynchronous fast serial interface. The protocol is based on a frame format that includes synchronization information at the beginning of the frame. Data within the frame is synchronous).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula in view of Brunell and include wherein the first interface module and the second interface module each include an Asynchronous Serial Transmission Interface block for providing said transmission and receipt of the signaling using the teaching of Dees. One would have been motivated to do so in order to leverage Asynchronous serial transmission and SIPI to address the need for a standardized, high speed communication interface between microcontrollers.
Regarding claim 9, claim 1 is incorporated. Kasichainula in view of Brunell may not explicitly disclose wherein the Asynchronous Serial Transmission Interface block comprise a Low Voltage Differential Signaling Asynchronous Serial Transmission Interface. However, Dees disclose wherein the Asynchronous Serial Transmission Interface block comprise a Low Voltage Differential Signaling Asynchronous Serial Transmission Interface (see pages 1-5 and figs. 1-2 the actual physical layer is implemented with the LFAST physical communication interface. As implied in the name of the interface, the LFAST physical layer is an asynchronous fast serial interface… the Zipwire uses a low-speed reference clock that is shared between the clients and uses a single pair of LVDS signals for data transmission and a second pair for reception. The normal communication mode for the Zipwire is 320 Mb/s, however, it starts up at a lower speed until a basic connection is established between the devices. Page 25, the data signals use a low voltage differential signaling (LVDS) that is internally terminated on the MCU, see also Fig. 5).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula in view of Brunell and include wherein the Asynchronous Serial Transmission Interface block comprise a Low Voltage Differential Signaling Asynchronous Serial Transmission Interface using the teaching of Dees. One would have been motivated to do so in order to leverage Asynchronous serial transmission and SIPI to address the need for a standardized, high speed communication interface between microcontrollers.
Regarding claim 10, claim 1 is incorporated. Kasichainula in view of Brunell may not explicitly disclose wherein the first interface module and the second interface module each include a Serial Inter-Processor Interface, SIPI, block coupled with the Asynchronous Serial Transmission Interface block, wherein the SIPI block and Asynchronous Serial Transmission Interface block provide for said transmission and receipt of the signaling However, Dees disclose wherein the first interface module and the second interface module each include an Asynchronous Serial Transmission Interface block for providing said transmission and receipt of the signaling (see pages 1-5 and figs. 1-2, the actual physical layer is implemented with the LFAST physical communication interface. As implied in the name of the interface, the LFAST physical layer is an asynchronous fast serial interface. The application layer of Zipwire is implemented in the SIPI. The application layer runs on top of the LFAST physical communication interface and has its own protocol. The main purpose of the SIPI is to provide the framework to exchange
information and provides the link between memory or processes on one MCU through the LFAST physical communication interface to another MCU or a smart peripheral device. SIPI also adds error detection features such as CRC, acknowledge,
and timeout).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula in view of Brunell and include wherein the first interface module and the second interface module each include a Serial Inter-Processor Interface, SIPI, block coupled with the Asynchronous Serial Transmission Interface block, wherein the SIPI block and Asynchronous Serial Transmission Interface block provide for said transmission and receipt of the signaling using the teaching of Dees. One would have been motivated to do so in order to leverage Asynchronous serial transmission and SIPI to address the need for a standardized, high speed communication interface between microcontrollers.
Regarding claim 11, claim 2 is incorporated. Kasichainula in view of Brunell may not explicitly disclose wherein: the first interface module and the second interface module each include a Serial Inter-Processor Interface, SIPI, block and an Asynchronous Serial Transmission Interface block, wherein the respective Asynchronous Serial Transmission Interface block includes said one or more first terminals to provide for said transmission and receipt of the signaling to the respective second node and third node and wherein the respective SIPI block includes said one or more second terminals for coupling to the first processor; and wherein the first routing module is configured to provide data frames to and receive data frames from the respective Asynchronous Serial Transmission Interface block and is configured to couple to the first processor via the respective SIPI block; and wherein the second routing module is configured to provide data frames to and receive data frames from the respective Asynchronous Serial Transmission Interface block and is configured to couple to the first processor via the respective SIPI block. However Dees discloses the first interface module and the second interface module each include a Serial Inter-Processor Interface, SIPI, block and an Asynchronous Serial Transmission Interface block, wherein the respective Asynchronous Serial Transmission Interface block includes said one or more first terminals to provide for said transmission and receipt of the signaling to the respective second node and third node and wherein the respective SIPI block includes said one or more second terminals for coupling to the first processor; and wherein the first routing module is configured to provide data frames to and receive data frames from the respective Asynchronous Serial Transmission Interface block and is configured to couple to the first processor via the respective SIPI block; and wherein the second routing module is configured to provide data frames to and receive data frames from the respective Asynchronous Serial Transmission Interface block and is configured to couple to the first processor via the respective SIPI block (see pages 1-5 and Figs 1-2 and 5)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula in view of Brunell and include the first interface module and the second interface module each include a Serial Inter-Processor Interface, SIPI, block and an Asynchronous Serial Transmission Interface block, wherein the respective Asynchronous Serial Transmission Interface block includes said one or more first terminals to provide for said transmission and receipt of the signaling to the respective second node and third node and wherein the respective SIPI block includes said one or more second terminals for coupling to the first processor; and wherein the first routing module is configured to provide data frames to and receive data frames from the respective Asynchronous Serial Transmission Interface block and is configured to couple to the first processor via the respective SIPI block; and wherein the second routing module is configured to provide data frames to and receive data frames from the respective Asynchronous Serial Transmission Interface block and is configured to couple to the first processor via the respective SIPI block using the teaching of Dees. One would have been motivated to do so in order to leverage Asynchronous serial transmission and SIPI to address the need for a standardized, high speed communication interface between microcontrollers.
Regarding claims 13 and 20, claim 1 is incorporated. Kasichainula in view of Brunell may not explicitly disclose wherein the identifier present in the routing field is provided in the data frame in addition to an address field within the data frame. However Dees discloses wherein the identifier present in the routing field is provided in the data frame in addition to an address field within the data frame (see pages 1-3 and Fig. 2, the frame format of the LFAST encapsulated SIPI frames/messages. A frame starts with 16 bits for synchronization (0b1010_1000_0100_1011 [0xA84B]) followed by the LFAST header. The payload of the LFAST frame includes the SIPI header and the actual payload (the contents depend on the payload type), followed by a CRC of the SIPI information. The frame ends with a single '1' stop bit. The synchronization pattern allows the receiver to adjust when the bits will be sampled within the remaining bits in the frame for optimum performance. The receiver uses a multiphase clock to determine which phase of its internal clock to use based on decoding the LFAST sync pattern).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula in view of Brunell and include wherein the identifier present in the routing field is provided in the data frame in addition to an address field within the data frame using the teaching of Davis. One would have been motivated to do so in order to leverage Asynchronous serial transmission and SIPI to address the need for a standardized, high speed communication interface between microcontrollers.
11. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kasichainula et al. in view of Brunell et al. and further in view of Davis et al. (US 20220123864 A1) hereinafter Davis.
Regarding claim 12, claim 1 is incorporated. Kasichainula in view of Brunell may not explicitly disclose wherein the routing module is configured to, based on forwarding of the data frame to the interface-to-interface connection for retransmission by the other of the first interface module and the second interface module, transmit a message for the first processor to inform it of said forwarding. However, Davis discloses wherein the routing module is configured to, based on forwarding of the data frame to the interface-to-interface connection for retransmission by the other of the first interface module and the second interface module, transmit a message for the first processor to inform it of said forwarding (para. [0020] nodes are discrete devices separated by wires.[0021] nodes are discrete devices separated by fiber optics.[0098] Refer to FIG. 3, that shows the symbol clock used for communication between two nodes over their direct connection, as might be used for a Serial Peripheral Interface (SPI))
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula in view of Brunell and include wherein the routing module is configured to, based on forwarding of the data frame to the interface-to-interface connection for retransmission by the other of the first interface module and the second interface module, transmit a message for the first processor to inform it of said forwarding using the teaching of Davis. One would have been motivated to do so in order to support simultaneous transfers, optimize bandwidth utilization, and enable nodes to initiate a multi hop communication.
12. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kasichainula et al. in view of Brunell et al. and further in view of Yousefi et al.(US 20160016523 A1) hereinafter Yousefi.
Regarding claim 14, claim 1 is incorporated. Kasichainula in view of Brunell discloses each node including communication interface as recited in claim 1 above (see Kasichainula’s figs 2 and 3). Kasichainula may not explicitly disclose An electronic control unit, ECU, for a vehicle, the ECU including a plurality of the nodes, each node including a communication interface However, Yousefi discloses An electronic control unit, ECU, for a vehicle, the ECU including a plurality of the nodes, each node including a communication interface (para. [0009],[0140] a vehicle control module 38 may be one or more processing modules, a network node module, an electronic control unit, and/or a vehicle assembly. A vehicle control module 38 (which may also be referred to as a network node module) includes a network interface and at least one device. If the device is an analog device, the vehicle control module 38 further includes an analog to digital converter and/or a digital to analog converter. Such devices may include a sensor, an actuator, an intelligent sensor, an intelligent actuator, an electronic control unit (ECU), and/or a control device. As another example, a vehicle assembly includes a switching circuit module, a plurality of network interfaces operably coupled to the switch circuit module, and a plurality of devices operably coupled to the plurality of network interfaces. Various examples of vehicle control modules will be discussed in greater detail with reference to FIGS. 41-57).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Kasichainula in view of Brunell and include the first interface module and the second interface module each include a Serial Inter-Processor Interface, SIPI, block and an Asynchronous Serial Transmission Interface block, wherein the respective Asynchronous Serial Transmission Interface block includes said one or more first terminals to provide for said transmission and receipt of the signaling to the respective second node and third node and wherein the respective SIPI block includes said one or more second terminals for coupling to the first processor; and wherein the first routing module is configured to provide data frames to and receive data frames from the respective Asynchronous Serial Transmission Interface block and is configured to couple to the first processor via the respective SIPI block; and wherein the second routing module is configured to provide data frames to and receive data frames from the respective Asynchronous Serial Transmission Interface block and is configured to couple to the first processor via the respective SIPI block using the teaching of Dees. One would have been motivated to do so in order to
enhance safety of the vehicle.
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kidest Mendaye whose telephone number is (571)272-2603. The examiner can normally be reached on Monday through Friday 7:00 am-5:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ario Etienne can be reached on (571) 272-4001. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
07/09/2026
/KIDEST MENDAYE/
Examiner, Art Unit 2457
/ARIO ETIENNE/Supervisory Patent Examiner, Art Unit 2457
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