Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3,6,7,9,10,12-15,18,19 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Chou et al (PG Pub 2023/0008409 A1).
Regarding claim 1, Chou teaches a semiconductor device comprising: a channel layer (126/126A to 126C) including a two-dimensional semiconductor material (paragraph [0058]); a source electrode and a drain electrode (210N/210P, paragraphs [0060][0064]) spaced apart from each other on the channel layer; a gate insulating layer (182, paragraph [0051]) on the channel layer, and the gate insulating layer including a two-dimensional insulating material (a sheet as thin as 1 nm thick, paragraph [0070]); an interlayer (180) between the channel layer and the gate insulating layer; and a gate electrode (194) on the gate insulating layer.
Regarding claim 2, Chou teaches the semiconductor device of claim 1, wherein the two-dimensional semiconductor material comprises transition metal dichalcogenide (WS2, paragraph [0047]).
Regarding claim 3, Chou teaches the semiconductor device of claim 2, wherein the transition metal dichalcogenide comprises a metal element (WS2, paragraph [0047]) selected from the group consisting of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re, and a chalcogen element selected from the group consisting of S, Se, and Te.
Regarding claim 6, Chou teaches the semiconductor device of claim 1, wherein the interlayer comprises at least one of transition metal oxide (WO, paragraph [0047]) or transition metal sulfide.
Regarding claim 7, Chou teaches the semiconductor device of claim 6, wherein the transition metal oxide includes oxide of an element selected from the group consisting of Nb, Ta, Mo, and W (WO, paragraph [0047]).
Regarding claim 9, Chou teaches the semiconductor device of claim 1, wherein a thickness of the interlayer is in a range of about 0.1 nm to about 5 nm (paragraph [0070]).
Regarding claim 10, Chou teaches the semiconductor device of claim 1, wherein the interlayer comprises 1 to 10 layers (one layer 180).
Regarding claim 12, Chou teaches the semiconductor device of claim 1, wherein the gate electrode is on at least one of an upper portion or a lower portion of the channel layer (figs. 1-14).
Regarding claim 13, Chou teaches an electronic device comprising the semiconductor device according to claim 1 (figs. 1-14).
Regarding claim 14, Chou teaches (see claim 1) a method of manufacturing a semiconductor device comprising: forming a channel layer, the channel layer including a two-dimensional semiconductor material; forming an interlayer on the channel layer; forming a gate insulating layer on the interlayer, the gate insulating layer including a two-dimensional insulating material; forming a gate electrode on the gate insulating layer; and forming a source electrode and a drain electrode spaced apart from each other on the channel layer.
Regarding claim 15, Chou teaches the method of claim 14, wherein the two-dimensional semiconductor material includes transition metal dichalcogenide (paragraph [0047]).
Regarding claim 18, Chou teaches the method of claim 14, wherein the interlayer comprises at least one of transition metal oxide (WO, paragraph [0047]) or transition metal sulfide.
Regarding claim 19, Chou teaches the method of claim 14, wherein a thickness of the interlayer is in a range of about 0.1 nm to about 5 nm (paragraph [0070]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4,5,16,17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (PG Pub 2023/0008409 A1) as applied to claims 1 and 14 above, and further in view of Osada et al. "A- and B-Site Modified Perovskite Nanosheets and Their Integrations into High-k Dielectric Thin Films", International Journal of Applied Ceramic Technology, 9(1), 29-36, Published 2012, a reference cited by Applicant.
Regarding claims 4 and 16, Chou remains as applied in claims 1 and 14.
Chou does not teach wherein the two-dimensional insulating material comprises Ca2(Nb(1-x)Tax)3O10 (0.3≤x≤1).
In the same field of endeavor, Osada teaches a two-dimensional insulating material comprises Ca2(Nb(1-x)Tax)3O10 (0.3≤x≤1), for benefits such as achieving low leakage and minimal frequency-dependent dielectric constant (fig. 3).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the two-dimensional insulating material to comprise Ca2(Nb(1-x)Tax)3O10 (0.3≤x≤1), for benefits such as achieving low leakage and minimal frequency-dependent dielectric constant
Regarding claims 5 and 17, Chou remains as applied in claims 1 and 14.
Chou does not teach wherein the two-dimensional insulating material comprises Sr2(Nb(1-x)Tax)3O10 (0.3≤x≤1).
In the same field of endeavor, Osada teaches a two-dimensional insulating material comprises Sr2(Nb(1-x)Tax)3O10 (0.3≤x≤1), for benefits such as achieving low leakage and minimal frequency-dependent dielectric constant (fig. 3).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the two-dimensional insulating material to comprise Sr2(Nb(1-x)Tax)3O10 (0.3≤x≤1) for benefits such as achieving low leakage and minimal frequency-dependent dielectric constant.
Claim(s) 8,11,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (PG Pub 2023/0008409 A1) as applied to claims 1 and 14 above, and further in view of Chamlagain et al. "Thermally oxidized 2D TaS2 as a high-? gate dielectric for MoS2 field-effect transistors", 2D Materials, 4(3), 031002, Published June 22, 2017, a reference cited by Applicant.
Regarding claim 8, Chou remains as applied in claim 1.
Chou does not teach the semiconductor device of claim 6, wherein the transition metal sulfide includes sulfide of an element selected from the group consisting of Nb, Ta, Mo, and W.
In the same field of endeavor, Chamlagain teaches a transition metal sulfide includes sulfide (TaS2, page 7, right column) of an element selected from the group consisting of Nb, Ta, Mo, and W, for benefits of providing an interfacial layer with high dielectric quality and low interface trap density (abstract).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the transition metal sulfide includes sulfide of an element selected from the group consisting of Nb, Ta, Mo, and W, for benefits of providing an interfacial layer with high dielectric quality and low interface trap density.
Regarding claim 11, Chou remains as applied in claim 1.
Chou does not teach the interlayer includes a first layer adjacent to the channel layer, the first layer including transition metal sulfide, and a second layer adjacent to the gate insulating layer, the second layer including transition metal oxide.
In the same field of endeavor, Chamlagain teaches an interlayer includes a first layer adjacent to the channel layer, the first layer including transition metal sulfide (TaS2), and a second layer (Ta2O5) adjacent to the gate insulating layer, the second layer including transition metal oxide (page 7, right column), for benefits of providing an interfacial layer with high dielectric quality and low interface trap density (abstract).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the interlayer includes a first layer adjacent to the channel layer, the first layer including transition metal sulfide, and a second layer adjacent to the gate insulating layer, the second layer including transition metal oxide, for benefits of providing an interfacial layer with high dielectric quality and low interface trap density.
Regarding claim 20, Chou remains as applied in claim 14.
Chou does not teach the forming of the interlayer comprises forming a first layer on the channel layer, the first layer including a transition metal sulfide, and forming a second layer on the first layer, the second layer including a transition metal oxide.
Chamlagain teaches the forming of the interlayer comprises forming a first layer (TaS2) on the channel layer, the first layer including a transition metal sulfide (Ta2O5), and forming a second layer on the first layer (page 7, right column), the second layer including a transition metal oxide, for benefits of providing an interfacial layer with high dielectric quality and low interface trap density (abstract).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the forming of the interlayer comprises forming a first layer on the channel layer, the first layer including a transition metal sulfide, and forming a second layer on the first layer, the second layer including a transition metal oxide, for benefits of providing an interfacial layer with high dielectric quality and low interface trap density.
Conclusion
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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