DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicants’ arguments with respect amended claims 1-3, 12, 15-16, 20 filed on 07/21/2026 have been considered but they are not persuasive.
The examiner found some limitations are taught by references previously introduced.
In Remark lines 20-26, page 1, applicant argued that Claim 1 as amended recites, "a first stall counting circuit configured to, based on receiving the first stall counting enable signal at a logic high, count a first stall signal input from the first path, and output a stall counting value indicating a number of counted first stall signals based on counting the first stall signal." Applicant respectfully submits that the cited portions of Subramanian and Lee, either alone or in combination, do not disclose or suggest at least this combination of features of amended claim 1.
Examiner respectfully disagrees with Applicant’s argument. In fact, in paragraph [0064], Lee discloses “the CPU 210 may generate a selection signal SEL having second level, e.g., a high level or logic 1 during the scale-down operation” and Fig.2, [0065] “The one-input multi-output scaler 410 may output pixels HS1 to HSn each scaled at a different scaling ratio at the same time or in a parallel manner” and [0069] The image signal processor 230 may stop or delay a transmission of the pixels OTFI in response to a stall indication signal STALL output from the one-input multi-output scaler 410. For example, the one-input multi-output scaler 410 may generate a stall indication signal STALL having a second level during the scale-up operation” and [0072] “FIGS. 2 and 3, the line memory controller 420 may receive pixels IM which are sequentially input through one of the first path PATH1 and the second path PATH2” Lee teaches a first stall counting circuit (referred to as one-input multi-output scaler 410 operates from HS1 to HSn each scaled value) based on receiving the first stall counting enable at logic high (a stall indication signal STALL output from the one-input multi-output scaler 410 having a second level, high logic level) input from the first path (sequentially input through one of the first path PATH1 and the second path PATH2).
Furthermore, in paragraph [0064], Lee discloses “the CPU 210 may generate a selection signal SEL having a first level, e.g., a low level or logic 0, having a second level, e.g., a high level or logic 1 during the scale-down operation” and Fig. 2, [0065] “The one-input multi-output scaler 410 may receive pixels IM sequentially output from the selector 401, and output pixels HS1 to HSn each scaled at a different scaling ratio at the same time or in a parallel manner” and [0069] The image signal processor 230 may stop or delay a transmission of the pixels OTFI in response to a stall indication signal STALL output from the one-input multi-output scaler 410. For example, the one-input multi-output scaler 410 may generate a stall indication signal STALL having a second level during the scale-up operation” Lee teaches output a stall (a signal STALL output from the one-input multi-out scaler 410) counting value indicating a number of (output pixels HS1 to HSn each scaled at a different scaling ratio value at the same time, Fig. 2) of first stall signal (a selection signal SEL) based on counting the first stall signal.
The interpretations of claims 1-11 under 35 U.S.C. 112(f) are withdrawn in view of the amendment of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective fiTokitag date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable by Subramanian et al. (U.S. 2023/0298124 A1) in view of Lee et al. (U.S. 2016/0239941 A1).
Regarding Claim 1 (Currently amended), Subramanian discloses an image signal processor (Subramanian, [0005] “an image signal processor”), comprising:
a first throttle buffer (Subramanian, Fig. 4, [0064] “The dynamic allocation of the shared section of a buffer 410 is controlled by a rate limiter circuit 430A” and Fig. 5, [0067] “each pixel pipeline 422 may be connected to independent rate limiter circuitry. Rate limiter circuit 430 throttles, such as by exponential reduction, the request rate of a pixel pipeline 422 based on the amount of pending” configured to receive first to third image signals from an image sensor, buffer the first to third image signals, and output the buffered first to third image signals, the first image signal including at least one first line (Subramanian, Fig. 2, [0037] “Image data or video data may flow through various data paths within SOC component 204, raw image data may be generated from the image sensors 202 and processed by ISP 206, and then sent to system memory 230 via bus 232 and memory controller 222” [0039] FIG. 3, an image sensor system 201 that includes one or more image sensors 202A through 202N, an image sensor 202 may include different types of image sensing components that may provide raw image data in different forms to the ISP 206” and Fig. 4, [0060] “ Image signal processor 206 read various image data from system memory 230, process the image data, and write the data back to system memory 230. Multiple asynchronous image processing circuits, which may also be referred to as image processing circuits 422A, 422B, 422C” Subramanian teaches a first throttle buffer (a rate limiter Circuit 430A throttle of Image Signal Processor 206, Fig. 4) receive first to third image signals (Image Processing Circuit 422A-422C, Fig. 4) from an image sensor (202) via the system memory (image sensor generates image signals of raw data and sent to the system memory 230), buffer (410A) the first to third image signals, and output the buffered first to third image signals, the first image signal including at least one first line (Channel 424, Fig. 4);
a first image processing circuit configured to receive the first to third image signals, perform a first calculation on each of the first to third image signals, and output first to third calculated image signals corresponding to the first to third image signals, respectively (Subramanian, Fig. 5, [0061] “Image signal processor 206 includes a plurality of image processing circuits 422. An image processing circuits 422, which may also be referred to as pixel pipeline 422” and [0070] “The pixel pipeline 422 calculates its expected bytes per evaluation period (e.g., clock period or every several clock periods) and sends this value to rate limiter circuit 430, which scales up the value to calculate 606 the initial channel byte per period” Subramanian teaches a first module (referred to as a pixel pipeline 422A) receives the first to third image signals and calculate on each of the first to the third image signals and output first to third calculate signals to the first throttle buffer (the rate limiter Circuit 430) ;
a first buffer checking circuit configured to receive a first memory status signal from the first throttle buffer including information about a capacity of the first line, a total capacity of the first throttle buffer, and a usage capacity of the first throttle buffer (Subramanian, Fig. 4, [0060] “Image signal processor 206 read various image data from system memory 230, process the image data” and [0063] “various pixel pipelines 422 may initiate requests to fetch image data from system memory 230. The fetched image data are temporarily stored in read buffer 410A” and Fig. 5, [0067] “each pixel pipeline 422 may be connected to independent rate limiter circuitry. Rate limiter circuit 430 throttles, the request rate of a pixel pipeline 422 based on the amount of pending and valid data of the pixel pipeline 422 used in the shared section 520” and Fig. 5, [0066] “buffer 410 is divided into sections that include a plurality of private sections 510A, 510B, each pixel pipeline 422 has a reserved minimum private section 510 that is sufficient for one data stream request, buffer 410 may be divided into blocks of 64 bytes” and [0068] “Rate limiter circuit 430 may determine the total number of blocks occupied by the particular pixel pipeline 422 exceeding a throttling threshold” Subramanian teaches receive a first memory (230) status signal from the first throttle buffer (buffer 410A of Rate limiter Circuit Throttle 430A, fetch the image signal data from memory 230, Fig. 4) of the first line (the Pixel Pipeline 422A ) with a total capacity of 64 bytes (a block of 64 bytes, Private Section 510A, Buffer 410, Fig. 5) and determine the usage capacity of the first throttle buffer (the total number of blocks occupied by the pixel pipeline 422A) until a throttling threshold is exceeded.
output a first stall counting enable signal at a logic high, in response to a ratio of the usage capacity of the first throttle buffer to the total capacity of the first throttle buffer being greater than a ratio of the capacity of the first line to the total capacity of the first throttle buffer (Subramanian, Fig. 6, [0074] “a response 620, so that the data are pending to be consumed by the pixel pipeline 422” and [0076] “Rate limiter circuit 430 may detect that the pixel pipeline 422 has stopped sending a buffer data request to buffer 410. As such, the pixel pipeline 422 is determined to be stalled” and Fig. 6, [0078] “Rate limiter circuit 630 determined 634 whether the total allocated blocks exceed a throttling threshold, which may be referred to as a backoff threshold (e.g., measured in a number of blocks). If a particular pixel pipeline 422 has been allocated more than the throttling threshold, rate limiter circuit 430 will perform a throttling operation” and [0079] In the process of throttling, during the period when the total allocated blocks of the pixel pipeline 422 are greater than to a threshold” Subramanian teaches in response 620 to check 628 pending data blocks (Fig. 6) to determining the pixel pipeline is stalled and at exceed a throttling threshold, in response to a ratio of the usage capacity of the first throttle buffer being greater than a ratio of the capacity of the first line (Pixel Pipeline 422A, Private Section 510A, a block of 64 bytes, Buffer 410, Fig. 5) and rate limiter circuit 430 will perform a throttling operation, when the total allocated blocks of the pixel pipeline 422 are greater than to a threshold (64 bytes), step 632, 634, Fig. 6); and
Subramanian discloses Operations performed by resample processing stage 308 may include downscaling or sub-band splitting (Subramanian, [0048]).
However, Subramanian does not explicitly teach a first splitter configured to receive the first to third calculated image signals, split the first to third calculated image signals, and send the first calculated image signal to a first path;
output a first stall counting enable signal at a logic high;
a first stall counting circuit configured to, based on receiving the first stall counting enable signal at a logic high, count a first stall signal input from the first path, and output a stall counting value indicating a number of counted first stall signals based on counting the first stall signal
Lee teaches a first splitter configured to receive the first to third calculated image signals, split the first to third calculated image signals, and send the first calculated image signal to a first path (Lee, Fig. 2, [0049] “The scaler circuit 240 may perform a scaling operation on an image (or pixels OTFI included in the image) transmitted from the image signal processor 230 or an image (or pixels) output from the memory 310 through the bus architecture 203” and [0043] when pixels included in an image to be processed by the scaler circuit 240 are scaled-up, the scaler circuit 240 may generate a stall indication signal, and transmit the generated stall indication signal to the image signal processor 230. Accordingly, the image signal processor 230 may stall pixels transmitted to the scaler circuit 240 or transmit the pixels to the memory controller 250 through the bus architecture 203 in response to the stall indication signal” Lee teaches a first splitter (referred to a scaler circuit 240) to receive image signals from image sensor 300 or memory 310 (Fig. 1) through a first path (Fig. 2) and generate a stall indication signal and transmit the pixels to the memory controller 250 in response the stall indication signal (Fig. 2).
output a first stall counting enable signal at a logic high (Lee, [0064] the CPU 210 may generate a selection signal SEL having a second level, e.g., a high level or logic 1, during the scale-up operation” and Fig. 2, [0069] “The image signal processor 230 may stop or delay a transmission of the pixels OTFI in response to a stall indication signal STALL output from the one-input multi-output scaler 410. For example, the one-input multi-output scaler 410 may generate a stall indication signal STALL having a second level during the scale-up operation” Lee teaches output a first stall counting enable signal at a logic high (a stall indication signal STALL output from the one-input multi-output scaler 410 having a second level, high logic level);
a first stall counting circuit configured to, based on receiving the first stall counting enable signal at a logic high, count a first stall signal input from the first path (Lee, [0064] “the CPU 210 may generate a selection signal SEL having second level, e.g., a high level or logic 1 during the scale-down operation” and Fig.2, [0065] “The one-input multi-output scaler 410 may output pixels HS1 to HSn each scaled at a different scaling ratio at the same time or in a parallel manner” and [0069] The image signal processor 230 may stop or delay a transmission of the pixels OTFI in response to a stall indication signal STALL output from the one-input multi-output scaler 410. For example, the one-input multi-output scaler 410 may generate a stall indication signal STALL having a second level during the scale-up operation” and [0072] “FIGS. 2 and 3, the line memory controller 420 may receive pixels IM which are sequentially input through one of the first path PATH1 and the second path PATH2” Lee teaches a first stall counting circuit (referred to as one-input multi-output scaler 410 operates from HS1 to HSn each scaled value) based on receiving the first stall counting enable at logic high (a stall indication signal STALL output from the one-input multi-output scaler 410 having a second level, high logic level) input from the first path (sequentially input through one of the first path PATH1 and the second path PATH2).
and output a stall counting value indicating a number of counted first stall signals based on counting the first stall signal (Lee, [0064] “the CPU 210 may generate a selection signal SEL having a first level, e.g., a low level or logic 0, having a second level, e.g., a high level or logic 1 during the scale-down operation” and Fig. 2, [0065] “The one-input multi-output scaler 410 may receive pixels IM sequentially output from the selector 401, and output pixels HS1 to HSn each scaled at a different scaling ratio at the same time or in a parallel manner” and [0069] The image signal processor 230 may stop or delay a transmission of the pixels OTFI in response to a stall indication signal STALL output from the one-input multi-output scaler 410. For example, the one-input multi-output scaler 410 may generate a stall indication signal STALL having a second level during the scale-up operation” Lee teaches output a stall (a signal STALL output from the one-input multi-out scaler 410) counting value indicating a number of (output pixels HS1 to HSn each scaled at a different scaling ratio value at the same time, Fig. 2) of first stall signal (a selection signal SEL) based on counting the first stall signal.
A combination between Subramanian and Lee can be used to teach output a first stall counting enable signal at a logic high (as taught by Lee), in response to a ratio of the usage capacity of the first throttle buffer to the total capacity of the first throttle buffer being greater than a ratio of the capacity of the first line to the total capacity of the first throttle buffer (as taught by Subramanian).
a first stall counting circuit configured to count a first stall signal input from the first path, in response to receiving the first stall counting enable signal at a logic high (Lee, [0064] the CPU 210 may generate a selection signal SEL having a second level, e.g., a high level or logic 1, during the scale-up operation” and Fig. 2, [0069] “The image signal processor 230 may stop or delay a transmission of the pixels OTFI in response to a stall indication signal STALL output from the one-input multi-output scaler 410. For example, the one-input multi-output scaler 410 may generate a stall indication signal STALL having a second level during the scale-up operation” and [0072] “FIGS. 2 and 3, the line memory controller 420 may receive pixels IM which are sequentially input through one of the first path PATH1 and the second path PATH2” Lee teaches output a first stall counting enable signal at a logic high (a stall indication signal STALL output from the one-input multi-output scaler 410 having a second level, high logic level) Lee teaches a first stall counting circuit (referred to as a scaler 410) configured to count a first stall input from the first path (the first path PATH1);
Subramanian and Lee are combinable because they are from the same field of endeavor, system and method for image processing and try to solve similar problems. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made for modifying the method of Subramanian to combine with a splitter (referred to a scaler circuit (as taught by Lee) in order to receive an image signal through the path 1 by splitter and generate a stall indication signal because Lee can provide a first splitter (referred to a scaler circuit 240) to receive image signals from image sensor 300 or memory 310 (Fig. 1) through a first path (Fig. 2) and generate a stall indication signal and transmit the pixels to the memory controller 250 in response the stall indication signal (Fig. 2) (Lee, Fig. 2, [0043], [0049]). Doing so, it may provide a scaler circuit (referred to a splitter) generates images which have different scaling, images which have different resolution, or resized images from a single image in a parallel manner, power consumption of the scaler circuit and devices including the scaler can be decreased (Lee, [0186]).
Allowable Subject Matter
Independent claims 12 and 20 are in allowable.
Dependent claims 2-11 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to independent claim 1 the closest prior art references the examiner found are Subramanian et al. (U.S. 2023/0298124 A1) in view of Lee et al. (U.S. 2016/0239941 A1) have been made of record as teaching: : a first throttle buffer configured to receive first to third image signals from an image sensor, buffer the first to third image signals, and output the buffered first to third image signals, the first image signal including at least one first line (Subramanian, Fig. 2, [0037]), Fig. 3, [0039], Fig. 4, [0060], [0064], Fig. 5, [0067]); a first module configured to receive the first to third image signals, perform a first calculation on each of the first to third image signals, and output first to third calculated image signals corresponding to the first to third image signals, respectively (Subramanian, Fig. 5, [0061], [0070]); a first buffer checking circuit configured to receive a first memory status signal from the first throttle buffer including information about a capacity of the first line, a total capacity of the first throttle buffer, and a usage capacity of the first throttle buffer (Subramanian, Fig. 4, [0060], [0064], [0066]); in response to a ratio of the usage capacity of the first throttle buffer to the total capacity of the first throttle buffer being greater than a ratio of the capacity of the first line to the total capacity of the first throttle buffer (Subramanian, [0076], Fig. 8, [0078]); a first splitter configured to receive the first to third calculated image signals, split the first to third calculated image signals, and send the first calculated image signal to a first path (Lee, Fig. 2, [0043], [0049]); output a first stall counting enable signal at a logic high (Lee, [0043], Fig. 2, [0049]); a first stall counting circuit configured to count a first stall signal input from the first path, in response to receiving the first stall counting enable signal at a logic high (Lee, [0064], Fig. 2 [0069]) recited in independent claim 1.
However, the art of record did not teach or suggest the claim taken as a whole and particularly the limitation pertaining
“a throughput checking circuit configured to receive a period signal of the first image signal from the first throttle buffer including information about a first time-point at which the N-th line of the first image signal is input to the first throttle buffer and a second time-point at which the (N+1)-th line of the first image signal is input into the first throttle buffer, and a valid signal of the first image signal from the first throttle buffer including information about a third time-point at which the N-th line of the first image signal is output from the first throttle buffer, and
output a first stall counting enable signal at a logic high, in response to the second time-point being earlier than the third time-point; and
a first stall counting circuit configured to count a first stall signal input from the first path, in response to receiving the first stall counting enable signal at a logic high” recites in independent claim 12.
“a throughput checking circuit configured to receive a period signal of the third image signal from the throttle buffer including information about a first time-point at which the N-th line of the third image signal is input to the throttle buffer and a second time-point at which the (N+1)-th line of the third image signal is input to the throttle buffer, and a valid signal of the third image signal from the throttle buffer including information about a third time-point at which the N-th line of the third image is output from the throttle buffer, and
output a second stall counting enable signal at a logic high, in response to the second time-point of the third image signal being earlier than the third-time point of the third image signal; and
a stall counting circuit configured to count a stall signal input from the first path, in response to receiving one of the first stall counting enable signal at a logic high and the second stall counting enable signal at a logic high” recites in independent claim 20.
“wherein the first splitter is configured to split the first to third calculated image signals, and send the second and third calculated image signals to a second path,
wherein the image signal processor further comprises:
a second throttle buffer configured to receive the second and third calculated image signals through the second path, buffer the second and third calculated image signals, and output the buffered second and third calculated image signals;
a second module image processing circuit configured to receive the second and third calculated image signals, perform a second calculation on each of the second and third calculated image signals, and output fourth and fifth calculated image signals respectively corresponding to the second and third calculated image signals; and
a second splitter configured to receive the fourth and fifth calculated image signals, split the fourth and fifth calculated image signals, and send the fourth calculated image signal to a third path”, recited in dependent claim 2.
Dependent claims 13-18 are allowed because they depend on independent claim 12.
Dependent claims 2-11 are objected because they depend on claim 2.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KHOA VU/Examiner, Art Unit 2611
/KEE M TUNG/Supervisory Patent Examiner, Art Unit 2611
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