DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of species I, claims 1-18 in the reply filed on 03/26/2026 is acknowledged. Claims 19 and 20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim status
Claims 1-20 are pending; claims 1 and 14 are independent. Claims 19-20 have been withdrawn from further consideration.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hasegawa (US 2015/0339989), provided by applicant’s IDS.
Regarding claim 1, Hasegawa teaches a display device (fig. 1 and Para 0024) comprising:
a pixel array (fig. 1, a display panel 20 contains an array of pixels) comprising:
a plurality of pixels (fig. 1 and para 0027);
a plurality of gate lines (fig. 1 and Para 0025, wherein a display panel 20 as an example of a liquid crystal panel is provided with n horizontal scan lines S1 to Sn (n is an integer equal to two or greater); and
a plurality of source lines connected to the plurality of pixels (fig. 1 and Para 0025, wherein a display panel 20 as an example of a liquid crystal panel is provided with m data lines D1 to Dm (m is an integer equal to three or greater) extending in the vertical direction of the two-dimensional screen and coupling a to pixels);
a gate driver configured to apply a plurality of gate signals to each of the plurality of gate lines (fig. 1, scan driver 11 and Para 0030);
a source driver configured to generate a plurality of first data signals corresponding to each of the plurality of source lines (fig. 1, data driver 12 and Para 0031); and
an interpolation circuit configured to: receive the plurality of first data signals from the source driver (fig. 2, KS1-KS6 and Paras 0042-0044); and
provide a second data signal, obtained by interpolating a first data signal corresponding to a first source line among the plurality of source lines and a first data signal corresponding to a third source line among the plurality of source lines, to a second source line between the first source line and the third source line (fig. 2, KS1-KS6 and Paras 0042-0047, wherein a D/A converter C1 converts the video data SD.sub.1 into a gradation voltage corresponding to the brightness level represented by the video data SD.sub.1, and then supplies the gradation voltage as a gradation voltage Vi to an amplifier A1 and an input end VA of a gradation voltage interpolation circuit KS1 and the same for D/A converter C2-C6).
Regarding claim 12, Hasegawa teaches the display device of claim 1, further comprising: a plurality of the second source lines including the second source line, wherein the interpolation circuit is further configured to provide a plurality of the second data signal, obtained by interpolating the first data signal corresponding to the first source line and the first data signal corresponding to the third source line, to the plurality of second source lines (fig. 2, KS1-KS6 and Paras 0042-0047, wherein a D/A converter C1 converts the video data SD.sub.1 into a gradation voltage corresponding to the brightness level represented by the video data SD.sub.1, and then supplies the gradation voltage as a gradation voltage Vi to an amplifier A1 and an input end VA of a gradation voltage interpolation circuit KS1 and the same for D/A converter C2-C6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa, and further in view of Shiu (US 2012/0038599).
Regarding claim 2, Hasegawa teaches the display device of claim 1, but Hasegawa does not expressly disclose wherein the interpolation circuit comprises: a first resistor connected between the first source line and the second source line; a first switch connected between the first source line and the first resistor; a second switch connected between the second source line and the first resistor; a second resistor connected between the second source line and the third source line; a third switch connected between the second source line and the second resistor; and a fourth switch connected between the third source line and the second resistor.
However, Shiu discloses “wherein the interpolation circuit comprises: a first resistor connected between the first source line and the second source line; a first switch connected between the first source line and the first resistor; a second switch connected between the second source line and the first resistor; a second resistor connected between the second source line and the third source line; a third switch connected between the second source line and the second resistor; and a fourth switch connected between the third source line and the second resistor”, see fig. 1 and Paras 0013-0019.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Hasegawa with the teaching Shiu to include a charge-sharing circuit which comprises a resistor, a first switch and a second switch between a first and second source lines (fig. 1, Shiu) as an internal configuration of an interpolation circuit (KS1-KS6, figs 4 and 5, Hasegawa) to improve and enhance an efficiency of the charge sharing of the source driver, as a known technique to yield a predictable result.
Regarding claim 3, Hasegawa in view of Shiu teaches the display device of claim 2, wherein the interpolation circuit comprises: a plurality of first resistors connected in parallel between the first source line and the second source line (fig. 2, resistor R11, R12.,…R1n and Para 0020, Shiu);
a plurality of first switches respectively connected between each of the plurality of first resistors and the first source line (fig. 2, switches 51, 52, …5n and Para 0020, Shiu);
a plurality of second switches respectively connected between each of the plurality of first resistors and the second source line (fig. 2, switches 71, 72, . . . 7n and Para 0022 Shiu);
a plurality of second resistors connected in parallel between the second source line and the third source line (fig. 2, resistor R21, R22.,…R2n and Para 0021, Shiu);
a plurality of third switches respectively connected between each of the plurality of second resistors and the second source line (fig. 2, switches 61, 62, …6n and Para 0021, Shiu); and
a plurality of fourth switches respectively connected between each of the plurality of second resistors and the third source line (fig. 2, switches 71, 72, . . . 7n and Para 0022 Shiu).
Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa, in view of Shiu, and further in view of Knez (US 2019/0180672), provided by applicant’s IDS.
Regarding claim 4, Hasegawa in view of Shiu teaches the display device of claim 2 further comprising: a timing controller (fig. 1, a drive control part 10).
Hasegawa in view of Shiu does not expressly disclose a timing controller configured to receive an image signal, comprising a first area rendered with a first quality and a second area rendered with a second quality lower than the first quality, from a host device.
However, Knez discloses a timing controller configured to receive an image signal, comprising a first area rendered with a first quality and a second area rendered with a second quality lower than the first quality, from a host device, see fig. figs 1, 2 and Paras 0028-0029.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Hasegawa in view of Shiu with the teaching Knez to include a portion of display that is being directly viewed by the user may be displayed using the full (native) resolution available from pixel array. In the native resolution area (fig. 2, area 50), each pixel is provided with unfiltered full resolution data. In portions of the image that lie in the user's peripheral vision such as area (fig. 2, 52 and 54), graphics processing unit 22 can render the image with a lower resolution (e.g., with half resolution, as a known technique to yield a predictable result.
Regarding claim 5, Hasegawa in view of Shiu and in view of Knez teaches the display device of claim 4, wherein the timing controller is further configured to: receive area indication data, indicating a first display area displaying the first area and a second display area displaying the second area, from the host device (fig. 1, 2 and Para 0028, Knez); and
generate a switching control signal for controlling the first switch, the second switch, the third switch, and the fourth switch based on the area indication data (fig. 1, 2 and Para 0027, Knez).
Regarding claim 6, Hasegawa in view of Shiu and in view of Knez teaches the display device of claim 5, wherein the timing controller is further configured to: generate the switch control signal for controlling the first switch, the second switch, the third switch, and the fourth switch to open when pixels connected to each of the first source line, the second source line, and the third source line are in the first display area, based on the area indication data (fig. 1, 2 and Paras 0026-0027, wherein timing controller integrated circuit 28 and/or column driver integrated circuit 30 may include interpolation and filtering circuitry such as circuitry 42 in circuitry 28 and/or circuitry 44 in circuitry 30. The interpolation and filtering circuitry in the display driver circuitry of display 14 may allow graphics processing unit 22 to only render portions of a displayed image at full resolution. Other portions of the image may be rendered at low and/or intermediate level(s) of resolution, Knez).
Regarding claim 7, Hasegawa in view of Shiu and in view of Knez teaches the display device of claim 5, wherein the timing controller is further configured to: generate the switch control signal for controlling the first switch, the second switch, the third switch, and the fourth switch to close when pixels connected to each of the first source line, the second source line, and the third source line are in the second display area, based on the area indication data (fig. 1, 2 and Paras 0026-0027, wherein timing controller integrated circuit 28 and/or column driver integrated circuit 30 may include interpolation and filtering circuitry such as circuitry 42 in circuitry 28 and/or circuitry 44 in circuitry 30. The interpolation and filtering circuitry in the display driver circuitry of display 14 may allow graphics processing unit 22 to only render portions of a displayed image at full resolution. Other portions of the image may be rendered at low and/or intermediate level(s) of resolution, Knez).
Claim(s) 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa, in view of Shiu, in view of Knez, and further in view of Bae (US 2020/0193894).
Regarding claim 8, Hasegawa in view of Shiu and in view of Knez teaches the display device of claim 7, wherein the source driver comprises a plurality of source amplifiers respectively connected to each of the first source line, the second source line, and the third source line (fig. 4 and Paras 0042-0046, Hasegawa), and
Hasegawa in view of Shiu and in view of Knez does not expressly disclose wherein the timing controller is further configured to generate a source amplifier control signal for turning off a second source amplifier connected to the second source line, among the plurality of source amplifiers.
However, Bae “wherein the timing controller is further configured to generate a source amplifier control signal for turning off a second source amplifier connected to the second source line, among the plurality of source amplifiers”, see fig. 2 and Para 0085.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Hasegawa in view of Shiu and in view of Knez with the teaching Bae to include a configuration for driving a display panel based on a relatively lower driving frequency, the first source amplifier 311 may receive a signal and the first logic circuit 202a may control the second source amplifier 312 to be in a turn-off state, as a known technique to yield a predictable result.
Regarding claim 9, Hasegawa in view of Shiu in view of Knez and Bae teaches the display device of claim 8, wherein the source driver further comprises: a plurality of first amplifier switches, each respectively connected to an output terminal of each of the plurality of source amplifiers; a plurality of second amplifier switches, each respectively connected between an inverting terminal of each of the plurality of source amplifiers and each of the plurality of first amplifier switches; and a plurality of third amplifier switches, each respectively connected to the inverting terminal of each of the plurality of source amplifiers and each of the first source line, the second source line, and the third source line (figs 1, 2 and Paras 0020-0022, Shiu).
Regarding claim 10, Hasegawa in view of Shiu in view of Knez and Bae teaches the display device of claim 8, wherein the first source line, the second source line, and the third source line are respectively connected to a plurality of sub-pixels in one pixel through a multiplexer, and wherein the multiplexer is configured to receive the second data signal from the interpolation circuit and provide the second data signal to only one sub-pixel among the plurality of sub-pixels (fig. 2 and para 0086, wherein during the second period, the first logic circuit 202a may activate the connection switch 390 located between the first source amplifier 311 and the second source amplifier 312, based on a connection switch control signal MUX_SW, Bae).
Regarding claim 11, Hasegawa in view of Shiu in view of Knez and Bae display device of claim 10, wherein the plurality of sub-pixels have different colors (fig. 1 and para 0025, Hasegawa).
Claim(s) 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa (US 2015/0339989), and further in view of Knez (US 2019/0180672), both provided by applicant’s IDS.
Regarding claim 14, Hasegawa teaches a display system (fig. 1 and Para 0024) comprising:
a display device comprising a plurality of pixels (fig. 1, a display panel 20 contains an array of pixels) and a plurality of source lines respectively connected to the plurality of pixels, the display device being configured to: generate a plurality of first data signals by the image signal (fig. 1 and Para 0025, wherein a display panel 20 as an example of a liquid crystal panel is provided with m data lines D1 to Dm (m is an integer equal to three or greater) extending in the vertical direction of the two-dimensional screen and coupling a to pixels); and
provide second data signals, obtained by interpolating the plurality of first data signals, to source lines among the plurality of source lines connected to pixels among the plurality of pixels that are displaying the second area (fig. 2, KS1-KS6 and Paras 0042-0047, wherein a D/A converter C1 converts the video data SD.sub.1 into a gradation voltage corresponding to the brightness level represented by the video data SD.sub.1, and then supplies the gradation voltage as a gradation voltage Vi to an amplifier A1 and an input end VA of a gradation voltage interpolation circuit KS1 and the same for D/A converter C2-C6).
Hasegawa does not expressly disclose a host device providing an image signal comprising a first area rendered with a first quality and a second area rendered with a second quality lower than the first quality.
However, Knez discloses a host device providing an image signal comprising a first area rendered with a first quality and a second area rendered with a second quality lower than the first quality, see fig. figs 1, 2 and Paras 0028-0029.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a display system of Hasegawa with the teaching Knez to include a portion of display that is being directly viewed by the user may be displayed using the full (native) resolution available from pixel array. In the native resolution area (fig. 2, area 50), each pixel is provided with unfiltered full resolution data. In portions of the image that lie in the user's peripheral vision such as area (fig. 2, 52 and 54), graphics processing unit 22 can render the image with a lower resolution (e.g., with half resolution, as a known technique to yield a predictable result.
Regarding claim 15, Hasegawa in view of Knez teaches the display system of claim 14 further comprising an eye tracking sensor configured to: track a position of a user eye to obtain eye tracking data; and transmit the eye tracking data to the host device (fig. 4 and Para 0034, wherein the location of the user's gaze (location 74) may be tracked dynamically using eye tracking (e.g., gaze detection system 70), Knez).
Regarding claim 16, Hasegawa in view of Knez teaches the display system of claim 15, wherein the host device further comprises an image processor configured to: render the first area corresponding to the position of the user eye with the first quality; and render the second area which is a peripheral area of the first area with the second quality based on the eye tracking data (fig. figs 1, 2 and Paras 0028-0029, Knez).
Regarding claim 17, Hasegawa in view of Knez teaches the display system of claim 14, wherein the display device is further configured to generate a gate driver control signal, a source driver control signal, and a switch control signal based on the driving control signal (fig. 1 and Paras 0028-0031, Hasegawa), and
wherein the host device is further configured to transmit a driving control signal comprising area indication data indicating the first area and the second area to the display device according to the image signal (fig. figs 1, 2 and Paras 0028-0029, Knez).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa, in view of Knez, and further in view of Bae (US 2020/0193894).
Regarding claim 18, Hasegawa in view of Knez teaches the display system of claim 17, but Hasegawa in view of Knez does not expressly disclose wherein the display device further comprises: a switch controller configured to: receive the switch control signal from the host device; and generate a switch signal for differently driving a plurality of switches connecting between source lines among the plurality of source lines connected to pixels among the plurality of pixels displaying the first area, and a plurality of switches connecting between source lines among the plurality of source lines connected to pixels among the plurality of pixels displaying the second area.
However, Bae disclose wherein the display device further comprises: a switch controller configured to: receive the switch control signal from the host device; and generate a switch signal for differently driving a plurality of switches connecting between source lines among the plurality of source lines connected to pixels among the plurality of pixels displaying the first area, and a plurality of switches connecting between source lines among the plurality of source lines connected to pixels among the plurality of pixels displaying the second area, see fig. 2, Para 0074 and 0080-0081.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the display device of Hasegawa in view of Knez with the teaching Bae to include a first source driver may include a first switch connected to an outer end of the first source amplifier 311, a second switch connected to an output end of the second source amplifier 312, and a connection switch disposed between the output end of the first source amplifier 311 and the output end of the second source amplifier 312, as a known technique to yield a predictable result.
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art either alone or in obvious combination does NOT teach ALL of the above limitations including:
wherein the interpolation circuit comprises: a first resistor connected between one of the plurality of second source lines and the first source line; a first switch connected between the first source line and the first resistor; a second switch connected between one of the plurality of second source lines and the first resistor; at least one second resistor connected between a first adjacent second source line and a second adjacent second source line among the plurality of second source lines; a third switch connected between the first adjacent second source line and the at least one second resistor; a fourth switch connected between the second adjacent second source line and the at least one second resistor; a third resistor connected between another one of the plurality of second source lines and the third source line; a fifth switch connected between the other one of the plurality of second source lines and the third resistor; and a sixth switch connected between the third source line and the third resistor, as recited in claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Spitzer (US 2018/0136720), related to a foveated display system includes a rendering device including at least one graphics processing unit (GPU) to render a foveal region and a peripheral region of a first image, wherein the foveal region has a higher resolution than the peripheral region.
Stafford (US 2017/0287112), related to digital graphics. In particular, the present disclosure is related to varying the quality of imagery presented to the peripheral vision of a viewer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
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/S.E.E/Examiner, Art Unit 2625 8/8/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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