DETAILED ACTION
This office action is in response to the amendment filed on 08/11/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in claim 9 . Therefore, the “a delay circuit… and the output via an inverter” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Examiner’s note: According to claim 1 the current path is between the input and the output and between 202 and 204 of the figures there is no resistor.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 1 and 17 objected to because of the following informalities: Claims 1 and 17 “a first resistor coupled to an input terminal of the output” should be “a first resistor coupled to an input terminal of the output”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Le US 2010/0201332.
Regarding Claims 1 and 17, Le teaches (Figures 2-5) a device (fig. 2) comprising: an input (at 38) configured to receive an input voltage (38); an output (at Vout) configured to provide an output voltage (Vout); a first circuit (R1-R6) coupled to the output, the first circuit being configured to generate a first signal (Vs2) associated with the output voltage (Vout); a first comparator (64) coupled to the first circuit (at 54), the first comparator (64) being configured to compare the first signal with a first reference voltage (Vref2) and generate a second signal (66) based on the comparison, a first resistor (Rz1) coupled to an input terminal of the output; a second resistor (Rz3) coupled to the first resistor at a node at a first terminal (at 36); and a switch (t3) coupled to the comparator, the switch being configured to receive the second signal (66) and adjust a first resistance (of 36) in a current path (I) between the input and the output (38 and Vout) based at least on the second signal (66), the switch being coupled to the node (see fig. 2). (For example: Paragraph 29-30, 40 and 47-58)
Regarding Claim 2, Le teaches (Figures 2-5) further comprising a first amplifier (32) coupled to the switch (t3), the first amplifier being configured to adjust an output current (Iout) based at least on the second signal (66). (For example: Paragraph 29-30, 40 and 47-58)
Regarding Claim 3, Le teaches (Figures 2-5) wherein the first circuit (R1Rr6) comprises a first resistor coupled to the output (R5).
Regarding Claims 4-5 and 18-19, Le teaches (Figures 2-5) wherein the switch (t3) is configured to provide a first current limit ( Rz1, see fig. 5) in response to the output voltage being below the first reference voltage (with 64), and a second current limit (see fig. 5, Rz1+Rz3) in response to the output voltage being above the first reference voltage (with 64); wherein the first current limit is higher than the second current limit (See fig. 5, Is2 is higher and Is1). (For example: Paragraph 29-30, 40 and 47-58)
Regarding Claims 8 and 20, Le teaches (Figures 2-5) wherein the switch comprises a transistor (T1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Le in view of Lopata US 2007/0018623.
Regarding Claim 7, Le teaches (Figures 2-5) the apparatus.
Le does not teach a delay circuit coupled to the switch, the delay circuit being configured to control an activation timing of the switch based at least on the second signal.
Lopata teaches (Figure 2) a delay circuit coupled to the switch (D coupled to the switch at R1), the delay circuit (D) being configured to control an activation timing of the switch (at R1) based at least on the second signal (from 220 or 221). (For example: Paragraph 15-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Le to include a delay circuit coupled to the switch, the delay circuit being configured to control an activation timing of the switch based at least on the second signal, as taught by Lopata to avoid voltage overshoot during operation of the device.
Regarding Claims 9, Le teaches (Figures 2-5) a device.
Le does not teach a second comparator coupled to the first circuit, the second comparator being configured to compare the first signal with a second reference voltage and generate a third signal based on the comparison.
Lopata teaches (Figure 2) a second comparator (221) coupled to the first circuit (R2 and R1), the second comparator being configured to compare the first signal (at input of COMP) with a second reference voltage (Vn) and generate a third signal (from 221) based on the comparison. (For example: Paragraph 15-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Le to include a second comparator coupled to the first circuit, the second comparator being configured to compare the first signal with a second reference voltage and generate a third signal based on the comparison, as taught by Lopata to avoid voltage overshoot during operation of the device.
Claim(s) 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Le in view of Tonomura US 2010/0264896.
Regarding Claim 10, Le teaches (Figures 2-5) a device (fig. 2) comprising: an input (at 38) configured to receive an input voltage (38); an output (at Vout) configured to provide an output voltage (Vout); a first circuit (R1-R6) coupled to the output (at Vout), the first circuit being configured to generate a first signal (Vs2) associated with the output voltage (Vout); a first comparator (64) coupled to the first circuit (R1-R6), the first comparator being configured to compare the first signal with a first reference voltage (inputs to 64) and generate a second signal (66) based on the comparison; a first switch (t1) coupled to the comparator, the first switch being configured to receive the second signal (66); and a first resistor (Rz) coupled to the first switch (t2), the first switch (T2) is configured to adjust a first resistance (of 36) of the first resistor (Rz) based at least on the second signal (66). (For example: Paragraph 29-30, 40 and 47-58)
Le does not teach a delay circuit coupled to a gate of the first switch and the output via an inverter, the delay circuit being associated with an activation timing.
Tonomura teaches (Figure 2) a delay circuit (nand1) coupled to a gate of the first switch (sw2) and the output (at Vout) via an inverter (inv1), the delay circuit being associated with an activation timing (activation of the switches). (For example: Paragraph 57-58 and 66-83)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Le to include a delay circuit coupled to a gate of the first switch and the output via an inverter, the delay circuit being associated with an activation timing, as taught by Tonomura to avoid high inrush currents.
Regarding Claim 11, Le teaches (Figures 2-5) further comprising a first amplifier (32) coupled to the switch (t1), the first amplifier being configured to adjust an output current (Iout) based at least on the second signal (66). (For example: Paragraph 29-30, 40 and 47-58)
Regarding Claim 12, Le teaches (Figures 2-5) wherein the first circuit (r1-r6) comprises a second resistor (r6) coupled to the output.
Regarding Claims 13-14, Le teaches (Figures 2-5) wherein the switch is configured to provide a first current limit (rz1 and Is2 with fig. 5) in response to the output voltage being below the first reference voltage ( with 64, Vref2 and Vs2 ), and a second current limit (Rz1+Rz3 and Is1, see fig. 5) in response to the output voltage being above the first reference voltage (with 64); wherein the first current limit is higher than the second current limit (see fig. 5, Is1 and Is2). (For example: Paragraph 29-30, 40 and 47-58)
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Le in view of Tonomura and further in view of Lopata US 2007/0018623.
Regarding Claim 15, Le teaches (Figures 2-5) a device.
Le does not teach a second comparator coupled to the first circuit, the second comparator being configured to compare the first signal with a second reference voltage and generate a third signal based on the comparison.
Lopata teaches (Figure 2) a second comparator (221) coupled to the first circuit (R2 and R1), the second comparator being configured to compare the first signal (at input of COMP) with a second reference voltage (Vn) and generate a third signal (from 221) based on the comparison. (For example: Paragraph 15-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Le to include a second comparator coupled to the first circuit, the second comparator being configured to compare the first signal with a second reference voltage and generate a third signal based on the comparison, as taught by Lopata to avoid voltage overshoot during operation of the device.
Regarding Claim 16, Le teaches (Figures 2-5) the device.
Le does not teach a second switch coupled to the second comparator and the first resistor, the second switch is configured to adjust the resistance of the first resistor based at least on the third signal.
Lopata teaches (Figure 2) a second switch (at R1n) coupled to the second comparator (at 221) and the first resistor (at R1), the second switch is configured to adjust the resistance of the first resistor (R1) based at least on the third signal (from 221). (For example: Paragraph 15-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Le to include a second switch coupled to the second comparator and the first resistor, the second switch is configured to adjust the resistance of the first resistor based at least on the third signal, as taught by Lopata to avoid voltage overshoot during operation of the device.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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