DETAILED ACTION
Claims 1-20 are present for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, 14-15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over McDermott et al. (US5,860,105) in view of Agrawal et al. (US 2022/0405253).
With respect claim 1, McDermott et al. teaches assigning a dirty tracking bit for each byte of a cache line that is modified while the cache line is stored at a cache and not yet propagated to another cache or memory (see column 6, lines 66-77 and column 7, lines 1-5; each 16 byte cache line also includes four dirty bits (one dirty bit per dword) to allow for write-back mode operations.... The four dirty bits allow for dirty locations to be marked on a dword (32 bit) basis).
McDermott et al. does not teach compressing contiguous dirty tracking bits for each portion of a plurality of portions of the cache line prior to evicting the cache line from the cache.
Agrawal et al. teaches metadata associated with a BMP and/or a BDP section may be run-length encoded before (e.g., before or during) the transferring of the metadata to the live migration server 100b… migration controller 210b may run length encode the 88 bits by counting consecutive 1's and 0's. The example bitmap XBM may have 16 1's, followed by 32 0's, followed by 40 1's. Because only two values (1's and 0's) exist for the bitmap, a marker MKR may indicate a transition between values. Thus, the 11 bytes of metadata associated with the example bitmap XBM may be compressed to 5 bytes of run length encoded metadata RLEMD (e.g., two bytes per marker MKR and one byte per count of 16, 32, and 40) (i.e., contiguous dirty bits may be encoded/compressed) (see paragraphs 120-121).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by McDermott et al. to include the above mentioned to significantly improve (e.g., reduce) bandwidth usage (see Agrawal, paragraph 120).
With respect claim 8, McDermott et al. teaches a cache (see Fig. 1 and column 4, lines 21-27; L2 cache 404); and
a cache controller (see Fig. 1 and column 4, lines 26-27 and 42-44; controller 804 (which may be included as part of the system chipset) configured to:
assign a dirty tracking bit for each byte of a cache line that is modified while the cache line is stored at the cache (see column 6, lines 66-77 and column 7, lines 1-5; each 16 byte cache line also includes four dirty bits (one dirty bit per dword) to allow for write-back mode operations.... The four dirty bits allow for dirty locations to be marked on a dword (32 bit) basis).
McDermott et al. does not teach compress contiguous dirty tracking bits for each portion of a plurality of portions of the cache line prior to evicting the cache line from the cache.
Agrawal et al. teaches metadata associated with a BMP and/or a BDP section may be run-length encoded before (e.g., before or during) the transferring of the metadata to the live migration server 100b… migration controller 210b may run length encode the 88 bits by counting consecutive 1's and 0's. The example bitmap XBM may have 16 1's, followed by 32 0's, followed by 40 1's. Because only two values (1's and 0's) exist for the bitmap, a marker MKR may indicate a transition between values. Thus, the 11 bytes of metadata associated with the example bitmap XBM may be compressed to 5 bytes of run length encoded metadata RLEMD (e.g., two bytes per marker MKR and one byte per count of 16, 32, and 40) (i.e., contiguous dirty bits may be encoded/compressed) (see paragraphs 120-121).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by McDermott et al. to include the above mentioned to significantly improve (e.g., reduce) bandwidth usage (see Agrawal, paragraph 120).
With respect claim 14, McDermott et al. does not teach wherein the cache controller is further configured to: indicate with a single compressed dirty tracking bit that all portions of the cache line are modified.
However, Agrawal et al. teaches wherein section status indicator bit S associated with a given section of the N sections may indicate whether the given section has dirty data or not (e.g., when the section corresponds to a BDP) (i.e., this can be interpreted as if all the portions/line are dirty the status indicator bit S will also be set) (see paragraph 88).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by McDermott et al. to include the above mentioned to significantly improve (e.g., reduce) bandwidth usage (see Agrawal, paragraph 120).
With respect claim 15, McDermott et al. teaches a processor (see Fig. 1 and column 4, lines 23-25; processor 200);
a cache (see Fig. 1 and column 4, lines 21-27; L2 cache 404); and
a cache controller (see Fig. 1 and column 4, lines 26-27 and 42-44; controller 804 (which may be included as part of the system chipset) configured to:
allocate a dirty mask comprising one or more dirty tracking bits to indicate modified bytes of a cache line stored at the cache (see column 6, lines 66-77 and column 7, lines 1-5; each 16 byte cache line also includes four dirty bits (one dirty bit per dword) to allow for write-back mode operations.... The four dirty bits allow for dirty locations to be marked on a dword (32 bit) basis).
McDermott et al. does not teach compress contiguous dirty tracking bits of the dirty mask corresponding to contiguous modified portions of the cache line into a single dirty tracking bit indicating a contiguous range of modified portions of the cache line prior to evicting the cache line from the cache.
Agrawal et al. teaches metadata associated with a BMP and/or a BDP section may be run-length encoded before (e.g., before or during) the transferring of the metadata to the live migration server 100b… migration controller 210b may run length encode the 88 bits by counting consecutive 1's and 0's. The example bitmap XBM may have 16 1's, followed by 32 0's, followed by 40 1's. Because only two values (1's and 0's) exist for the bitmap, a marker MKR may indicate a transition between values. Thus, the 11 bytes of metadata associated with the example bitmap XBM may be compressed to 5 bytes of run length encoded metadata RLEMD (e.g., two bytes per marker MKR and one byte per count of 16, 32, and 40) (i.e., contiguous dirty bits may be encoded/compressed) (see paragraphs 120-121).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by McDermott et al. to include the above mentioned to significantly improve (e.g., reduce) bandwidth usage (see Agrawal, paragraph 120).
With respect claim 20, McDermott et al. does not teach wherein the cache controller is further configured to: indicate with a single compressed dirty tracking bit that all portions of the cache line are modified.
However, Agrawal et al. teaches wherein section status indicator bit S associated with a given section of the N sections may indicate whether the given section has dirty data or not (e.g., when the section corresponds to a BDP) (i.e., this can be interpreted as if all the portions/line are dirty the status indicator bit S will also be set) (see paragraph 88).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by McDermott et al. to include the above mentioned to significantly improve (e.g., reduce) bandwidth usage (see Agrawal, paragraph 120).
Claim(s) 6-7 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over McDermott et al. (US5,860,105) and Agrawal et al. (US 2022/0405253) as applied to claim 1 and 8 above, and further in view of Yang et al. (US10,853,209).
With respect claim 6, McDermott et al. and Agrawal et al. do not teach wherein each compressed dirty tracking bit indicates a range of one or more portions of the cache line that are modified.
Yang et al. teaches wherein first bitmap 310 may include N bits 310-1, 310-2…, 310-N corresponding to the N storage areas respectively, where the shaded bits 310-3, 310-7, 310-12 and 310-13 are marked as “dirty” to indicate that data in the storage areas corresponding to these bits is to be synchronized to the second storage device 120…the mirror module 112 may convert the first bitmap 310 into the second bitmap 320 based on the first size and the second size. In this way, the mirror module 112 may determine that the bit 310-7 in the first bitmap 310 corresponds to a bit 320-4 in the second bitmap 320, and the bits 310-12 and 310-13 in the first bitmap 310 correspond to a bit 320-8 in the second bitmap 320. (i.e., compressed bit 320-8 is associated with areas 310-12 and 310-13 marked as dirty) (see column 7, lines 1-22).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by McDermott et al. and Agrawal et al. to include the above mentioned to improve data consistency (see Yang, column 3, line 45-67).
With respect claim 7, McDermott et a. does not teaches indicating with a single compressed dirty tracking bit that all portions of the cache line are modified.
However, Agrawal et al. teaches wherein section status indicator bit S associated with a given section of the N sections may indicate whether the given section has dirty data or not (e.g., when the section corresponds to a BDP) (i.e., this can be interpreted as if all the portions/line are dirty the status indicator bit S will also be set) (see paragraph 88).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by McDermott et al. to include the above mentioned to significantly improve (e.g., reduce) bandwidth usage (see Agrawal, paragraph 120).
With respect claim 13, McDermott et al. and Agrawal et al. do not teach wherein each compressed dirty tracking bit indicates a range of one or more portions of the cache line that are modified.
Yang et al. teaches wherein first bitmap 310 may include N bits 310-1, 310-2…, 310-N corresponding to the N storage areas respectively, where the shaded bits 310-3, 310-7, 310-12 and 310-13 are marked as “dirty” to indicate that data in the storage areas corresponding to these bits is to be synchronized to the second storage device 120…the mirror module 112 may convert the first bitmap 310 into the second bitmap 320 based on the first size and the second size. In this way, the mirror module 112 may determine that the bit 310-7 in the first bitmap 310 corresponds to a bit 320-4 in the second bitmap 320, and the bits 310-12 and 310-13 in the first bitmap 310 correspond to a bit 320-8 in the second bitmap 320. (i.e., compressed bit 320-8 is associated with areas 310-12 and 310-13 marked as dirty) (see column 7, lines 1-22).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by McDermott et al. and Agrawal et al. to include the above mentioned to improve data consistency (see Yang, column 3, line 45-67).
Allowable Subject Matter
Claims 2-5, 9-12 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 02/17/2026 have been fully considered but they are not persuasive.
Applicant’s representative argues, in pages 5-6, that McDermott does not teach "assigning a dirty tracking bit for each byte of a cache line that is modified while the cache line is stored at a cache and not yet propagated to another cache or memory," as recited in claim 1. Applicant’s representative argues that McDermott does not disclose assigning a dirty tracking bit for each byte of a cache line; and instead, McDermott discloses dirty tracking at a coarser granularity than a byte, namely at the cache-line level and, at most, at a dword level.
In response: The examiner disagrees. McDermott teaches wherein each 16 byte cache line also includes four dirty bits (one dirty bit per dword) to allow for write-back mode operations.... The four dirty bits allow for dirty locations to be marked on a dword (32 bit) basis) (see column 6, lines 66-77 and column 7, lines 1-5). The four dirty bits allowing for dirty locations to be marked on a dword (32 bit) basis is being interpreted as 1 dirty bit per 1 byte (8 bits) of the cache line.
Applicant’s representative argues, in page 6, that Agrawal does not teach "compressing contiguous dirty tracking bits for each portion of a plurality of portions of the cache line prior to evicting the cache line from the cache" as recited in claim 1. Applicant’s representative argues that Agrawal operates at the page level, not at the cache line level, and the compression is not performed prior to cache eviction.
In response: The examiner disagrees. As the response above, McDermott teaches four dirty bits allowing for dirty locations to be marked on a dword (32 bit) basis (i.e., 1 dirty bit per 1 byte (8 bits) of the cache line); and uses the NDIRTY array 331, as well as PDIRTY bits 332, to reduce the number of cycles required to complete the flush/eviction (see column 9, lines 7-17). However, McDermott does not teach compressing contiguous dirty tracking bits for each portion of a plurality of portions of the cache line. Agrawal et al. teaches metadata associated with a BMP and/or a BDP section may be run-length encoded before (e.g., before or during) the transferring of the metadata to the live migration server 100b… migration controller 210b may run length encode the 88 bits by counting consecutive 1's and 0's. The example bitmap XBM may have 16 1's, followed by 32 0's, followed by 40 1's. Because only two values (1's and 0's) exist for the bitmap, a marker MKR may indicate a transition between values. Thus, the 11 bytes of metadata associated with the example bitmap XBM may be compressed to 5 bytes of run length encoded metadata RLEMD (e.g., two bytes per marker MKR and one byte per count of 16, 32, and 40) (i.e., contiguous dirty bits may be encoded/compressed) (see paragraphs 90 and 120-121).
Applicant’s arguments, see page 7, filed 02/17/2026, with respect to rejection of claims 2-3, 9-10 and 16-17 have been fully considered and are persuasive. The rejection of the claims has been withdrawn.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Garnett et al. (US2002/0066049) teaches wherein dirty indicators are stored in groups with each group having associated therewith a validity indicator computed from the dirty indicator values of the group.
Tan (US2006/0184745) teaches wherein a tag array includes a cache-line dirty bit associated with each cache line and the data array includes a plurality of dirty bits for each cache line. The plurality of dirty bits comprises one sub-line dirty bit for each sub-line (see paragraph 6).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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