Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are pending.
This is in response to communications filed on 6/18/26.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 2-4 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claims 2-4 depend on claim 1. Claim 1 recites “there is at least one batch-processed item” and “the at least one power-on state all indicate success”. Claim 2-4 recite limitations that are inconsistent with parent claim 1. Parent claim 1 requires “there is at least one batch-processed item”, while claim 2 requires “there is no batch processed item”. Parent claim 1 requires “the at least one power-on state all indicate success”, while claim 3 and 4 require “not all of the at least one power-on state indicate success”.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-4, 7-8 is/are rejected under 35 U.S.C. 103 as being obvious over Suzhou (CN116088952; cited in IDS; translation is provided), in view of Gan (US Patent Application Publication 2024/0119023)
The applied reference (Gan et al) has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
For claim 1, Suzhou (CN116088952) teaches the following limitations: A method of managing power supply for a server system (lines 1-5 of page 1 – controlling startup of hard disk of server), the server system including a mainboard and a system board (Fig 3; left side board is the motherboard and right side board is the system board; Page 1 mentions main board or power board and Page 6 mentions description of Fig 2 – main board side and hard disk backplane side – the hard disk backplane includes a board), the mainboard being electrically connected to the system board (Fig 2 and Fig 3), the mainboard including a programmable logic device (CPLD shown on the left side of Fig 3; main board CPLD is explained in page 7 first paragraph; mainboard stores table 1 mentioned in page 8) that stores first power-on sequence data for the mainboard (first power on data is the number of backplanes connected to the mainboard; Fig 2 shows the BP_PRSNT_N pin to the mainboard and sending the information about backplane to the motherboard; main board CPLD stores the information about backplanes; Page 7 provides the description about table, backplane ID, backplane presence) and second power-on sequence data for the system board (number of hard disks connected to each backplane shown in Fig 3; Page 7, Page 9 - 11; step S604 – CPLD has the information on number of hard disks connected to the backplanes), the first power-on sequence data containing a plurality of first power-on items that are related to supplying power to the mainboard (the number of backplanes connected to the mainboard are the plurality of first power-on items; the enables signals are activated based on the connected backplanes; Fig 3 shows the number of backplanes; Page 8 mentions CPLD includes table storing the backplanes information; Page 11 mentions backplane ID, whether connected are stored in CPLD/table), the second power-on sequence data containing a plurality of second power-on items (number of hard disks on each backplane; the hard disks are to be powered on the mainboard; Fig 6 and page 10-11) that are related to supplying power to the system board (the backplane or system board connects the plurality of hard disks to power on the disks; the main board stores the number of hard disks so as to power on sequential through P_12V_EFUSE_En as shown in Fig 3; Page 11), the method being to be implemented by the programmable logic device of the mainboard (CPLD on the mainboard performs the power sequencing; mainboard CPLD is explained in Page 6, Page 8, Page 10-11, Fig 2 and Fig 3 shows the CPLD on main board) and comprising steps of: A) selecting a to-be-processed item from among the first power-on items of the first power-on sequence data (selecting the first interface for first backplane as the to-be processed item; Page 6 and Page 9 mentions how the backplane is selected to compute the power on time; thus the first backplane is selected as to be processed item), and determining whether there is at least one batch-processed item among the second power-on items according to the to-be-processed item (the backplane and the corresponding interface is the to be processed item; whether any hard disk presents on the first backplane; each hard disk is a batch processed item; Page 8 mentions CPLD can obtain the number of hard disks on the connected backplane based on BP_ID and table; page 7 and page 11 mentions X is the number of hard disks on a backplane; thus determine there is at least one hard disk among the hard disks on the table of CPLD according to the target backplane); B) in response to determining that there is at least one batch-processed item among the second power-on items (Page 8 mentions CPLD can obtain the number of hard disks on the connected backplane based on BP_ID and table; page 7 and page 11 mentions X is the number of hard disks on a backplane; thus determine there is at least one hard disk among the hard disks on the table of CPLD according to the target backplane), performing a power-on procedure that is related to the to-be-processed item (step 606 mentioned in Fig 6 and corresponding description in page 11 mention that main board CPLD powers sequentially the power the backplane interfaces).
Suzhou (CN116088952) does not teach the following limitations: transmitting to the system board a power- on notification for the system board to perform at least one power-on procedure related respectively to the at least one batch-processed item; C) transmitting to the system board a result request for a power-on result of the at least one power-on procedure related to the at least one batch-processed item; D) in response to receipt of the power-on result that is responded by the system board to the result request and that contains at least one power-on state corresponding respectively to the at least one batch-processed item, determining whether the at least one power-on state all indicates success in the at least one power-on procedure related to the at least one batch-processed item; and E) in response to determining it is determined that the at least one power-on state all indicate indicates success, repeating steps A) to D) until all of the first power-on items of the first power-on sequence data have been selected.
Gan et al teach the following limitations: transmitting to the system board a power- on notification for the system board to perform at least one power-on procedure related respectively to the at least one batch-processed item (step 603 and 604 of Fig 2; step 606 and 607 of Fig 3; [0025][0028]; secondary power on stage includes the power-on procedure of the batch processed item) ; C) transmitting to the system board a result request for a power-on result of the at least one power-on procedure related to the at least one batch-processed item (step 606 and 607 of Fig 3 sends instructions and later stage report is sent by secondary PLD; thus sending instructions of includes the result request for power on result of the one power on procedure of the secondary power on stage); D) in response to receipt of the power-on result that is responded by the system board to the result request (step 608 of Fig 3; [0030]) and that contains at least one power-on state corresponding respectively to the at least one batch-processed item ([0029] – successful completion of the secondary power stage; ), determining whether the at least one power-on state all indicates success in the at least one power-on procedure related to the at least one batch-processed item ([0029][0032] - successful completion of the secondary power stage); and E) in response to determining it is determined that the at least one power-on state all indicate indicates success, repeating steps A) to D) until all of the first power-on items of the first power-on sequence data have been selected (step 611 in Fig 3 to step 615; [0038]; the next iteration for another first power on item of the first power sequence is performed).
It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to combine the teachings of Suzhou and Gan to include the notifications, requests and responses between the two boards so the power on procedure can be performed effectively and accurately. Gan et al performs the joint power on between the two boards ([0025][0027] and [0039]) so that power sequences are synchronized. This synchronization provides a functionally stable system.
For claim 2, Suzhou (CN116088952) teaches the following limitations: when it is determined that there is no batch-processed item among the second power-on items (if no hard disks on the backplane present and X is “0” on page 7 and page 11), performing the power-on procedure that is related to the to-be-processed item without transmitting the power-on notification to the system board (the power on procedure for enable signals are performed based on the number of disks as shown in Page 11; Page 6-7 mentions that the both hard disks and backplanes are sequentially powered; in absence of hard disk no power is supplied to hard disk; thus there will no power on notification when hard disk is not there), and repeating the steps of selecting another one of the first power-on items as another to-be-processed item (another backplane is selected; Page 11), and determining whether at least another one second to-be-processed item exists (determines the number of hard disks connected thereto; Page 11), until all of the first power-on items of the entry of first power-on sequence data have been selected (Page 11 shows the completion of all backplanes; Fig 6).
For claim 3, Gan teaches in response to determine that not all of the at least one power- on state indicate success, for each of the at least one power-on state that does not indicate success (Gans step 611 of Fig 3), recording a corresponding one of the at least one batch-processed item that corresponds to the power-on state ([0029] – a stream of bits where each bit represents a current stage is a success or failure).
For claim 4, Sozhou teaches the BP_ID pins are the indicators for the second power on items (Page 8 and Page 11; Fig 3 Sozhou). Gan further teaches that the method further comprising: in response to determining that not all of the at least one power- on state indicate success, for each of the at least one power-on state that does not indicate success, transmitting an indicator command to a corresponding one of the indicators to activate the corresponding one of the indicators, the corresponding one of the indicators corresponding to the second power-on item that is determined as one of the at least one batch-processed item which corresponds to the power-on state not indicating success ([0029] bit is the indicator of success/failure of the current secondary power on stage in the stage report; the main board receives the stage report Fig 3; for failure the indicator 0 is transmitted; the current secondary stage mentioned in [0029] represents second power-on item that is determined as one of the at least one batch-processed item).
For claim 7, Suzhou Page 1 mentions the power supply. Fig 1 and Fig 3 shows the connection that must be realized before detecting whether batch process items exist by BP_ID and BP_PRSNT_N. Thus, power must be supplied before step A).
For claim 8, Suzhou (CN116088952) teaches the following limitations: the first power-on items respectively corresponding to a plurality of first power-on voltages (Fig 3 shows that voltages are 12V on main board), the second power-on items respectively corresponding to a plurality of second power-on voltages (Fig 3 shows the voltages are 12V and 5 V on the backplane), wherein, in step A), each of the at least one batch-processed item is one of the second power-on items corresponding to the second power-on voltage that is not greater than the first power-on voltage corresponding to the first power-on item which is selected as the to-be-processed item (12 V and 5 V for the hard disk (or batch processed item) is not greater than voltage of the to be processed item (backplane voltage 12V)).
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzhou (CN116088952; cited in IDS; translation is provided), in view of Gan (US Patent Application Publication 2024/0119023), further in view of Li et al (US patent Application Publication 2025/0165422).
For claim 5, Suzhou (CN116088952) teaches transmitting power to the main board and system board (Fig 3; standby power before powering the hard disks). The main board receives the power-on sequence data through BP_ID and BP_PRSNT_N as shown in Fig 3. This data is received (i.e., stored to calculate the power on time) by CPLD. Suzhou (CN116088952) does not explicitly mention about the data request to system board. Instead, the connection realizes the acquire operation (Fig 5; Page 9), which can be taken as the data request. Gans et al teach the request and receiving response (603 and 604 of Fig 2). However, for further clarification, Li teaches a system where a board request data during power on sequence ([0040]; Fig 3). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide the data request to the system board, since that ensures the correct communication between the boards. Suzhou (CN116088952) teaches communication (Page 8), which would further assist communications between two boards.
For claim 6, Suzhou teaches Page 1 mentions the power supply. Fig 1 and Fig 3 shows the connection that must be realized before detecting whether batch process items exist by BP_ID and BP_PRSNT_N. Thus, power must be supplied before step A).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzhou (CN116088952; cited in IDS; translation is provided), in view of Gan (US Patent Application Publication 2024/0119023), further in view of Huang (US Patent Application Publication 20210209983) further in view of Li et al (US Patent Application Publication 2023/0318871).
For claim 9, Suzhou (CN116088952) teaches wherein, in step A), each of the at least one batch-processed item is one of the second power-on items corresponding to the second power-on voltage that is not greater than the first power-on voltage corresponding to the first power-on item which is selected as the to-be-processed item (12 V and 5 V for the hard disk (or batch processed item) is not greater than voltage of the to be processed item (backplane voltage 12V)). Suzhou teaches ordering based on duration (page 10 – sequentially sorted), not based on voltage value. Suzhou in view of Gan does not explicitly mention second power on voltage is greater than the first power on voltage corresponding to a subsequent one of the power on item. Organizing voltage levels in sorted order is known in the art (Huang et al [0015][004]). Also, the voltage levels for different components can be different based on the component power consumption (Fig 5; Fig 2; Li et al). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to order the voltage values in descending order and provide the voltage level to components that greater/less than the voltage level provided to other components for correct operation of the components.
For claim 10, Suzhou (CN116088952) teaches the first power-on items respectively corresponding to a plurality of first power-on voltages (Fig 3 shows that voltages are 12V on main board), the second power-on items respectively corresponding to a plurality of second power-on voltages (Fig 3 shows the voltages are 12V and 5 V on the backplane)wherein, in step A), each of the at least one batch-processed item is one of the second power-on items corresponding to the second power-on voltage that is not greater than the first power-on voltage corresponding to the first power-on item which is selected as the to-be-processed item (12 V and 5 V for the hard disk (or batch processed item) is not greater than voltage of the to be processed item (backplane voltage 12V)). Suzhou teaches ordering based on duration (page 10 – sequentially sorted), not based on voltage value. Suzhou in view of Gan does not explicitly mention second power on voltage is greater than the first power on voltage corresponding to a subsequent one of the power on item. Organizing voltage levels in sorted order is known in the art (Huang et al [0015]). Also, the voltage levels for different components can be different based on the component power consumption (Fig 5; Fig 2 Li et al). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to order the voltage values in descending order and provide the voltage level to components that greater/less than the voltage level provided to other components for correct operation of the components.
Response to Arguments
Applicant’s arguments have been fully considered. Based on the arguments and amendment, the new grounds of rejection is provided.
Applicant mentioned that the use of “in response to determining” language, as distinguished from “when” or “if”, establishes an affirmative condition that requires the recited determination to occur and the subsequent steps to be performed in response to thereto. Therefore, according to the applicant, steps B) through E) of amended claim 1 are no longer contingent; they are required method steps that must be given patentable weight during examination (remarks, page 6 -7).
Examiner considered these statements as admission and interpreted that the “in response to determining” has been positively recited in claim 1, which are not conditional. Examiner agreed that the reference Suzhou does not teach the limitations of step B), C), D) of claim 1 as argued by the applicant. The newly cited reference is relied upon for these steps.
Since applicant provided the statement that the “in response to” language establishes the affirmative condition, claims 2-4 have been rejected under 35 USC 112 (d), because these claims recite limitations that are not consistent with parent claim 1. Parent claim 1 requires “there is at least one batch-processed item”, while claim 2 requires “there is no batch processed item”. Parent claim 1 requires “the at least one power-on state all indicate success”, while claim 3 and 4 require “not all of the at least one power-on state indicate success”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175
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