Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are pending.
This is in response to communications filed on 9/19/24.
Claim Interpretation
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent is not met. If the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed. See Ex Parte Schulhauser. For example, assume a method claim requires step A if a first condition happens and step Bif a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B (MPEP 2111.04).
Claim 1 recite the conditional limitations “B) when it is determined that there is at least one batch-processed item among the second power-on items” which are not required conditions to be occurred. The BRI does not include the conditions and associated functions based on the conditions when method can be practiced without conditions being met. Applicant’s disclosure Fig 2 shows the condition in step 206. Based on the determination steps, the outcome can either be “No” or “Yes”. Steps B) through E) corresponds to steps 207 to 213 in Fig 2 which follow the “YES” path. Claim 2’s limitations when it is determined that there is no batch-processed item among the second power-on items corresponds to step 214 of Fig 2. BRI includes either B) through E) steps of claim 1 or claim 2 as these are mutually exclusive steps as shown in Fig 2 of the applicant’s disclosure. Claims 3 and 4 recite the step 211 and the corresponding functions. Therefore, the “no” branch of claim 2 does not include the limitations corresponds to claim 3 and claim 4. For the rest of the action, the examination is performed claim 1 with step A only as the steps B) through E) are not required when there is no batch processed items.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-8 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Suzhou (CN116088952; cited in IDS; translation is provided)
For claim 1, Suzhou (CN116088952) teaches the following limitations: A method of managing power supply for a server system (lines 1-5 of page 1 – controlling startup of hard disk of server), the server system including a mainboard and a system board (Fig 3; left side board is the motherboard and right side board is the system board; Page 1 mentions main board or power board and Page 6 mentions description of Fig 2 – main board side and hard disk backplane side – the hard disk backplane includes a board), the mainboard being electrically connected to the system board (Fig 2 and Fig 3), the mainboard including a programmable logic device (CPLD shown on the left side of Fig 3; main board CPLD is explained in page 7 first paragraph; mainboard stores table 1 mentioned in page 8) that stores first power-on sequence data for the mainboard (first power on data is the number of backplanes connected to the mainboard; Fig 2 shows the BP_PRSNT_N pin to the mainboard and sending the information about backplane to the motherboard; main board CPLD stores the information about backplanes; Page 7 provides the description about table, backplane ID, backplane presence) and second power-on sequence data for the system board (number of hard disks connected to each backplane shown in Fig 3; Page 7, Page 9 - 11; step S604 – CPLD has the information on number of hard disks connected to the backplanes), the first power-on sequence data containing a plurality of first power-on items that are related to supplying power to the mainboard (the number of backplanes connected to the mainboard are the plurality of first power-on items; the enables signals are activated based on the connected backplanes; Fig 3 shows the number of backplanes; Page 8 mentions CPLD includes table storing the backplanes information; Page 11 mentions backplane ID, whether connected are stored in CPLD/table), the second power-on sequence data containing a plurality of second power-on items (number of hard disks on each backplane; the hard disks are to be powered on the mainboard; Fig 6 and page 10-11) that are related to supplying power to the system board (the backplane or system board connects the plurality of hard disks to power on the disks; the main board stores the number of hard disks so as to power on sequential through P_12V_EFUSE_En as shown in Fig 3; Page 11), the method being to be implemented by the programmable logic device of the mainboard (CPLD on the mainboard performs the power sequencing; mainboard CPLD is explained in Page 6, Page 8, Page 10-11, Fig 2 and Fig 3 shows the CPLD on main board) and comprising steps of: A) selecting a to-be-processed item from among the first power-on items of the first power-on sequence data (selecting the first interface for first backplane as the to-be processed item; Page 6 and Page 9 mentions how the backplane is selected to compute the power on time; thus the first backplane is selected as to be processed item), and determining whether there is at least one batch-processed item among the second power-on items according to the to-be-processed item (the backplane and the corresponding interface is the to be processed item; whether any hard disk presents on the first backplane; each hard disk is a batch processed item; Page 8 mentions CPLD can obtain the number of hard disks on the connected backplane based on BP_ID and table; page 7 and page 11 mentions X is the number of hard disks on a backplane; thus determine there is at least one hard disk among the hard disks on the table of CPLD according to the target backplane) ; B) when it is determined that there is at least one batch-processed item among the second power-on items, performing a power-on procedure that is related to the to-be-processed item and transmitting to the system board a power-on notification for the system board to perform at least one power-on procedure related respectively to the at least one batch-processed item (as explained above, BRI does not require the steps when no batch processed items, which is realized when there is no hard disk presents on the first interface; thus, step B) to E) are not part of BRI).
For claim 2, Suzhou (CN116088952) teaches the following limitations: when it is determined that there is no batch-processed item among the second power-on items (if no hard disks on the backplane present and X is “0” on page 7 and page 11), performing the power-on procedure that is related to the to-be-processed item without transmitting the power-on notification to the system board (the power on procedure for enable signals are performed based on the number of disks as shown in Page 11; Page 6-7 mentions that the both hard disks and backplanes are sequentially powered; in absence of hard disk no power is supplied to hard disk; thus there will no power on notification when hard disk is not there), and repeating the steps of selecting another one of the first power-on items as another to-be-processed item (another backplane is selected; Page 11), and determining whether at least another one second to-be-processed item exists (determines the number of hard disks connected thereto; Page 11), until all of the first power-on items of the entry of first power-on sequence data have been selected (Page 11 shows the completion of all backplanes; Fig 6).
For claim 3, BRI does not include the corresponding limitations, as method can be practiced when there is no batch processed items.
For claim 4, the BP_ID pins are the indicators for the second power on items (Page 8 and Page 11; Fig 3). BRI does not include the corresponding limitations, as method can be practiced when there is no batch processed items.
For claim 7, Page 1 mentions the power supply. Fig 1 and Fig 3 shows the connection that must be realized before detecting whether batch process items exist by BP_ID and BP_PRSNT_N. Thus, power must be supplied before step A).
For claim 8, Suzhou (CN116088952) teaches the following limitations: the first power-on items respectively corresponding to a plurality of first power-on voltages (Fig 3 shows that voltages are 12V on main board), the second power-on items respectively corresponding to a plurality of second power-on voltages (Fig 3 shows the voltages are 12V and 5 V on the backplane), wherein, in step A), each of the at least one batch-processed item is one of the second power-on items corresponding to the second power-on voltage that is not greater than the first power-on voltage corresponding to the first power-on item which is selected as the to-be-processed item (12 V and 5 V for the hard disk (or batch processed item) is not greater than voltage of the to be processed item (backplane voltage 12V)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzhou (CN116088952; cited in IDS; translation is provided), further in view of Li et al (US patent Application Publication 2025/0165422).
For claim 5, Suzhou (CN116088952) teaches transmitting power to the main board and system board (Fig 3; standby power before powering the hard disks). The main board receives the power-on sequence data through BP_ID and BP_PRSNT_N as shown in Fig 3. This data is received (i.e., stored to calculate the power on time) by CPLD. Suzhou (CN116088952) does not explicitly mention about the data request to system board. Instead, the connection realizes the acquire operation (Fig 5; Page 9), which can be taken as the data request. However, for further clarification, Li teaches a system where a board request data during power on sequence ([0040]; Fig 3). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide the data request to the system board, since that ensures the correct communication between the boards. Suzhou (CN116088952) teaches communication (Page 8), which would further assist the communications between two boards.
For claim 6, Suzhou teaches Page 1 mentions the power supply. Fig 1 and Fig 3 shows the connection that must be realized before detecting whether batch process items exist by BP_ID and BP_PRSNT_N. Thus, power must be supplied before step A).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzhou (CN116088952; cited in IDS; translation is provided), further in view of Huang (US Patent Application Publication 20210209983) further in view of Li et al (US Patent Application Publication 2023/0318871).
For claim 9, Suzhou (CN116088952) teaches wherein, in step A), each of the at least one batch-processed item is one of the second power-on items corresponding to the second power-on voltage that is not greater than the first power-on voltage corresponding to the first power-on item which is selected as the to-be-processed item (12 V and 5 V for the hard disk (or batch processed item) is not greater than voltage of the to be processed item (backplane voltage 12V)). Suzhou teaches ordering based on duration (page 10 – sequentially sorted), not based on voltage value. Suzhou does not explicitly mention second power on voltage is greater than the first power on voltage corresponding to a subsequent one of the power on item. Organizing voltage levels in sorted order is known in the art (Huang et al [0015][004]). Also, the voltage levels for different components can be different based on the component power consumption (Fig 5; Fig 2; Li et al). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to order the voltage values in descending order and provide the voltage level to components that greater/less than the voltage level provided to other components for correct operation of the components.
For claim 10, Suzhou (CN116088952) teaches the first power-on items respectively corresponding to a plurality of first power-on voltages (Fig 3 shows that voltages are 12V on main board), the second power-on items respectively corresponding to a plurality of second power-on voltages (Fig 3 shows the voltages are 12V and 5 V on the backplane)wherein, in step A), each of the at least one batch-processed item is one of the second power-on items corresponding to the second power-on voltage that is not greater than the first power-on voltage corresponding to the first power-on item which is selected as the to-be-processed item (12 V and 5 V for the hard disk (or batch processed item) is not greater than voltage of the to be processed item (backplane voltage 12V)). Suzhou teaches ordering based on duration (page 10 – sequentially sorted), not based on voltage value. Suzhou does not explicitly mention second power on voltage is greater than the first power on voltage corresponding to a subsequent one of the power on item. Organizing voltage levels in sorted order is known in the art (Huang et al [0015]). Also, the voltage levels for different components can be different based on the component power consumption (Fig 5; Fig 2 Li et al). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to order the voltage values in descending order and provide the voltage level to components that greater/less than the voltage level provided to other components for correct operation of the components.
Conclusion
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/FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175