DETAILED ACTION
1. It is hereby acknowledged that 18/890429 the following papers have been received and placed of record in the file: Remark date 09/19/24
Claim Objections
2. Claims 1-20 are objected to because of the following informalities:
Claims 1 and 17 states,…. state of at least one of the buffer and the port queue.
…
However further in the claims seems to merely mentions the buffer and not the port queue. This leaves one questioning if the port queue was selected as an option would the remaining limitation need to be considered since it is applying to the buffer.
Claims 1 and 17 further states… determines a state of at least one of a buffer and a port queue …
State of a buffer and port queue is vague and can be considered to merely being used, on, failed, load size, congested or etc… .
Claim 20 states…. determining a state of a buffer…
Like above the state of a buffer is vague and can be considered to merely being used, on, failed, or etc… .
The claim 7 recites “…buffer based on the statue of the port queue …” It is unclear what is meant by statue, this may be a typo instead of status. Appropriate correction is required.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-20 are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over patent application ( 1,212,6541 B2) claims 1-23. Although the conflicting claims are not identical, they are not patentably distinct from each other because they both deal with a buffer for temporarily storing one or more packets. The main difference is the instant application (18/890429) is based on state of at least one of the buffer or port queue while patent application (12126541) explains one pointer is adjusted as part of truncating the packet to release at least one cell in the buffer thereby allocating more buffer space to storage of other packets. These differences would be obvious for the purpose of improving managing storage capacity or reduction of data in memory.
Instant Application (18/890429)
Patent Application ( 1,212,6541 B2)
1. A device, comprising: circuitry that determines a state of at least one of a buffer and a port queue used for temporarily storing one or more packets and, based on the state of at least one of the buffer and the port queue, truncates the one or more packets thereby reducing a size of the one or more packets prior to storing the one or more packets in the buffer.
1. A networking device, comprising: an interface that receives one or more packets; a buffer that temporarily stores the one or more packets prior to being transmitted by the networking device; and circuitry that evaluates a packet received at the interface and, based on the evaluation of the packet, truncates the packet thereby reducing a size of the packet prior to storing the packet in the buffer, wherein the packet is initially stored in the buffer prior to truncation and at least one pointer is adjusted as part of truncating the packet to release at least one cell in the buffer thereby allocating more buffer space to storage of other packets.
The remaining claims are similar to instant application.
Claim Rejections - 35 USC § 102
4.The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1, 6-14, and 17-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matthews et al. (US 10,313,255).
Regarding claim 1. Mathews teaches a device, comprising:
circuitry that determines a state of at least one of a buffer and a port queue used for temporarily storing one or more packets and, (see Mathews Fig. 1, 130, see col. 8, lines 63-65, device 100 may store packets 105 in temporary memory structures referred to as buffers 130 while the packets 105 are waiting to be processed, see column 10 line 12-25, column 20 lines 10-20 explains overload)
based on the state of at least one of the buffer and the port queue, (see Mathews Fig. 1 column 15 lines 58-61 explains… In an embodiment, instead of being dropped completely, the packet 105 may likewise be forwarded to the special visibility queue 142 and provided with a drop visibility tag. For instance, the packet 105 may be linked to a special visibility queue 142, or even the original queue 142, and include a special tag indicating that a problem was encountered when trying to assign the packet 105 to the queue. In an embodiment, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload are sent to the downstream logic.…column 8 lines 63-65)
truncates the one or more packets thereby reducing a size of the one or more packets prior to storing the one or more packets in the buffer. (see Mathews column Fig. 1, 130, 150; 15 lines 58-61 explains… In an embodiment, instead of being dropped completely, the packet 105 may likewise be forwarded to the special visibility queue 142 and provided with a drop visibility tag. For instance, the packet 105 may be linked to a special visibility queue 142, or even the original queue 142, and include a special tag indicating that a problem was encountered when trying to assign the packet 105 to the queue. In an embodiment, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload are sent to the downstream logic.…column 8 lines 63-65)
Regarding claim 6, Mathews taught the device of claim 1, as described above. Mathews further teaches wherein a decision is made to truncate the one or more packets prior to storing the one or more packets in the buffer based on the status of the buffer. (see Mathews fig. 1, 150A packet processor, see col. 15, lines 52-61, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload, see column 10 line 12-25, column 20 lines 10-20 explains overload).
Regarding claim 7, Mathews taught the device of claim 1, , as described above. Mathews further teaches wherein a decision is made to truncate the one or more packets prior to storing the one or more packets in the buffer based on the statue of the port queue. (see Mathews fig. 1, 150A packet processor, see col. 15, lines 58-61, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload)
Regarding claim 8, Mathews taught the device of claim 1, as described above. Mathews further teaches wherein a decision is made to truncate the one or more packets based on the state of the buffer. (see Mathews fig. 1, 150A packet processor, see col. 15, lines 58-61, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload)
Regarding claim 9, Mathews taught the device of claim 1, as described above. Mathews further teaches wherein a decision is made to truncate the one or more packets based on the state of the port queue. (see Mathews column Fig. 1, 130, 150; 15 lines 58-61 explains… In an embodiment, instead of being dropped completely, the packet 105 may likewise be forwarded to the special visibility queue 142 and provided with a drop visibility tag. For instance, the packet 105 may be linked to a special visibility queue 142, or even the original queue 142, and include a special tag indicating that a problem was encountered when trying to assign the packet 105 to the queue. In an embodiment, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload are sent to the downstream logic.…column 8 lines 63-65)
Regarding claim 10, Mathews taught the device of claim 1, as described above. Mathews further teaches wherein a decision is made to truncate the one or more packets based on both the state of the buffer and the state of the port queue. (see Mathews column Fig. 1, 130, 150; 15 lines 58-61 explains… In an embodiment, instead of being dropped completely, the packet 105 may likewise be forwarded to the special visibility queue 142 and provided with a drop visibility tag. For instance, the packet 105 may be linked to a special visibility queue 142, or even the original queue 142, and include a special tag indicating that a problem was encountered when trying to assign the packet 105 to the queue. In an embodiment, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload are sent to the downstream logic.…column 8 lines 63-65)
Regarding claim 11, Mathews taught the device of claim 1, as described above. Mathews further teaches wherein the one or more packets are initially stored in the buffer prior to truncation and at least one pointer is adjusted as part of truncating the one or more packets to release at least one cell in the buffer thereby allocating more buffer space to storage of other packets. ( see Mathews col 15, lines 55-61, the packet 105 may be linked to a special visibility queue 142, or even the original queue 142, and include a special tag indicating that a problem was encountered when trying to assign the packet 105 to the queue. In an embodiment, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload are sent to the downstream logic.)
Regarding claim 12, Mathews taught the device of claim 1, as described above. Mathews further teaches wherein the port queue facilitates retrieval of the one or more packets from the buffer, the device further comprising:
an interface that receives one or more packets; and
an output port, wherein the circuitry reads the truncated one or more packets from the buffer and causes the truncated one or more packets to be transmitted via the output port. (see Mathews fig. 1, 190, egress port, see col. 7, lines 33-42, packet processing component 150 is configured to perform one or more processing tasks with a packet 105. By way of example, such tasks may include, without limitation, sending the packet 105 out a specified port 190, applying rules or policies to the packet (e.g. traffic flow control, traffic shaping, security, etc.), manipulating the packet 105, discarding a packet 105, locating forwarding information for a packet 105, annotating or tagging a packet, or simply determining a next processing component 150 to which the packet 105 should be sent).
Regarding claim 13, Mathews taught the device of claim 1, as described above. Mathews further teaches further comprising: a multiplexer, wherein the circuitry reads the truncated one or more packets from the buffer and causes the truncated one or more packets to be provided to the multiplexer. ( see Mathews fig. 1, 150, see col. 7, lines 20-32, Device 100 comprises various packet processing components 150. A packet processing component 150 (multiplex packet processor) may be or include, for example, a Field Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), or a general purpose processor executing software-based instructions. The packet processor 150 reads or accepts packets 105 as input, and determines how to handle the packets 105 based on various logic implemented by the packet processor 150. In an embodiment, a first set of one or more packet processing components 150 may form a RX component (or pre-buffer manager), and a second set of one or more packet processing components 150 may form a TX component (or post-queue manager).).
Regarding claim 14, Mathews taught the device of claim 1, as described above. Mathews further teaches wherein the circuitry analyzes the one or more packets and makes a routing decision based on the analysis of the one or more packets. ( see fig. 1, 150, see col. 7, lines 20-32, Device 100 comprises various packet processing components 150. A packet processing component 150 (multiplex packet processor) may be or include, for example, a Field Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), or a general purpose processor executing software-based instructions. The packet processor 150 reads or accepts packets 105 as input, and determines how to handle the packets 105 based on various logic implemented by the packet processor 150. In an embodiment, a first set of one or more packet processing components 150 may form a RX component (or pre-buffer manager), and a second set of one or more packet processing components 150 may form a TX component (or post-queue manager).).
Regarding claim 17, Mathews teaches a system, comprising: a device that receives one or more packets;(see Mathews column 20 lines 31-50 explains receiving packets) and
a controller that determines a state of at least one of a buffer and a port queue and, (see Mathews Fig. 1, 130, see col. 8, lines 63-65, device 100 may store packets 105 in temporary memory structures referred to as buffers 130 while the packets 105 are waiting to be processed, see column 10 line 12-25, column 20 lines 10-20 explains overload) ) based on the state of at least one of the buffer and the port queue, , (see Mathews Fig. 1 column 15 lines 58-61 explains… In an embodiment, instead of being dropped completely, the packet 105 may likewise be forwarded to the special visibility queue 142 and provided with a drop visibility tag. For instance, the packet 105 may be linked to a special visibility queue 142, or even the original queue 142, and include a special tag indicating that a problem was encountered when trying to assign the packet 105 to the queue. In an embodiment, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload are sent to the downstream logic.…column 8 lines 63-65)
truncates the one or more packets thereby reducing a size of the one or more packets prior to storing the one or more packets in the buffer. (see Mathews column Fig. 1, 130, 150; 15 lines 58-61 explains… In an embodiment, instead of being dropped completely, the packet 105 may likewise be forwarded to the special visibility queue 142 and provided with a drop visibility tag. For instance, the packet 105 may be linked to a special visibility queue 142, or even the original queue 142, and include a special tag indicating that a problem was encountered when trying to assign the packet 105 to the queue. In an embodiment, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload are sent to the downstream logic.…column 8 lines 63-65)
Regarding claim 18, Mathews taught the system of claim 17, as described above. Mathews further teaches wherein the controller is provided as part of the device, wherein the device comprises the buffer and the port queue, and wherein the port queue facilitates retrieval of the one or more packets from the buffer. (see Mathews column 10 line 12-25, column 20 lines 10-20 explains buffer and queue)
Regarding claim 19, Mathews taught the system of claim 17, as described above. Mathews further teaches wherein a decision is made to truncate the one or more packets based on both the state of the buffer and the state of the port queue. (see Mathews fig. 1, 150A packet processor, column 10 line 12-25, column 20 lines 10-20 explains buffer and queue, col. 15, lines 58-61, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload,)
Regarding claim 20, Mathews teaches a method, comprising: receiving a packet; determining a state of a buffer that will store at least a portion of the packet; (see Mathews Fig. 1, 130, see col. 8, lines 63-65, device 100 may store packets 105 in temporary memory structures referred to as buffers 130 while the packets 105 are waiting to be processed, see column 10 line 12-25, column 20 lines 10-20 explains overload. column 15 lines 58-61 explains… In an embodiment, instead of being dropped completely, the packet 105 may likewise be forwarded to the special visibility queue 142 and provided with a drop visibility tag. For instance, the packet 105 may be linked to a special visibility queue 142, or even the original queue 142, and include a special tag indicating that a problem was encountered when trying to assign the packet 105 to the queue. In an embodiment, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload are sent to the downstream logic.…column 8 lines 63-65) based on the state of the buffer, making a truncation decision for the packet such that the packet is truncated to a smaller size prior to storing the packet in the buffer; (see Mathews Fig. 1 column 15 lines 58-61 explains… In an embodiment, instead of being dropped completely, the packet 105 may likewise be forwarded to the special visibility queue 142 and provided with a drop visibility tag. For instance, the packet 105 may be linked to a special visibility queue 142, or even the original queue 142, and include a special tag indicating that a problem was encountered when trying to assign the packet 105 to the queue. In an embodiment, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload are sent to the downstream logic.… see column 10 line 12-25, column 20 lines 10-20 explains overload) and storing the truncated packet in the buffer prior to transmitting the truncated packet with the networking device. (see Mathews column Fig. 1, 130, 150; 15 lines 58-61 explains… In an embodiment, instead of being dropped completely, the packet 105 may likewise be forwarded to the special visibility queue 142 and provided with a drop visibility tag. For instance, the packet 105 may be linked to a special visibility queue 142, or even the original queue 142, and include a special tag indicating that a problem was encountered when trying to assign the packet 105 to the queue. In an embodiment, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload are sent to the downstream logic.…column 8 lines 63-65)
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 2-5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Matthews et al. (US 10,313,255) in view of Gadelrab (US 2008/0240111),
Regarding claim 2, Mathews taught the device of claim 1, as described above. Mathews alone does not explicitly disclose these limitations however further combined with Gadelrab teaches wherein the circuitry further divides each of the one or more packets into two or more packet portions that are stored in a corresponding two or more cells in the buffer. (see Gadelrab paragraph [0010] explains….if an arriving packet length is larger than the size of associated Kernel Packet Buffer(KPB) 59, the NIC 10 divides the packet up into smaller data segments)
Therefore it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine Matthews with Gadelrab because Gadelrab invention reduces the usage of Computer Memory 20 bandwidth associated with writing data contained in the Application Payload 79 of arriving packets into the corresponding User Space Buffer(s)( see Gedelrab paragraph [0035] ).
Regarding claim 3, the modified Mathews taught the device of claim 2, wherein the one or more packets are divided prior to truncation. (see Gadelrab paragraph [0010] explains….if an arriving packet length is larger than the size of associated Kernel Packet Buffer(KPB) 59, the NIC 10 divides the packet up into smaller data segments)
Regarding claim 4, the modified Mathews taught the device of claim 2, wherein the one or more packets are divided after truncation. (see Gadelrab paragraph [0052] explains… If an arriving packet or truncated packet length is larger than the size of the associate KPB, the packet's contents are divided up into smaller parts and these parts written into multiple KPBs… )
Regarding claim 5, the modified Mathews taught the device of claim 2, wherein the truncated one or more packets occupy a number of cells in the buffer that is smaller than a number of cells that the one or more packets would occupy prior to truncation. (see Mathews fig. 1, 150A packet processor, see col. 15, lines 58-61, the packet 105 that could not be added may be truncated such that only the header and potentially a first portion of the payload. Therefore just the header and portion of payload, will occupy less cells of the packet then the original full packet without truncation)
Regarding claim 15, the modified Mathews taught the device of claim 1, , as described above. Mathews alone does not explicitly disclose these limitations however further combined with Gadelrab teaches wherein the circuitry updates a descriptor of the one or more packets to describe a length of the truncated one or more packets as stored in the buffer. (see Gadelrab [0052] The DRNIC Driver 451 informs the DRNIC 410 of the starting address and length of each KPB through a DRNIC Buffer Descriptor Data Structure 455. FIG. 9(a) shows an exemplary organization for a DRNIC Buffer Descriptor Data Structure 455. The DRNIC Driver 451 enters the starting address and length of one KPB 59 into the Buffer Field 570. ).
Therefore it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine Matthews with Gadelrab because Gadelrab invention reduces the usage of Computer Memory 20 bandwidth associated with writing data contained in the Application Payload 79 of arriving packets into the corresponding User Space Buffer(s)( see Gedelrab paragraph [0035] ).
8. Claim 16 are rejected under 35 U.S.C. 103 as being unpatentable over Matthews et al. (US 10,313,255) in view of Kung(US 11736986 B2),
Regarding claim 16, Mathews taught the device of claim 1, as described above. Mathews alone does not explicitly disclose these limitations however further combined with Kung teaches wherein the circuitry makes a decision related to a timing with which to truncate the one or more packets relative to a storage of the one or more packets in the buffer. (see Kung column 18 lines 35-40….when a timeAlignmentTimer expires: 2> if the timeAlignmentTimer is associated with the PTAG: 3> flush all HARQ buffers for all Serving Cells;…)
Therefore it would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention to combine Matthews with Kung because Kung’s invention reduces latency overhead (see column 5 lines 25-36)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gerald Smarth whose telephone number is (571) 270-1923. The examiner can normally be reached on Monday-Thursday 6am-4:30pm ET. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joseph Avellino can be reached on 571-272-3905. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GERALD A SMARTH/Primary Examiner, Art Unit 2478
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