DETAILED ACTION
The current Office Action is in response to the papers submitted 09/02/2026. Claims 1 – 20.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 8, 12, 15, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kilari et al. (Pub. No.: 2013/0326170) referred to a Kilari in view of Kern et a. (Pub. No.: US 2019/0057031).
Regarding claim 1, Kilari teaches a plurality of storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2; The Flash and RAM are both storage devices]; and
a storage controller [204, Fig 2; Paragraph 0032; The processor is a controller that controls the memory using the MMU] operatively coupled to the plurality of storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2], the storage controller [204, Fig 2] comprising a processing device [204 or 214, Fig 2; Item 204 is a processor and the MMU is a device/module that coordinates accesses to the memory running on the processor. Either can be considered a processing device] configured to:
form a data segment [502; Fig 5; The compressed MMU pages 1 – 4 together is a data segment] to be stored at one or more storage devices [103, Fig 1B; 202, Fig 2; The data is stored in flash] of the plurality of storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2];
allocate data [MMU PAGE 1, Fig 5A] of the data segment [502; Fig 5] to pages [508, Fig 5A] of the one or more storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2] based on a first page size associate with a first programming mode [Paragraphs 0035 – 0044; Figs 4 – 5A; MMU PAGE 1 is stored in a page size of 4kB in a first mode that does not use padding] of the one or more storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2];
determine that a fragment of data [MMU PAGE 2 – 4, Fig 5A; Each MMU PAGE from 2 – 4 is a fragment] of the data segment [502; Fig 5] is less than the first page size [Figs 4 – 5A; Paragraphs 0035 – 0040; The first page size is 4kB and each fragment MMU PAGE2 - MMU PAGE 4 is less than 4kB];
store the fragment of data [MMU PAGE 2 – 4, Fig 5A] at the one or more storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2] using a second programming mode having a second page size [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES] that is less than the first page size [Figs 4 – 5A; Paragraphs 0035 – 0040; The page where MMU PAGE 2 – 3 is stored is smaller than where MMU PAGE 1 is stored] and
store remaining data [MMU PAGE 1, Fig 5A] of the data segment [502; Fig 5] at the one or more storage device using the first programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; The first programming mode and size is the uncompressed method using the max chunk size which is 4kB].
However, Kilari may not specifically disclose the limitation(s) of the first programming mode and the second programming mode correspond to different numbers of bits stored per memory cell of the one or more storage devices.
Kern discloses the first programming mode and the second programming mode correspond to different numbers of bits stored per memory cell of the one or more storage devices [Paragraphs 0017 – 0019, 0023, and 0054 – 0059; The memory switches programming modes where each mode corresponds to a different number of bits stored in a cell compared to another mode].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Kern in Kilari, because SLC and MLC modes of writing data each have their own advantages and disadvantages and allowing the memory to switch allows the system to take advantage of both modes as needed based on system parameters or user desire [0055 and 0057].
Regarding claim 5, Kilari teaches the second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES] is selected from a plurality of programming modes based on the second programming mode having a smallest page size that is greater than or equal to a size of the fragment of data [502, Figs 5A - 5B, Data programmed in the mode used in 502 selected such that the size of the page the data is stored in is of a smallest size that is greater than the compressed version of the data plus some padding or equal such that no padding is needed].
Claim 8 is a corresponding method of claim 1 and is rejected using the same prior art and similar reasoning. Kilari teaches the method [Fig 4].
Regarding claim 12, Kilari teaches the second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES] is selected from a plurality of programming modes based on the second programming mode having a smallest page size that is greater than or equal to a size of the fragment of data [502, Figs 5A - 5B, Data programmed in the mode used in 502 selected such that the size of the page the data is stored in is of a smallest size that is greater than the compressed version of the data plus some padding or equal such that no padding is needed].
Claim 15 is a corresponding medium of claim 1 and is rejected using the same prior art and similar reasoning. Kilari teaches the medium [Fig 4; A flowchart is a visual representation of the execution of instructions stored on a medium and executed by a processor].
Regarding claim 19, Kilari teaches the second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES] is selected from a plurality of programming modes based on the second programming mode having a smallest page size that is greater than or equal to a size of the fragment of data [502, Figs 5A - 5B, Data programmed in the mode used in 502 selected such that the size of the page the data is stored in is of a smallest size that is greater than the compressed version of the data plus some padding or equal such that no padding is needed].
Claim(s) 2 – 3, 6, 9 – 10, 13, and 16 - 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kilari et al. (Pub. No.: 2013/0326170) referred to a Kilari in view of Kern et a. (Pub. No.: US 2019/0057031) as applied to claims 1, 8, and 15 above, and further in view of Bernat et al. (Pat 10/545,687) referred to as Bernat.
With regard to claim 2, Kilari teaches the plurality of storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2] comprise a first storage device having a first erase block size [103, Fig 1B; 202, Fig 2; Flash memory is comprised of erase blocks of a certain size] and a second storage device [110, Fig 1B; 206, Fig 2].
However, Kilari in view of Kern may not specifically disclose the limitation of the second storage device having a second erase block size.
Bernat discloses the second storage device [152, Fig 2A] having a second erase block size [Column 14, Lines 50 – 67].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari in view of Kern, because it allows data to be rebuilt and allocated between different block sizes [Column 1, Lines 33 – 43] and using multiple flash instead of RAM allows the volatile data in RAM to be stored in non-volatile Flash.
With regard to claim 3, Kilari teaches the processing device [204, Fig 2] is further to:
form a subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed] to be stored at the one or more storage devices [103, Fig 1B; 202, Fig 2; The data is stored in flash], a fragment of data [MMU PAGE 2 – 4], and wherein the subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed] is to be stored at the one or more storage devices [103, Fig 1B; 202, Fig 2; The data is stored in flash] using the first programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; The first programming mode and size is the uncompressed method using the max chunk size which is 4kB].
However, Kilari in the view of Kern may not specifically disclose the limitation of a subsequent data segment comprises the fragment of data.
Bernat discloses a subsequent data segment comprises the fragment of data [Column 30, Lines 11 – 67; The duplication of data shows a fragment of data can be duplicated in another page of data].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari in view of Kern, because it provides a level of data protection by providing the system with duplicate copies of data in case one copy of data is lost the data can still be retrieved using the copy [Column 30, Lines 11 – 42].
With regard to claim 6, Kilari teaches the first programming [Figs 4 – 5A; Paragraphs 0035 – 0040; The first programming mode and size is the uncompressed method using the max chunk size which is 4kB] and second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES].
Kern discloses an SLC-mode storing a single bit in a memory cell and an MLC-mode storing more than one bit in a memory cell [Paragraph 0019].
However, Kilari in view of Kern may not specifically disclose the limitation of the first programming mode corresponds to a quad-level cell (QLC) mode and the second programming mode corresponds to a single-level cell (SLC) mode.
Bernat discloses a first programming mode corresponds to a quad-level cell (QLC) mode and a second programming mode corresponds to a single-level cell (SLC) mode [Figs 2A – 2G and 3B; Column 28, Lines 21 – 62; The first programming mode would correspond to a QLC mode when the memory is QLC and the second programming mode would correspond to SLC when the memory is SLC]
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari in view of Kern, because it allows the system to use different memory programming methods which each have their own advantages based on system needs and desires.
With regard to claim 9, Kilari teaches the plurality of storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2] comprise a first storage device having a first erase block size [103, Fig 1B; 202, Fig 2; Flash memory is comprised of erased blocks of a certain size] and a second storage device [110, Fig 1B; 206, Fig 2].
However, Kilari in view of Kern may not specifically disclose the limitation of the second storage device having a second erase block size.
Bernat discloses the second storage device [152, Fig 2A] having a second erase block size [Column 14, Lines 50 – 67].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari in view of Kern, because it allows data to be rebuilt and allocated between different block sizes [Column 1, Lines 33 – 43] and using multiple flash instead of RAM allows the volatile data in RAM to be stored in non-volatile Flash.
With regard to claim 10, Kilari teaches the processing device [204, Fig 2] is further to:
form a subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed] to be stored at the one or more storage devices [103, Fig 1B; 202, Fig 2; The data is stored in flash], a fragment of data [MMU PAGE 2 – 4], and wherein the subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed] is to be stored at the one or more storage devices [103, Fig 1B; 202, Fig 2; The data is stored in flash] using the first programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; The first programming mode and size is the uncompressed method using the max chunk size which is 4kB].
However, Kilari in the view of Kern may not specifically disclose the limitation of a subsequent data segment comprises the fragment of data.
Bernat discloses a subsequent data segment comprises the fragment of data [Column 30, Lines 11 – 67; The duplication of data shows a fragment of data can be duplicated in another page of data].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari in view of Kern, because it provides a level of data protection by providing the system with duplicate copies of data in case one copy of data is lost the data can still be retrieved using the copy [Column 30, Lines 11 – 42].
With regard to claim 13, Kilari teaches the first programming [Figs 4 – 5A; Paragraphs 0035 – 0040; The first programming mode and size is the uncompressed method using the max chunk size which is 4kB] and second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES].
Kern discloses an SLC-mode storing a single bit in a memory cell and an MLC-mode storing more than one bit in a memory cell [Paragraph 0019].
However, Kilari in view of Kern may not specifically disclose the limitation of the first programming mode corresponds to a quad-level cell (QLC) mode and the second programming mode corresponds to a single-level cell (SLC) mode.
Bernat discloses a first programming mode corresponds to a quad-level cell (QLC) mode and a second programming mode corresponds to a single-level cell (SLC) mode [Figs 2A – 2G and 3B; Column 28, Lines 21 – 62; The first programming mode would correspond to a QLC mode when the memory is QLC and the second programming mode would correspond to SLC when the memory is SLC]
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari in view of Kern, because it allows the system to use different memory programming methods which each have their own advantages based on system needs and desires.
With regard to claim 16, Kilari teaches the plurality of storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2] comprise a first storage device having a first erase block size [103, Fig 1B; 202, Fig 2; Flash memory is comprised of erase blocks of a certain size] and a second storage device [110, Fig 1B; 206, Fig 2].
However, Kilari in view of Kern may not specifically disclose the limitation of the second storage device having a second erase block size.
Bernat discloses the second storage device [152, Fig 2A] having a second erase block size [Column 14, Lines 50 – 67].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari in view of Kern, because it allows data to be rebuilt and allocated between different block sizes [Column 1, Lines 33 – 43] and using multiple flash instead of RAM allows the volatile data in RAM to be stored in non-volatile Flash.
With regard to claim 17, Kilari teaches the processing device [204, Fig 2] is further to:
form a subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed] to be stored at the one or more storage devices [103, Fig 1B; 202, Fig 2; The data is stored in flash], a fragment of data [MMU PAGE 2 – 4], and wherein the subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed] is to be stored at the one or more storage devices [103, Fig 1B; 202, Fig 2; The data is stored in flash] using the first programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; The first programming mode and size is the uncompressed method using the max chunk size which is 4kB].
However, Kilari in view of Kern may not specifically disclose the limitation of a subsequent data segment comprises the fragment of data.
Bernat discloses a subsequent data segment comprises the fragment of data [Column 30, Lines 11 – 67; The duplication of data shows a fragment of data can be duplicated in another page of data].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari in view of Kern, because it provides a level of data protection by providing the system with duplicate copies of data in case one copy of data is lost the data can still be retrieved using the copy [Column 30, Lines 11 – 42].
Claim(s) 4, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kilari et al. (Pub. No.: 2013/0326170) referred to a Kilari in view of Kern et a. (Pub. No.: US 2019/0057031) in view of Bernat et al. (Pat 10/545,687) referred to as Bernat as applied to claims 3, 10, 17 above, and further in view of Gorobets (Pub. No.: US 2008/0082596) referred to as Gorobets.
With regard to claim 4, Kilari teaches the processing device [204, Fig 2] is further configured to:
store the subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed], the fragment of data [MMU PAGE 2 – 4, Fig 5A] programmed using the second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES].
Bernat discloses a subsequent data segment comprises the fragment of data [Column 30, Lines 11 – 67; The duplication of data shows a fragment of data can be duplicated in another page of data].
However, Kilari in view of Kern in view of Bernat may not specifically disclose the limitation of data in the subsequent data segment is to be garbage collected upon storing the subsequent data segment.
Gorobets discloses data in the subsequent data segment is to be garbage collected upon storing the subsequent data segment [Figs 6 – 7 and 9A – 9B; Data is garbage collected after the data is stored].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gorobets in Kilari in view of Kern in view of Bernat, because it prevents the timeout errors when the amount of time to perform a garbage collection operation exceeds the fixed amount of time [Paragraphs 0003 – 0004].
With regard to claim 11, Kilari teaches the processing device [204, Fig 2] is further configured to:
store the subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed], the fragment of data [MMU PAGE 2 – 4, Fig 5A] programmed using the second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES].
Bernat discloses a subsequent data segment comprises the fragment of data [Column 30, Lines 11 – 67; The duplication of data shows a fragment of data can be duplicated in another page of data].
However, Kilari in view of Kern in view of Bernat may not specifically disclose the limitation of data in the subsequent data segment is to be garbage collected upon storing the subsequent data segment.
Gorobets discloses data in the subsequent data segment is to be garbage collected upon storing the subsequent data segment [Figs 6 – 7 and 9A – 9B; Data is garbage collected after the data is stored].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gorobets in Kilari in view of Kern in view of Bernat, because it prevents the timeout errors when the amount of time to perform a garbage collection operation exceeds the fixed amount of time [Paragraphs 0003 – 0004].
With regard to claim 18, Kilari teaches the processing device [204, Fig 2] is further configured to:
store the subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed], the fragment of data [MMU PAGE 2 – 4, Fig 5A] programmed using the second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES].
Bernat discloses a subsequent data segment comprises the fragment of data [Column 30, Lines 11 – 67; The duplication of data shows a fragment of data can be duplicated in another page of data].
However, Kilari in view of Kern in view of Bernat may not specifically disclose the limitation of data in the subsequent data segment is to be garbage collected upon storing the subsequent data segment.
Gorobets discloses data in the subsequent data segment is to be garbage collected upon storing the subsequent data segment [Figs 6 – 7 and 9A – 9B; Data is garbage collected after the data is stored].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gorobets in Kilari in view of Kern in view of Bernat, because it prevents the timeout errors when the amount of time to perform a garbage collection operation exceeds the fixed amount of time [Paragraphs 0003 – 0004].
Claim(s) 7, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kilari et al. (Pub. No.: 2013/0326170) referred to a Kilari in view of Kern et a. (Pub. No.: US 2019/0057031) as applied to claims 1, 8, and 15 above, and further in view of Villa (Pub. No.: US 2018/0033467) referred to as Villa.
Regarding claim 7, Kilari teaches the processing device [204, Fig 2] is further to:
store the fragment of data [MMU PAGE 2 – 3] with padding data to fill a page size [404, Fig 4; Fig 5A; Paragraphs 0035 – 0040; Data is padded to a size that corresponds to a predetermined compressed size used in the second programming mode].
However, Kilari in view of Kern may not specifically disclose the limitation(s) of storing the fragment of data using the second programming mode requires less padding than storing the fragment of data using the first programming mode.
Villa discloses the fragment of data using the second programming mode requires less padding than storing the fragment of data using the first programming mode [Fig 7; Paragraphs 0016, 0024, 0027, 0117; When the page size is smaller in the second programming mode less padding data would be required to fill the page then in a first programming mode where the page size is larger].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing data of the claimed invention to incorporate Villa in Kilari in view of Kern, because it the dynamic sizing of page size allows for reduced power consumption when smaller page sizes are used while also allowing the system to increase page size as needed to increase performance [Paragraph 0015].
Regarding claim 14, Kilari teaches storing the fragment of data [MMU PAGE 2 – 3] with padding data to fill a page size [404, Fig 4; Fig 5A; Paragraphs 0035 – 0040; Data is padded to a size that corresponds to a predetermined compressed size used in the second programming mode].
However, Kilari in view of Kern may not specifically disclose the limitation(s) of storing the fragment of data using the second programming mode requires less padding than storing the fragment of data using the first programming mode.
Villa discloses the fragment of data using the second programming mode requires less padding than storing the fragment of data using the first programming mode [Fig 7; Paragraphs 0016, 0024, 0027, 0117; When the page size is smaller in the second programming mode less padding data would be required to fill the page then in a first programming mode where the page size is larger].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing data of the claimed invention to incorporate Villa in Kilari in view of Kern, because it the dynamic sizing of page size allows for reduced power consumption when smaller page sizes are used while also allowing the system to increase page size as needed to increase performance [Paragraph 0015].
Regarding claim 20, Kilari teaches the processing device [204, Fig 2] is further to:
store the fragment of data [MMU PAGE 2 – 3] with padding data to fill a page size [404, Fig 4; Fig 5A; Paragraphs 0035 – 0040; Data is padded to a size that corresponds to a predetermined compressed size used in the second programming mode].
However, Kilari in view of Kern may not specifically disclose the limitation(s) of storing the fragment of data using the second programming mode requires less padding than storing the fragment of data using the first programming mode.
Villa discloses the fragment of data using the second programming mode requires less padding than storing the fragment of data using the first programming mode [Fig 7; Paragraphs 0016, 0024, 0027, 0117; When the page size is smaller in the second programming mode less padding data would be required to fill the page then in a first programming mode where the page size is larger].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing data of the claimed invention to incorporate Villa in Kilari in view of Kern, because it the dynamic sizing of page size allows for reduced power consumption when smaller page sizes are used while also allowing the system to increase page size as needed to increase performance [Paragraph 0015].
Response to Arguments
Applicant's arguments filed 09/02/2026 have been fully considered but they are not persuasive.
The applicant argues on page 8 that Kilari fails to teach changing the number of bits stored per memory cell or otherwise disclose first and second programming modes. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
Kilari is not used to teach changing the number of bits stored per memory cell. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The arguments regarding Kilari not teaching first and second programming modes fail to properly explain how the claim limitations are not taught by the prior art other than saying they do not. There are no specific examples or explanation detailing how the prior art is different from the current claim limitations. Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. The rejections contain citations and explanations detailing how the prior art teaches the current claim limitations.
The applicant argues on pages 8 – 9 that Kern fails to remedy the argued deficiencies of Kilari since Kern does not teach selecting a programming mode based on determining that a fragment of a data segment is smaller than a page associated with an initially allocation programming mode. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., selecting a programming mode based on determining that a fragment of a data segment is smaller than a page associated with an initially allocation programming mode) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). There is no specific limitation that directly dependent on the determination step. The two storing steps are listed after the determining step but they are not directly dependent on the determination.
The applicant argues on page 9 that there is no teaching or reason to reconstruct the reference into the particular storage arrangement recited in claims 1, 8, and 15. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Kilari teaches using different programming methods to store data such as compressed and uncompressed. Kern further teaches the different programming methods can include how many bits are stored in a memory cell. The combination shows using different methods to store data that takes the advantage of compression of data and the different advantages of using different number of bits per memory cell such as SLC and MLC when storing data.
The applicant argues on pages 9 – 10 the prior art fails to teach the limitations of claims 3, 10, and 17 since Kilari fails to teach storing using a second bits-per-cell programming mode and subsequently incorporating that fragments into another data segment and that Kern fails to disclose the fragment lifecycle. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., storing using a second bits-per-cell programming mode) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Kilari and Kern are not used to teach subsequently incorporating that fragments into another data segment. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The applicant argues on pages 10 that claims 4, 11, and 18 are not taught by the prior art since Gorobets fails to teach all the limitations of the argued claims. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
Gorobets is not used to teach all the limitations of the claims. The claims are rejected by the combination of Kilari, Kern, and Gorobets are indicated in the rejections above. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The applicant argues on pages 10 – 11 that the prior art fails to teach the newly amended limitations of claims 5, 12, and 19. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The applicant’s arguments are moot in view of the new grounds of rejection. The amendments have changed the scope of the claims requiring further search and consideration of the prior art. The new grounds of rejection are a result of the further search and consideration of the prior art. The examiner suggests amending the claims to include further details defining the inventive concept from the specification to overcome the cited prior art and further advance prosecution.
The applicant argues on page 11 that the prior art fails to teach the newly amended limitations of claims 7, 14, and 20. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
The applicant’s arguments are moot in view of the new grounds of rejection. The amendments have changed the scope of the claims requiring further search and consideration of the prior art. The new grounds of rejection are a result of the further search and consideration of the prior art. The examiner suggests amending the claims to include further details defining the inventive concept from the specification to overcome the cited prior art and further advance prosecution.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached at 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
Prosecution Insights