DETAILED ACTION
The current Office Action is in response to the papers submitted 12/22/2025. Claims 1 – 20.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 2, 5 – 9, 12 – 16, and 19 - 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 - 14 of U.S. Patent No. 12,099,742. Although the claims at issue are not identical, they are not patentably distinct from each other for the reasons listed below.
Instant Application
Pat 12,099,742
Reasoning
1. A system comprising: a plurality of storage devices; and a storage controller operatively coupled to the plurality of storage devices, the storage controller comprising a processing device configured to: form a data segment to be stored at one or more storage devices of the plurality of storage devices, allocate data of the data segment to pages of the one or more storage devices based on a first page size associated with a first programming mode of the one or more storage devices; determine that a fragment of data of the data segment is less than the first page size; and store the fragment of data at the one or more storage devices using a second programming mode having a second page size that is less than the first page size and remaining data of the data segment at the one or more storage device using the first programming mode.
1. A system comprising: a plurality of storage devices; and a storage controller operatively coupled to the plurality of storage devices, the storage controller comprising a processing device, the processing device to: form a data segment to be stored at one or more storage devices of the plurality of storage devices, wherein the data segment is to be stored at the one or more storage devices using a first programming mode having a first page size; determine that a fragment of data of the data segment is less than the first page size; store a first copy of the fragment of data at the one or more storage devices using a second programming mode having a second page size that is less than the first page size and the remaining data of the data segment at the one or more storage device using the first programming mode; store a second copy of the fragment of data as part of a subsequent data segment using the first programming mode; and perform garbage collection on the first copy of the fragment of data after storing the second copy of the fragment using the first programming mode.
Both sets of claims use the same structure to form a data segment to be stored in storage, the segment is stored/allocated in memory using a first programming mode with a first page size, determine a fragment of a segment is smaller than a page size, and store the fragment using a second programming mode having a page size different from the first programming mode, and storing the rest of the segment using the first programming mode.
2
2
The same limitations are disclosed in both claims
5
3
The same limitations are disclosed in both claims
6
4
The same limitations are disclosed in both claims
7
5
The same limitations are disclosed in both claims
8 – 9, 12 – 16, and 19 - 20
6 – 14
Both sets of claims disclose similar limitations as indicated in the previous pairings above
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7 – 8, 14 – 15, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kilari et al. (Pub. No.: 2013/0326170) referred to a Kilari.
Regarding claim 1, Kilari teaches a plurality of storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2; The Flash and RAM are both storage devices]; and
a storage controller [204, Fig 2; Paragraph 0032; The processor is a controller that controls the memory using the MMU] operatively coupled to the plurality of storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2], the storage controller [204, Fig 2] comprising a processing device [204 or 214, Fig 2; Item 204 is a processor and the MMU is a device/module that coordinates accesses to the memory running on the processor. Either can be considered a processing device] configured to:
form a data segment [502; Fig 5; The compressed MMU pages 1 – 4 together is a data segment] to be stored at one or more storage devices [103, Fig 1B; 202, Fig 2; The data is stored in flash] of the plurality of storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2];
allocate data [MMU PAGE 1, Fig 5A] of the data segment [502; Fig 5] to pages [508, Fig 5A] of the one or more storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2] based on a first page size associate with a first programming mode [Paragraphs 0035 – 0044; Figs 4 – 5A; MMU PAGE 1 is stored in a page size of 4kB in a first mode that does not use padding] of the one or more storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2];
determine that a fragment of data [MMU PAGE 2 – 4, Fig 5A; Each MMU PAGE from 2 – 4 is a fragment] of the data segment [502; Fig 5] is less than the first page size [Figs 4 – 5A; Paragraphs 0035 – 0040; The first page size is 4kB and each fragment MMU PAGE2 - MMU PAGE 4 is less than 4kB];
store the fragment of data [MMU PAGE 2 – 4, Fig 5A] at the one or more storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2] using a second programming mode having a second page size [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES] that is less than the first page size [Figs 4 – 5A; Paragraphs 0035 – 0040; The page where MMU PAGE 2 – 3 is stored is smaller than where MMU PAGE 1 is stored] and
store remaining data [MMU PAGE 1, Fig 5A] of the data segment [502; Fig 5] at the one or more storage device using the first programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; The first programming mode and size is the uncompressed method using the max chunk size which is 4kB].
Regarding claim 7, Kilari teaches the processing device [204, Fig 2] is further to:
store the fragment of data [MMU PAGE 2 – 3] with padding data [404, Fig 4], wherein an amount of data of the fragment of data and the padding data corresponds to the second page size of the second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Data is padded to a size that corresponds to a predetermined compressed size used in the second programming mode].
Claims 8, 14 – 15, and 20 are corresponding method and medium claims of system claims 1 and 7 and are thus rejected using the same prior art and same reasoning.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 – 3, 5 – 6, 9 – 10, 12 – 13, 16 – 17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kilari et al. (Pub. No.: 2013/0326170) referred to a Kilari as applied to claims 1, 8, and 15 above, and further in view of Bernat et al. (Pat 10/545,687) referred to as Bernat.
With regard to claim 2, Kilari teaches the plurality of storage devices [103 and 110, Fig 1B; 202 and 206, Fig 2] comprise a first storage device having a first erase block size [103, Fig 1B; 202, Fig 2; Flash memory is comprised of erase blocks of a certain size] and a second storage device [110, Fig 1B; 206, Fig 2].
However, Kilari may not specifically disclose the limitation of the second storage device having a second erase block size.
Bernat discloses the second storage device [152, Fig 2A] having a second erase block size [Column 14, Lines 50 – 67].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari, because it allows data to be rebuilt and allocated between different block sizes [Column 1, Lines 33 – 43] and using multiple flash instead of RAM allows the volatile data in RAM to be stored in non-volatile Flash.
With regard to claim 3, Kilari teaches the processing device [204, Fig 2] is further to:
form a subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed] to be stored at the one or more storage devices [103, Fig 1B; 202, Fig 2; The data is stored in flash], a fragment of data [MMU PAGE 2 – 4], and wherein the subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed] is to be stored at the one or more storage devices [103, Fig 1B; 202, Fig 2; The data is stored in flash] using the first programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; The first programming mode and size is the uncompressed method using the max chunk size which is 4kB].
However, Kilari may not specifically disclose the limitation of a subsequent data segment comprises the fragment of data.
Bernat discloses a subsequent data segment comprises the fragment of data [Column 30, Lines 11 – 67; The duplication of data shows a fragment of data can be duplicated in another page of data].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari, because it provides a level of data protection by providing the system with duplicate copies of data in case one copy of data is lost the data can still be retrieved using the copy [Column 30, Lines 11 – 42].
With regard to claim 5, Kilari teaches the first programming [Figs 4 – 5A; Paragraphs 0035 – 0040; The first programming mode and size is the uncompressed method using the max chunk size which is 4kB] and second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES].
However, Kilari may not specifically disclose the limitation of the first programming mode corresponds to a triple-level cell (TLC) mode and the second programming mode corresponds to a single-level cell (SLC) mode.
Bernat discloses a first programming mode corresponds to a triple-level cell (TLC) mode and a second programming mode corresponds to a single-level cell (SLC) mode [Figs 2A – 2G and 3B; Column 28, Lines 21 – 62; The first programming mode would correspond to a TLC mode when the memory is TLC and the second programming mode would correspond to SLC when the memory is SLC]
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari, because it allows the system to use different memory programming methods which each have their own advantages based on system needs and desires.
With regard to claim 6, Kilari teaches the first programming [Figs 4 – 5A; Paragraphs 0035 – 0040; The first programming mode and size is the uncompressed method using the max chunk size which is 4kB] and second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES].
However, Kilari may not specifically disclose the limitation of the first programming mode corresponds to a quad-level cell (QLC) mode and the second programming mode corresponds to a single-level cell (SLC) mode.
Bernat discloses a first programming mode corresponds to a quad-level cell (QLC) mode and a second programming mode corresponds to a single-level cell (SLC) mode [Figs 2A – 2G and 3B; Column 28, Lines 21 – 62; The first programming mode would correspond to a QLC mode when the memory is QLC and the second programming mode would correspond to SLC when the memory is SLC]
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Bernat in Kilari, because it allows the system to use different memory programming methods which each have their own advantages based on system needs and desires.
Claims 9 – 10, 12 – 13, 16 – 17, and 19 are corresponding method and medium claims of system claims 2 – 3 and 5 - 6 and are thus rejected using the same prior art and same reasoning.
Claim(s) 4, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kilari et al. (Pub. No.: 2013/0326170) referred to a Kilari in view of Bernat et al. (Pat 10/545,687) referred to as Bernat as applied to claims 3, 10, 17 above, and further in view of Gorobets (Pub. No.: US 2008/0082596) referred to as Gorobets.
With regard to claim 4, Kilari teaches the processing device [204, Fig 2] is further configured to:
store the subsequent data segment [420, 410, and 400, Fig 4; 502, Fig 5; The system creates multiple subsequent data segments until all the MMU pages have been processed], the fragment of data [MMU PAGE 2 – 4, Fig 5A] programmed using the second programming mode [Figs 4 – 5A; Paragraphs 0035 – 0040; Each fragment is stored using in a compressed format and with padding if needed which is different from how MMU PAGE 1 is stored since the data is not compressed or padded when the outcome of step 402 is YES].
Bernat discloses a subsequent data segment comprises the fragment of data [Column 30, Lines 11 – 67; The duplication of data shows a fragment of data can be duplicated in another page of data].
However, Kilari in view of Bernat may not specifically disclose the limitation of data in the subsequent data segment is to be garbage collected upon storing the subsequent data segment.
Gorobets discloses data in the subsequent data segment is to be garbage collected upon storing the subsequent data segment [Figs 6 – 7 and 9A – 9B; Data is garbage collected after the data is stored].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gorobets in Kilari in view of Bernat, because it prevents the timeout errors when the amount of time to perform a garbage collection operation exceeds the fixed amount of time [Paragraphs 0003 – 0004].
Claims 11 and 18 are corresponding method and medium claims of system claim 4 and are thus rejected using the same prior art and same reasoning.
Response to Arguments
Applicant's arguments filed 12/22/2025 have been fully considered but they are not persuasive.
The applicant argues on page 7 that double patenting rejection should be withdrawn in view of the terminal disclaimer over US Pat. 12,099,742 being filed with the amendments. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
There does not appear to be a terminal disclaimer filed as the applicant argues. The double patenting rejection has been updated in view of the amendments and is still maintained.
The applicant argues on pages 9 – 10 regarding claims 1, 7 - 8,14 - 15, and 20 that Kilari fails to teach the programming mode used to store data since Kilari is argued as using the same programming mode since the pages are the same size. Kilari is also argued to not teach the claim limitations since Kilari does not describe the data is stored in different physical page size of different programming modes based on a comparison. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
Figure 5A of Kilari teaches the MMU Page in 504 is different sizes. MMU PAGE 1 is considered a page of data that is 4kB in size. MMU PAGE 3 is considered a page of data that is 2kB in size. There is no indication in the argued claims as to the page being a physical, logical, or other type of page. MMU PAGE 1 is considered a 4kB page comprised of 2 smaller 2kB pages. MMU PAGE1 may be considered a metapage but is still a page.
There is no mention in the argued claims what the programming mode is with respect to specifically or how the modes are different from each other. Figure 4 shows multiple programming modes. Decision blocks 402, 406, and 412 all result in a different programming mode of storing data. Each step 404, 408, 414, 416, and 418 result in data being programmed into memory using a different method based on the decision outcomes in steps 402, 406, and 412.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., data is stored in different physical page size of different programming modes based on a comparison) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). There is no mention of a physical page size being used in a comparison in the argued claims.
The applicant argues on pages 10 – 11 that the remaining dependent claims are allowable since the additional prior art fails to remedy the argued deficiencies of Kilari above. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments above detailing how Kilari teaches the amended limitations and updated the rejections above to show how Kilari teaches the amended limitations. The dependent claims rejections are maintained based in part on the rejections of the respective base claim rejections in view of Kilari.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2136