DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
This Office Action is sent in response to Applicant’s Communication received 9/19/2024 for application number 18/890,669. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and claims.
Claims 1 is presented for examination.
Drawings
Examiner contends that the drawings filed 9/19/2024 are acceptable for examination proceedings.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,111,711 in view of Yu et al. (hereinafter as Yu) PGPUB 2012/0011377. Although the claims at issue are not identical, they are not patentably distinct from each other because they are simple changes of a statutory category. A person of ordinary skill in the art would conclude that the invention defined in the claims at issue would have been an obvious variation of the invention defined in the claims of the patent.
USPAT 12,111,711 teaches an integrated circuit package comprising:
a core unit having a first core including a first cache memory, a second core including a second cache memory, and a shared cache memory to be shared by at least the first core and the second core, the first and second cores each having two architecture state registers [claim 1];
a graphics processing unit (GPU) to execute a graphics workload [claim 1];
a memory controller [claim 1];
a cache coherent interconnect coupling the core unit and the GPU [claim 1];
a static random access memory [claim 1];
an interface to couple the integrated circuit package with another device via a Peripheral Component Interconnect Express (PCIe) protocol [claim 1];
a first workload monitor to determine a core workload of the core unit [claim 1];
a second workload monitor to determine the graphics workload of the GPU [claim 1];
a third workload monitor to determine a bus workload for the cache coherent interconnect [claim 1]; and
a power controller coupled to the first, second, and third workload monitors to receive inputs therefrom and configured to balance performance of the core unit and the GPU according to actual monitored workloads of the core unit, the GPU and the cache coherent interconnect within a thermal design power (TDP) limit for the integrated circuit package to achieve maximum performance for the integrated circuit package by [claim 1]: and (ii) increasing a frequency for the core unit and the cache coherent interconnect [claim 1].
Yu teaches at a first time when the GPU is fully occupied, (i) increasing a frequency for the GPU, and either (ii) increasing a frequency for the core unit if the TDP power limit for the integrated circuit package has not been reached [0022], or (iii) capping or decreasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has been reached. Yu monitors the GPU and the CPU and may increase the frequency of them together when under the temperature limit and over-frequency is permitted to improve performance.
The combination of USPAT 12,111,711 with Yu leads to increasing the GPU frequency along with the CPU and interconnect bus frequency together when the temperature limits have not been reached and over-frequency is permitted.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to use Yu’s teachings of increasing frequency for both CPU and GPU when under the TDP limit in USPAT 12,111,711. One of ordinary skill in the art would have been motivated to increase frequency for both the CPU and GPU if there is available TDP or thermal limit because it will increase the performance of the computing device.
Similarly, claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 6 of U.S. Patent No. 11,106,262 in view of Yu.
Similarly, claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 6 of U.S. Patent No. 9,703,352 in view of Yu.
Similarly, claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 10,317,976 in view of Yu.
Comparisons of claims are shown in the following tables.
Instant Application (18/890,669)
U.S. Patent 12,111,711
U.S. Patent 11,106,262
1. An integrated circuit package comprising:
a core unit having a first core including a first cache memory, a second core including a second cache memory, and a shared cache memory to be shared by at least the first core and the second core, the first and second cores each having two architecture state registers; a graphics processing unit (GPU) to execute a graphics workload; a memory controller; a cache coherent interconnect coupling the core unit and the GPU; a static random access memory; an interface to couple the integrated circuit package with another device via a Peripheral Component Interconnect Express (PCIe) protocol; a first workload monitor to determine a core workload of the core unit;
a second workload monitor to determine the graphics workload of the GPU; a third workload monitor to determine a bus workload for the cache coherent interconnect; and a power controller coupled to the first, second, and third workload monitors to receive inputs therefrom and configured to balance performance of the core unit and the GPU according to actual monitored workloads of the core unit, the GPU and the cache coherent interconnect within a thermal design power (TDP) limit for the integrated circuit package to achieve maximum performance for the integrated circuit package by: at a first time when the GPU is fully occupied, (i) increasing a frequency for the GPU, and either (ii) increasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has not been reached, or (iii) capping or decreasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has been reached.
1. A system on chip (SoC) comprising: an integrated circuit package comprising: a core unit having a first core to support out-of-order execution of instructions including a first cache memory, a second core to support in-order execution of instructions including a second cache memory, and a shared cache memory to be shared by at least the first core and the second core; a graphics processing unit (GPU) to execute a graphics workload; a memory controller; a communication bus coupled to the core unit, the communication bus to couple the core unit and the GPU, the communication bus comprising a cache coherent interconnect; a static random access memory; an interface to interface the SoC with another device via a Peripheral Component Interconnect Express (PCle) protocol; a first workload monitor to determine a core workload of the core unit; a second workload monitor to determine the graphics workload of the GPU; a third workload monitor to determine a bus workload for the communication bus; and a power controller to reduce a power consumption of at least the core unit if a thermal value of the SoC exceeds a thermal design power (TDP) limit for the SoC, wherein in a first scenario the power controller is to increase a frequency for the GPU when the graphics workload is greater than a graphics threshold and reduce the frequency of the core unit, and in a second scenario to increase a frequency for the core unit and the communication bus and reduce the frequency of the GPU, wherein the power controller is to receive the bus workload and to dynamically balance power between the core unit and the communication bus based on the TDP limit and a comparison between the bus workload and a bus threshold, and wherein the power controller, in response to operation of the SoC at the TDP limit, is to increase frequency for the communication bus and cap the frequency for the core unit if the bus workload is greater than the bus threshold, and decrease the frequency for the communication bus and increase the frequency for the core unit if the bus workload is less than the bus threshold.
1. A system on chip (SoC) comprising: an integrated circuit package comprising: a central processing unit (CPU) having a first plurality of cores including a first core to support out-of-order execution of instructions, the first core having a first cache memory, and a second core, the second core asymmetric from the first core, and a shared cache memory to be shared by at least some of the first plurality of cores; a graphics processing unit (GPU) having a second plurality of cores; a memory controller; a communication bus coupled to the CPU, the communication bus to couple the CPU and the GPU; a first workload monitor to determine a core workload of the CPU; a second workload monitor to determine a graphics workload of the GPU; a third workload monitor to determine a bus workload for the communication bus; and a power controller to receive the graphics workload and to dynamically balance power between the CPU and the GPU based at least in part on a thermal design power (TDP) limit for the SoC and a comparison between the graphics workload and a graphics threshold, wherein a power consumption of at least the CPU is to be reduced if a thermal value of the SoC exceeds the TDP limit, wherein in a first scenario the power controller is to increase a frequency for the GPU and cap a frequency for the CPU if the graphics workload is greater than the graphics threshold, and in a second scenario to reduce the frequency for the GPU and increase the frequency for the CPU and the communication bus.
6. The SoC of claim 1, wherein the communication bus comprises a cache coherent interconnect.
Instant Application (18/890,669)
U.S. Patent 9,703,352
U.S. Patent 10,317,976
1. An integrated circuit package comprising:
a core unit having a first core including a first cache memory, a second core including a second cache memory, and a shared cache memory to be shared by at least the first core and the second core, the first and second cores each having two architecture state registers; a graphics processing unit (GPU) to execute a graphics workload; a memory controller; a cache coherent interconnect coupling the core unit and the GPU; a static random access memory; an interface to couple the integrated circuit package with another device via a Peripheral Component Interconnect Express (PCIe) protocol; a first workload monitor to determine a core workload of the core unit;
a second workload monitor to determine the graphics workload of the GPU; a third workload monitor to determine a bus workload for the cache coherent interconnect; and a power controller coupled to the first, second, and third workload monitors to receive inputs therefrom and configured to balance performance of the core unit and the GPU according to actual monitored workloads of the core unit, the GPU and the cache coherent interconnect within a thermal design power (TDP) limit for the integrated circuit package to achieve maximum performance for the integrated circuit package by: at a first time when the GPU is fully occupied, (i) increasing a frequency for the GPU, and either (ii) increasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has not been reached, or (iii) capping or decreasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has been reached.
1. A processor comprising: a first semiconductor die including: a first core; a cache memory; a communication bus coupled to the first core, the communication bus to couple the first core and the cache memory; a graphics processor; a core workload monitor to determine a core workload for the first core; a bus workload monitor to determine a bus workload for the communication bus; and a power control unit including logic to receive the bus workload and to dynamically balance power between the first core and the communication bus based on a power limit for the processor and a comparison between the bus workload and a bus workload threshold, the power limit corresponding to a maximum thermal dissipation capacity for the processor, wherein a power consumption of one of the first core and the communication bus is to be reduced if a thermal value of the processor exceeds the power limit, wherein the logic, in response to operation of the processor at the power limit, is to increase frequency for the communication bus and cap frequency for the first core if the bus workload is greater than the bus workload threshold, and decrease frequency for the communication bus and increase the frequency for the first core if the bus workload is less than the bus workload threshold.
6. The processor of claim 5, wherein the logic is to reduce a frequency of the graphics processor and to increase a frequency of the first core and the communication bus.
14. A system comprising: a system on chip (SoC) comprising: a plurality of cores including a first core to support out-of-order execution of instructions, the first core having a first cache memory; a cache memory separate from the plurality of cores, the cache memory to be shared by at least some of the plurality of cores; a graphics processor; a memory controller; a communication bus coupled to the first core, the communication bus to couple the first core and the cache memory; a core workload monitor to determine a core workload of the first core; a graphics workload monitor to determine a graphics workload of the graphics processor, a bus workload monitor to determine a bus workload for the communication bus; and a power controller to receive the graphics workload and to dynamically balance power between the first core and the graphics processor based at least in part on a power limit for the SoC and a comparison between the graphics workload and a graphics threshold, the power limit corresponding to a maximum thermal dissipation capacity for the SoC, wherein a power consumption of at least the first core is to be reduced if a thermal value of the SoC exceeds the power limit, wherein the power controller is to increase frequency for the graphics processor and cap frequency for the first core if the graphics workload is greater than the graphics threshold, and to reduce the frequency for the graphics processor and increase the frequency for the first core and the communication bus; and a dynamic random access memory (DRAM) coupled to the SoC.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Branover et al. (hereinafter as Branover)1 PGPUB 2012/0110352, and further in view of Yu et al. (hereinafter as Yu) PGPUB 2012/0011377 and Park et al. (hereinafter as Park)1 PGPUB 20120102345.
As per claim 1, Branover teaches an integrated circuit package [0010: system on a chip (SoC) and FIG. 1 integrated circuit 2] comprising:
a core unit having a first core [FIG. 1-2 and 0030: (multicore processor have multiple processing nodes/cores, such as core 11-1 (first core); grouping of cores is a core unit)] including a first cache memory [0031: (processing nodes each have cache memories)], a second core including a second cache memory [FIG. 1-2 and 0031: (core 11-2 (second core) has its own cache memory)], and a shared cache memory to be shared by at least the first core and the second core FIG. 1 main memory 6], the first and second cores each having two architecture state registers [0024, and 0036-0037: (local TDP limits may be set per core), 0049: (each core may be set to a P-state); setting local TDP limits requires storage of such setting, and such storage unit is a register; similarly, setting P-state for a core requires storage of such setting, and such storage unit is also a register; thus each core has two state registers)];
a graphics processing unit (GPU) to execute a graphics workload [0032 and FIG. 1: (GPU processing unit; GPU inherently executes graphics workload)];
a memory controller [FIG. 1 memory controller 18];
a cache coherent interconnect [0032 and FIG. 1 north bridge 12] coupling the core unit and the GPU [FIG. 1: north bridge 12 couples the core unit to the GPU)];
a static random access memory [0085: static RAM];
an interface to couple the integrated circuit package with another device via a Peripheral Component Interconnect Express (PCIe) protocol [FIG. 1 and 0033: (PCI express bus)];
a first workload monitor to determine a core workload of the core unit [0036 and 0044: (power management unit (PMU) 20 manages power consumption based on respective activity levels of workload; PMU 20 monitors the workloads of processing nodes)];
a power controller [0037: (thermal control unit 21 within PMU 20)] to balance performance within a thermal design power (TDP) limit for the integrated circuit package to achieve maximum performance for the integrated circuit package [0027-0028: (when TDP limit is reached, cores are throttled)]
Branover does not teach a second workload monitor to determine the graphics workload of the GPU; a third workload monitor to determine a bus workload for the cache coherent interconnect; and the power controller coupled to the first, second, and third workload monitors to receive inputs therefrom and configured to balance performance of the core unit and the GPU according to actual monitored workloads of the core unit, the GPU and the cache coherent interconnect within a thermal design power (TDP) limit for the integrated circuit package to achieve maximum performance for the integrated circuit package by: at a first time when the GPU is fully occupied, (i) increasing a frequency for the GPU, and either (ii) increasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has not been reached, or (iii) capping or decreasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has been reached.
Yu teaches dynamically adjusting operating frequency in a computing circuit based on detected load. Yu is thus similar to Branover. Yu further teaches a second workload monitor to determine the graphics workload of the GPU [FIG. 1 second load-detecting unit 16 connected to GPU]; the power controller coupled to the first, second, workload monitors to receive inputs therefrom [FIG. 1: (control unit receives information from first load detecting unit 15 of CPU and second load detecting unit 16 of GPU)] and configured to balance performance according to actual monitored workloads of the core unit, the GPU by: at a first time when the GPU is fully occupied [0022: (load equal to load threshold value)], (i) increasing a frequency for the GPU, and either (ii) increasing a frequency for the core unit if the TDP power limit for the integrated circuit package has not been reached [0022: (raise the frequency of the clock signal of the CPU and the GPU when over-frequency is needed and permitted (which means TDP is not reached))] or (iii) capping or decreasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has been reached. In summary, Yu monitors the workload of the GPU and the CPU and may increase the frequency of them together to improve performance.
The combination of Branover with Yu leads to Branover also monitoring the workload of the GPU, and increasing the frequency of the CPU and the GPU when overclocking is permitted and TDP has not been reached.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to use Yu’s teachings of monitoring the GPU workload and increasing frequency for both CPU and GPU in Branover. One of ordinary skill in the art would have been motivated to monitor GPU workload and adjust GPU frequency in Branover because it allows for better optimization of processing components in both GPU and CPU. One of ordinary skill in the art would have been motivated to increase frequency for both the CPU and GPU if there is available TDP or thermal limit because it will increase the performance of the computing device.
Branover and Yu do not explicitly teach a third workload monitor to determine a bus workload for the cache coherent interconnect; the power controller coupled to the third workload monitor to receive inputs therefrom and configured to balance performance according to actual monitored workloads of the cache coherent interconnect by: either (ii) increasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has not been reached, or (iii) capping or decreasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has been reached. Branover and Yu do not appear to monitor the workload of a bus or describe increasing a frequency to both the core and the bus, or decreasing a frequency of both the core and bus.
Park teaches a System on a Chip and changing voltage and clock frequency of a processor. Park is thus similar to Branover and Yu. Park further teaches the first and second cores each having two architecture state registers [0074 and 0078]; a third workload monitor to determine a bus workload for the cache coherent interconnect [0052: (2nd slave controller 214 monitors the operation of the bus and selects a bus frequency depending on activity of the bus)]; and the power controller coupled to the third workload monitor [FIG. 2: (master controller coupled to 2nd salve controller)] to receive inputs therefrom and configured to balance performance according to actual monitored workloads of the cache coherent interconnect by: either (ii) increasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has not been reached [0065, 0070: (increase both the bus frequency and current CPU frequency)], or (iii) capping or decreasing a frequency for the core unit and the cache coherent interconnect if the TDP power limit for the integrated circuit package has been reached.
The combination of Branover and Yu with Park leads to monitoring of workload on the north bridge bus and increasing frequency for the bus and processor in Branover and Yu when the device is under the TDP operating point and there is available power.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to use Park’s teachings of a bus monitor and increasing both CPU and bus frequency in Branover and Yu. One of ordinary skill in the art would have been motivated to monitor the bus activity in Branover and Yu because it detects if the bus is operating correctly during a predefined reference time [Park 0062]. One of ordinary skill in the art would have been motivate to increase the frequency of both the bus and the CPU in Branover and Yu because it improves performance while operating within TDP and prevents the bus or CPU from becoming a bottleneck that would slow down the computing system.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Song et al. (PGPUB 2011/0161627) teaches each core having a plurality of architecture state registers [FIG. 1].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY CHAN whose telephone number is (571)270-5134. The examiner can normally be reached Monday - Friday 10-7 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 5712703779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY CHAN/Primary Examiner, Art Unit 2175
1 Cited in IDS submitted on 10/17/2024.