DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 11/25/2025 complies with the provisions of 37 CFR 1.98 with a size fee assertion. The information referred to therein has been considered as to the merits.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Mai et al. (US 11,581,875 B1) in view of Perraud (US 5,838,149 A).
Consider claim 1:
Mai discloses a transmitter (see Fig. 1 and col. 2, lines 5-10, where Mai describes a LVDS transmitter 102), comprising:
an output comprising a first terminal and a second terminal (see Fig. 1 and col. 2, lines 15-20, where Mai describes that the transmitter circuit 102 outputs differential signals at first node padn and second node padp);
a driver having first transistor switches coupled to first current sources (see col. 1, lines 45-50, where Mai describes that the LVDS transmitter 102 is a driver; see Fig. 1 and col. 3, lines 5-15, where Mai describes that the LVDS transmitter 102 includes transistors 106 and 108 which are coupled to a current source 172);
a first circuit having a first transistor coupled between the first transistor switches and the first terminal (see Fig. 1 and col. 3, lines 5-34, where Mai describes a first transistor 107 which in coupled between the transistor 106 and the first node padn), and
a second transistor coupled between the first transistor switches and the second terminal (see Fig. 1 and col. 3, lines 5-34, where Mai describes a second transistor 109 which in coupled between the transistor 108 and the second node padp); and
a second circuit, coupled between the output and gates of the first and second transistors, configured to bias the first transistor with a first voltage signal (see Fig. 1 and col. 3, lines 59-67, where Mai describes that the first transistor 107 receives a bias voltage pbias) and bias the second transistor with a second voltage signal (see Fig. 1 and col. 3, lines 59-67, where Mai describes that the second transistor 109 also receives the bias voltage pbias).
Mai does not specifically disclose: the first voltage signal is a first fraction of a first voltage at the first terminal, and the second voltage signal is a first fraction of a second voltage at the second terminal.
Perraud teaches: a first voltage signal is a first fraction of a first voltage at a first terminal (see Fig. 1 and col. 3, lines 38-50, where Perraud describes a transistor T2 whose base receives a voltage Vs which is a fraction of the voltage of terminal VDD), and a second voltage signal is a first fraction of a second voltage at a second terminal (see Fig. 1 and col. 3, lines 38-50, where Perraud describes a transistor T1 whose base receives a reference voltage Vref; see Fig. 1 and col. 5, lines 2-5, where Perraud describes that the Vs may be sufficient large with regard to the reference voltage Vref).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the first voltage signal is a first fraction of a first voltage at the first terminal, and the second voltage signal is a first fraction of a second voltage at the second terminal, as taught by Perraud to modify the method of Mai in order to attenuate effect of temperature variations, as discussed by Perraud (see col. 2, lines 1-3).
Consider claim 2:
Mai in view of Perraud discloses the transmitter of claim 1 above. Mai discloses: the driver includes second transistor switches coupled to second current sources (see Fig. 1 and col. 3, lines 5-15, where Mai describes that the LVDS transmitter 102 includes transistors 126 and 128, and the transistors 126 is coupled to a current source 130), and wherein the transmitter comprises:
a third circuit having a third transistor coupled between the second transistor switches and the first terminal (see Fig. 1 and col. 3, lines 5-34, where Mai describes a third transistor 110 which in coupled between the transistor 126 and the first node padn) and
a fourth transistor coupled between the second transistor switches and the second terminal (see Fig. 1 and col. 3, lines 5-34, where Mai describes a fourth transistor 112 which in coupled between the transistor 128 and the second node padp); and
a fourth circuit, coupled between the output and gates of the third and fourth transistors, configured to bias the third transistor with a first voltage signal (see Fig. 1 and col. 3, lines 59-67, where Mai describes that the third transistor 110 receives a bias voltage nbias) and bias the fourth transistor with a second voltage signal (see Fig. 1 and col. 3, lines 59-67, where Mai describes that the fourth transistor 112 also receives the bias voltage nbias).
Mai does not specifically disclose: the first voltage signal is a second fraction of the first voltage signal, and the second voltage signal is a second fraction of the second voltage signal.
Perraud teaches: a first voltage signal is a second fraction of a first voltage signal (see Fig. 1 and col. 3, lines 38-50, where Perraud describes a transistor T2 whose base receives a voltage Vs which is a fraction of the voltage of terminal VDD), and a second voltage signal is a second fraction of a second voltage signal (see Fig. 1 and col. 3, lines 38-50, where Perraud describes a transistor T1 whose base receives a reference voltage Vref; see Fig. 1 and col. 5, lines 2-5, where Perraud describes that the Vs may be sufficient large with regard to the reference voltage Vref).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the first voltage signal is a second fraction of the first voltage signal, and the second voltage signal is a second fraction of the second voltage signal, as taught by Perraud to modify the method of Mai in order to attenuate effect of temperature variations, as discussed by Perraud (see col. 2, lines 1-3).
Consider claim 7:
Mai in view of Perraud discloses the transmitter of claim 1 above. Mai discloses: a calibration circuit having an input coupled to the second circuit, the calibration circuit configured to calibrate at least one of the driver or the second circuit in response to the first voltage signal and the second voltage signal (see Fig. 1, col. 2, lines 62-67 and col. 3, lines 1-5, where Mai describes a pre-driver 150 which has an input connected to the driver 102 and provides pre-drive signals pn and nn to the driver 102).
Mai does not specifically disclose: the first fraction of the first voltage signal and the first fraction of the second voltage signal.
Perraud teaches: a first fraction of a first voltage signal (see Fig. 1 and col. 3, lines 38-50, where Perraud describes a transistor T2 whose base receives a voltage Vs which is a fraction of the voltage of terminal VDD), and a first fraction of a second voltage signal (see Fig. 1 and col. 3, lines 38-50, where Perraud describes a transistor T1 whose base receives a reference voltage Vref; see Fig. 1 and col. 5, lines 2-5, where Perraud describes that the Vs may be sufficient large with regard to the reference voltage Vref).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the first fraction of the first voltage signal and the first fraction of the second voltage signal, as taught by Perraud to modify the method of Mai in order to attenuate effect of temperature variations, as discussed by Perraud (see col. 2, lines 1-3).
Consider claim 8:
Mai in view of Perraud discloses the transmitter of claim 7 above. Mai discloses: a level shifter coupled between the calibration circuit and the second circuit (see Fig. 1 and col. 2, lines 37-42, where Mai describes a level sifter 158 that is connected in a loopback circuit which includes the pre-driver 150).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Mai et al. (US 11,581,875 B1) in view of Perraud (US 5,838,149 A), as applied to claim 1 above, and further in view of Ikoma (US 2011/0012769 A1).
Consider claim 3:
Mai in view of Perraud discloses the transmitter of claim 1 above. Mai discloses: the driver includes the first transistor switches and the first current sources (see Fig. 1 and col. 3, lines 5-15, where Mai describes that the LVDS transmitter 102 includes transistors 106 and 108 which are coupled to a current source 172), wherein the first transistor switches comprise source-coupled transistor pairs (see Fig. 1 and col. 3, lines 5-15, where Mai describes the pair of transistors 106 and 108 which are source connected), and wherein gates of the source-coupled transistor pairs comprise an input and drains of the source-coupled transistor pairs comprise an output (see Fig. 1 and col. 3, lines 35-55, where Mai describes that the gate of the transistor 106 receives input signal padp_lo and that the gate of the transistor 108 receives input signal padn_lo).
Mai does not specifically disclose: the driver comprises a digital-to-analog converter (DAC).
Ikoma teaches: a driver comprises a digital-to-analog converter (DAC) (see Fig. 1 and paragraphs 0059-0060, where Ikoma describes a driver circuit that includes pairs of transistors to implement a digital-to-analog (D/A) converter).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the driver comprises a digital-to-analog converter (DAC), as taught by Ikoma to modify the method of Mai in order to achieve excellent communication characteristics, as discussed by Ikoma (see paragraph 0037).
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Mai et al. (US 11,581,875 B1) in view of Perraud (US 5,838,149 A), as applied to claim 1 above, and further in view of Chen et al. (US 2021/0265988 A1).
Consider claim 4:
Mai in view of Perraud discloses the transmitter of claim 1 above. Mai does not specifically disclose: a first voltage divider configured to provide the first fraction of the first voltage signal to the gate of the first transistor and a second voltage divider configured to provide the first fraction of the second voltage signal to the gate of the second transistor.
Chen teaches: a first voltage divider configured to provide a first fraction of a first voltage signal to the gate of a first transistor and a second voltage divider configured to provide a first fraction of a second voltage signal to the gate of a second transistor (see Fig. 12 and paragraph 0079, where Chen describes a first voltage divider 74 which provides a first fraction of voltage 5V to the gate of first transistor Q1, and a second voltage divider 71 which provides a first fraction of voltage 12V to the gate of second transistor Q2 in MCU).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: a first voltage divider configured to provide the first fraction of the first voltage signal to the gate of the first transistor and a second voltage divider configured to provide the first fraction of the second voltage signal to the gate of the second transistor, as taught by Chen to modify the method of Mai in order to lower output voltage, as discussed by Chen (see paragraph 0004).
Consider claim 5:
Mai in view of Perraud and Chen discloses the transmitter of claim 4 above. Mai does not specifically disclose: the first voltage divider comprises a first resistor coupled between the first terminal and the gate of the first transistor and a second resistor coupled between the gate of the first transistor and a first node, and wherein the second voltage divider comprises a third resistor coupled between the second terminal and the gate of the second transistor and a fourth resistor coupled between the gate of the second transistor and the first node.
Chen teaches: the first voltage divider comprises a first resistor coupled between the first terminal and the gate of the first transistor (see Fig. 12 and paragraph 0079, where Chen describes that the first voltage divider 74 includes a first resistor 75 which is connected between the 5V power supply and the gate of the first transistor Q1) and a second resistor coupled between the gate of the first transistor and a first node (see Fig. 12 and paragraph 0079, where Chen describes that the first voltage divider 74 includes a second resistor 76 which is connected between the gate of the first transistor Q1 and ground), and wherein the second voltage divider comprises a third resistor coupled between the second terminal and the gate of the second transistor (see Fig. 12 and paragraph 0079, where Chen describes that the second voltage divider 71 includes a third resistor 72 which is connected between the 12V power supply and the gate of the second transistor Q2) and a fourth resistor coupled between the gate of the second transistor and the first node (see Fig. 12 and paragraph 0079, where Chen describes that the second voltage divider 71 includes a fourth resistor 73 which is connected between the gate of the second transistor Q2 and the ground).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the first voltage divider comprises a first resistor coupled between the first terminal and the gate of the first transistor and a second resistor coupled between the gate of the first transistor and a first node, and wherein the second voltage divider comprises a third resistor coupled between the second terminal and the gate of the second transistor and a fourth resistor coupled between the gate of the second transistor and the first node, as taught by Chen to modify the method of Mai in order to lower output voltage, as discussed by Chen (see paragraph 0004).
Claims 9, 10, 12, 15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mai et al. (US 11,581,875 B1) in view of Ikoma (US 20110012769 A1), and further in view of Perraud (US 5,838,149 A).
Consider claims 9 and 17:
Mai discloses an apparatus (see Fig. 1 and col. 2, lines 5-10, where Mai describes a LVDS transmitter 102), comprising:
A load circuit coupled to a first node and a second node (see Fig. 1 and col. 2, lines 15-20, where Mai describes that the transmitter 102 outputs differential signals at first node padn and second node padp);
a driver coupled to the load circuit (see col. 1, lines 45-50, where Mai describes that the LVDS transmitter 102 is a driver; see Fig. 1 and col. 2, lines 15-20, where Mai describes that the LVDS transmitter 102 includes the first node padn and the second node padp);
a first circuit having a first transistor coupled between slices of the DAC and the first node (see Fig. 1 and col. 3, lines 5-34, where Mai describes a first transistor 107 which in coupled between the transistor 106 and the first node padn), and
a second transistor coupled between the slices and the second node (see Fig. 1 and col. 3, lines 5-34, where Mai describes a second transistor 109 which in coupled between the transistor 108 and the second node padp); and
a second circuit, coupled to the first and second nodes and gates of the first and second transistors, configured to bias the first transistor with a first voltage signal (see Fig. 1 and col. 3, lines 59-67, where Mai describes that the first transistor 107 receives a bias voltage pbias) and bias the second transistor with a second voltage signal (see Fig. 1 and col. 3, lines 59-67, where Mai describes that the second transistor 109 also receives the bias voltage pbias).
Mai does not specifically disclose: (1), the driver having a digital-to-analog converter (DAC), and (2), the first voltage signal is a first fraction of a first voltage signal from the first node, and the second voltage signal is a first fraction of a second voltage signal from the second node.
Regarding (1), Ikoma teaches: the driver having a digital-to-analog converter (DAC) (see Fig. 1 and paragraphs 0059-0060, where Ikoma describes a driver circuit that includes pairs of transistors to implement a digital-to-analog (D/A) converter).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the driver having a digital-to-analog converter (DAC), as taught by Ikoma to modify the method of Mai in order to achieve excellent communication characteristics, as discussed by Ikoma (see paragraph 0037).
Regarding (2), Perraud teaches: a first voltage signal is a first fraction of a first voltage signal from a first node (see Fig. 1 and col. 3, lines 38-50, where Perraud describes a transistor T2 whose base receives a voltage Vs which is a fraction of the voltage of terminal VDD), and a second voltage signal is a first fraction of a second voltage signal from a second node (see Fig. 1 and col. 3, lines 38-50, where Perraud describes a transistor T1 whose base receives a reference voltage Vref; see Fig. 1 and col. 5, lines 2-5, where Perraud describes that the Vs may be sufficient large with regard to the reference voltage Vref).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the first voltage signal is a first fraction of a first voltage signal from the first node, and the second voltage signal is a first fraction of a second voltage signal from the second node, as taught by Perraud to modify the method of Mai and Ikoma in order to attenuate effect of temperature variations, as discussed by Perraud (see col. 2, lines 1-3).
Consider claim 10:
Mai in view of Perraud and Ikoma discloses the apparatus of claim 9 above. Mai discloses: the load circuit comprises: an impedance coupled to the first node and the second node (see Fig. 1 and col. 3, lines 6-20, where Mai describes that the first node padn is connected to field effect transistor 110, and that the second node padp is connected to field effect transistor 112); and a device coupled to the impedance through a transmission line (see Fig. 1 and col. 3, lines 35-55, where Mai describes that the field effect transistor 110 is connected to a circuit node 142, and that the field effect transistor 112 is connected to a circuit node 146).
Consider claim 12:
Mai in view of Perraud and Ikoma discloses the apparatus of claim 9 above. Mai discloses: the slices of the DAC include transistor switches coupled to current sources (see Fig. 1 and col. 3, lines 5-15, where Mai describes that the LVDS transmitter 102 includes transistors 106 and 108 which are coupled to a current source 172), the apparatus further comprising: an integrated circuit (IC) having the driver and the first circuit, the first transistor, the second transistor, and transistors of the transistor switches being core transistors for a technology node of the IC (see Fig. 1 and col. 2, lines 5-10, where Mai describes that the LVDS transmitter 102 is an integrated circuit (IC); see col. 1, lines 45-50, where Mai describes that the LVDS transmitter 102 is a driver; see Fig. 1 and col. 3, lines 5-15, where Mai describes that the LVDS transmitter 102 includes transistors 106 and 108 which are coupled to a current source 172).
Consider claim 15:
Mai in view of Perraud and Ikoma discloses the apparatus of claim 9 above. Mai discloses: the load circuit comprises a first impedance coupled between the first node and a voltage supply (see Fig. 1 and col. 3, lines 6-34, where Mai describes a transistor 106 which is coupled between the first node padn and voltage supply Vdda), and a second impedance coupled between the second node and the voltage supply (see Fig. 1 and col. 3, lines 6-34, where Mai describes a transistor 108 which is coupled between the second node padp and the voltage supply Vdda).
Consider claim 18:
Mai in view of Perraud and Ikoma discloses the method of claim 17 above. Mai discloses: supplying, from the DAC in response to the codes, a current signal to the load circuit through the first and second transistors (see Fig. 1 and col. 3, lines 5-20, where Mai describes that a current source 172 supplies a current to output nodes through transistor 106 and transistor 108).
Consider claim 19:
Mai in view of Perraud and Ikoma discloses the method of claim 17 above. Mai discloses: receiving, at an input of a calibration circuit, the fraction of the first voltage signal and the fraction of the second voltage signal (see Fig. 1 and col. 2, lines 52-67, where Mai describes a pre-driver circuit 150 which receives SE2DIFF out1 and SE2DIFF out2 from SE2DIFF 156).
Consider claim 20:
Mai in view of Perraud and Ikoma discloses the method of claim 19 above. Mai discloses: adjusting, by the calibration circuit in response to the input thereof, at least one device in the transmitter (see Fig. 1, col. 2, lines 62-67 and col. 3, lines 1-5, where Mai describes that the pre-driver 150 provides pre-drive signals pn and nn to the transmitter 102 in a loopback circuit).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Mai et al. (US 11,581,875 B1) in view of Perraud (US 5,838,149 A) and Ikoma (US 20110012769 A1), as applied to claim 10 above, and further in view of Venkataraman et al. (US 2022/0069545 A1).
Consider claim 11:
Mai in view of Perraud and Ikoma discloses the apparatus of claim 10 above. Mai discloses: the device comprises a diode (see Fig. 1 and col. 3, lines 5-20, where Mai describes that the circuit node 142 is connected to diode 114).
Mai does not specifically disclose: the diode is a laser diode.
Venkataraman teaches: a laser diode (see paragraph 0015, where Venkataraman that laser diodes are used).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the diode is a laser diode, as taught by Venkataraman to modify the method of Mai in order to generate high-power optical pulses, as discussed by Venkataraman (see paragraph 0015).
Allowable Subject Matter
Claims 6, 13, 14 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIHONG YU whose telephone number is (571)270-5147. The examiner can normally be reached 10:00 am-6:00 pm EST Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hannah S. Wang can be reached at (571)272-9018. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LIHONG YU/Primary Examiner, Art Unit 2631