Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS COMPRISING CONDUCTIVE HOT MELT LAYER, AND A MANUFACTURING METHOD THEREOF
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 10-12, 15-16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. [US PGPUB 20210242117] in view of Kanapady et al. [US PGUB 20200357593] (hereinafter Hung and Kanapady).
Regarding claim 1, Hung teaches a semiconductor device, comprising:
a package body (170 or 170/UF, Para 26/27);
a chip (140, Para 21);
a redistribution layer (120, Para 22); and
a passive device (left fuse 150, Para 24);
wherein the chip, the redistribution layer, and the passive device are packaged in the package body (Fig. 1I; where the redistribution layer is in the package body because of portion 122A of the redistribution layer is in the package body (Fig. 1A/I));
wherein the redistribution layer comprises a first conductive pad (left pad 122A connected to left pad of the left fuse, Fig. 1I) and a second conductive pad (right pad 122A connected to right pad of the left fuse, Fig. 1I) that are disposed at an interval from each other (Fig. 1A/I) and insulated from each other (Fig. 1A/I), wherein a part of the redistribution layer other than the first conductive pad and the second conductive pad is connected to a pin of the chip (Fig. 1I); and
wherein the conductive passive device is formed on a surface of the first conductive pad and a surface of the second conductive pad (Fig. 1I), and is in electrical contact with both the first conductive pad and the second conductive pad (Fig. 1I).
Hung does not specifically disclose a conductive hot melt layer.
However, since the passive device 150 disclosed by Hung is a fuse, a person having ordinary skills in the art will understand that the fuse of Hung would comprise a conductive hot melt layer.
Referring to the invention of Kanapady, Kanapady discloses a structure of a fuse, wherein the fuse comprises a conductive hot melt layer (fusible wire 112, Para 23/30).
In view of such teaching by Kanapady, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have to the invention of Hung comprise the teachings of Kanapady at least based on the rationale combining prior art elements/teachings according to known methods to yield predictable results (MPEP 2143.I.A) or applying a known technique to a known device (method, or product) ready for improvement to yield predictable results (MPEP 2143.I.D).
In view of such combination, the conductive hot melt layer of the fuse would be packaged in the package body; and
the conductive hot melt layer formed on a surface of the first conductive pad and a surface of the second conductive pad, and being in electrical contact with both the first conductive pad and the second conductive pad (it should be noted that “directly on the surface” is not claimed).
Regarding claim 2, Hung teaches a semiconductor device wherein the semiconductor device comprises an insulation layer (124, Para 44, Fig. 1A/I), wherein the insulation layer is located between the first conductive pad and the second conductive pad (Fig. 1A/I).
Regarding claim 10, Hung teaches a semiconductor device wherein the insulation layer comprises a solder resist material (Para 11).
Regarding claim 11, Hung teaches a semiconductor device wherein the package body comprises a first package body (UF, Para 26, Fig. 1C/I) and a second package body (170, Fig. 1I), wherein the first package body and the second package body are combined to jointly package the chip, the redistribution layer, and the conductive hot melt layer (Fig. 1C/I), wherein the chip is packaged in the first package body (Fig. 1C/I), wherein the pin is exposed outside the first package body (Fig. 1C/I), and wherein both the redistribution layer and the conductive hot melt layer are packaged in the second package body (Fig. 1C/I).
Regarding claim 12, Hung teaches a semiconductor device wherein the package body comprises a first package body (UF, Para 26, Fig. 1C/I) and a second package body (170, Fig. 1I), wherein the first package body and the second package body are combined to jointly package the chip, the redistribution layer, and the conductive hot melt layer (Fig. 1C/I), wherein the chip is packaged in the first package body (Fig. 1C/I), wherein the pin is exposed outside the first package body (Fig. 1C/I), and wherein both the redistribution layer and the conductive hot melt layer are packaged in the second package body (Fig. 1C/I).
Regarding claim 15, Hung teaches a semiconductor device wherein the semiconductor device comprises a power semiconductor device (at least in view of the chip being a voltage regulator chip, Para 21).
Regarding claim 16, Hung teaches an electronic apparatus, comprising:
a circuit board (Para 50); and
a semiconductor device (device of Fig. 1I);
wherein the semiconductor device is disposed on the circuit board (Para 50);
wherein the semiconductor device comprises:
a package body (170 or 170/UF, Para 26/27);
a chip (140, Para 21);
a redistribution layer (120, Para 22); and
a passive device (left fuse 150, Para 24);
wherein the chip, the redistribution layer, and the passive device are packaged in the package body (Fig. 1I; where the redistribution layer is in the package body because of portion 122A of the redistribution layer is in the package body (Fig. 1A/I));
wherein the redistribution layer comprises a first conductive pad (left pad 122A connected to left pad of the left fuse, Fig. 1I) and a second conductive pad (right pad 122A connected to right pad of the left fuse, Fig. 1I) that are disposed at an interval from each other (Fig. 1A/I) and insulated from each other (Fig. 1A/I), wherein a part of the redistribution layer other than the first conductive pad and the second conductive pad is connected to a pin of the chip (Fig. 1I); and
wherein the conductive passive device is formed on a surface of the first conductive pad and a surface of the second conductive pad (Fig. 1I), and is in electrical contact with both the first conductive pad and the second conductive pad (Fig. 1I).
Regarding claim 18, Hung teaches a semiconductor device manufacturing method, comprising:
forming a redistribution layer (120, Para 22), wherein the redistribution layer comprises a first conductive pad (left pad 122A connected to left pad of the left fuse, Fig. 1I) and a second conductive pad (right pad 122A connected to right pad of the left fuse, Fig. 1I) that are disposed at an interval from each other (Fig. 1A/I) and insulated from each other (Fig. 1A/I);
forming a passive device on the first conductive pad and the second conductive pad (Fig. 1I), wherein the passive device is in electrical contact with both the first conductive pad and the second conductive pad (Fig. 1I);
connecting a pin of a chip to a part of the redistribution layer other than the first conductive pad and the second conductive pad (Fig. 1I); and packaging the chip, the redistribution layer, and the passive device (Fig. 1I, i.e., packaged in material 170 or 170/UF, Para 26/27).
Hung does not specifically disclose a conductive hot melt layer.
However, since the passive device 150 disclosed by Hung is a fuse, a person having ordinary skills in the art will understand that the fuse of Hung would comprise a conductive hot melt layer.
Referring to the invention of Kanapady, Kanapady discloses a structure of a fuse, wherein the fuse comprises a conductive hot melt layer (fusible wire 112, Para 23/30).
In view of such teaching by Kanapady, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have to the invention of Hung comprise the teachings of Kanapady at least based on the rationale combining prior art elements/teachings according to known methods to yield predictable results (MPEP 2143.I.A) or applying a known technique to a known device (method, or product) ready for improvement to yield predictable results (MPEP 2143.I.D).
In view of such combination, a person having ordinary skills in the art will understand that the limitation of the claim will be met.
Regarding claim 19, Hung teaches a semiconductor device wherein forming the redistribution layer comprises:
packaging the chip by using a first packaging material (170 or 170/UF, Para 26/27), wherein the pin is exposed (Fig. 1C); and
forming the redistribution layer on the first packaging material (Fig. 1C);
wherein the method further comprises: forming an insulation layer (124, Para 10) between the first conductive pad and the second conductive pad (Fig. 1C), wherein the insulation layer isolates the first conductive pad from the second conductive pad (Fig. 1C).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Kanapady and further in view of Yoneda [US PGUB 20210074502].
Regarding claim 14, the combined invention of Hung and Kanapady teaches the limitation of claim 1 upon which it depends.
The combined invention does not specifically disclose wherein the conductive hot melt layer comprises solder.
Referring to the invention of Yoneda, Yoneda discloses various materials that can used for conductive hot melt layer 2, wherein the conductive hot melt layer can include solder (Para 63).
In view of such teaching by Yoneda, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the combined invention comprise the teachings of Yoneda at least based on the rationale of simple substitution of one known element/structure with a suitable another to obtain predictable results (MPEP 2143.I.B), such as, controlling the rating of the fuse.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Kanapady and further in view of Kerfoot et al. [US Patent 5581171] (hereinafter Kerfoot).
Regarding claim 17, the combined invention of Hung and Kanapady teaches the limitation of claim 16 upon which it depends.
The combined invention does not specifically disclose that the electronic apparatus further comprising at least one of: a motor controller; a vehicle-mounted charger; a power supply; an inverter; an electric vehicle; a data center; a photovoltaic power generation device; or a server.
However, it is noted that Hung discloses that the chip of the device can be of direct types of chips, to include a memory chip, a logic chip, a voltage regulator chip (Para 21). At least in view of such teaching, it would have been obvious to a person having ordinary skills in the art that the disclosure of Hung could be applied to a data center of a server --due to the chip being a memory chip.
Moreover, referring to the invention of Kerfoot, Kerfoot teaches implementing a voltage regulator chip in an electric vehicle/ a vehicle-mounted charger (Col. 2, lines 33-36/Col. 8, lines 37-50).
In view of such teaching by Kerfoot, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the combined invention comprise the teachings of Kerfoot at least based on the rationale of relying on teachings, suggestions, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Kanapady and further in view of Khaderbad et al. [US PGPUB 20190164817] (hereinafter Khaderbad).
Regarding claim 8, the combined invention of Hung and Kanapady teaches the limitation of claim 2 upon which it depends.
The combined invention does not specifically disclose wherein the insulation layer has hydrophobic performance.
Referring to the invention of Khaderbad, Khaderbad discloses filling trenches 104/106/108 (Para 61) in dielectric layers 87/88/102 with conductive material 114/116/118, and wherein the surfaces of the trenches can be treated to cause the surfaces to change from hydrophilic to hydrophobic, or vice versa (Para 61 –thus the surface can have hydrophobic performance).
In view of such teaching by Khaderbad, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the combined invention comprise the teachings of Khaderbad to improve the deposition of the conductive material in the trenches.
In view of another interpretation of the Hung reference, claims 1-3 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. [US PGPUB 20210242117] in view of Kanapady et al. [US PGUB 20200357593] (hereinafter Hung117 and Kanapady).
Regarding claim 1, Hung117 teaches a semiconductor device, comprising:
a package body (170 or 170/UF, Para 26/27);
a chip (140, Para 21);
a redistribution layer (120, Para 22); and
a passive device (left fuse 150, Para 24);
wherein the chip, the redistribution layer, and the passive device are packaged in the package body (Fig. 1I; where the redistribution layer is in the package body because of portion 122A of the redistribution layer is in the package body (Fig. 1A/I));
wherein the redistribution layer comprises a first conductive pad (see annotated Fig. 1I) and a second conductive pad (see annotated Fig. 1I) that are disposed at an interval from each other (Fig. 1A/I) and insulated from each other (Fig. 1A/I), wherein a part of the redistribution layer other than the first conductive pad and the second conductive pad is connected to a pin of the chip (Fig. 1I); and
wherein the conductive passive device is formed on a surface of the first conductive pad and a surface of the second conductive pad (Fig. 1I), and is in electrical contact with both the first conductive pad and the second conductive pad (Fig. 1I).
Hung117 does not specifically disclose a conductive hot melt layer.
However, since the passive device 150 disclosed by Hung is a fuse, a person having ordinary skills in the art will understand that the fuse of Hung would comprise a conductive hot melt layer.
Referring to the invention of Kanapady, Kanapady discloses a structure of a fuse, wherein the fuse comprises a conductive hot melt layer (fusible wire 112, Para 23/30).
In view of such teaching by Kanapady, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have to the invention of Hung117 comprise the teachings of Kanapady at least based on the rationale combining prior art elements/teachings according to known methods to yield predictable results (MPEP 2143.I.A) or applying a known technique to a known device (method, or product) ready for improvement to yield predictable results (MPEP 2143.I.D).
In view of such combination, the conductive hot melt layer of the fuse would be packaged in the package body; and
the conductive hot melt layer formed on a surface of the first conductive pad and a surface of the second conductive pad, and being in electrical contact with both the first conductive pad and the second conductive pad (it should be noted that “directly on the surface” is not claimed).
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Annotated Fig. 1I
Regarding claim 2, Hung117 teaches a semiconductor device wherein the semiconductor device comprises an insulation layer (124, Para 44, Fig. 1A/I), wherein the insulation layer is located between the first conductive pad and the second conductive pad (Fig. 1A/I).
Regarding claim 3, Hung117 teaches a semiconductor device wherein the insulation layer and the conductive hot melt layer further jointly cover the surface of the first conductive pad, and/or the insulation layer and the conductive hot melt layer further jointly cover the surface of the second conductive pad (Fig. 1I –wherein directly covering is not claimed).
Regarding claim 6, Hung117 teaches a semiconductor device wherein the insulation layer comprises a solder resist material (Para 11).
Regarding claim 7, Hung117 teaches a semiconductor device wherein the package body comprises a first package body (UF, Para 26, Fig. 1C/I) and a second package body (170, Fig. 1I), wherein the first package body and the second package body are combined to jointly package the chip, the redistribution layer, and the conductive hot melt layer (Fig. 1C/I), wherein the chip is packaged in the first package body (Fig. 1C/I), wherein the pin is exposed outside the first package body (Fig. 1C/I), and wherein both the redistribution layer and the conductive hot melt layer are packaged in the second package body (Fig. 1C/I).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Hung117 in view of Kanapady and further in view of Khaderbad et al. [US PGPUB 20190164817] (hereinafter Khaderbad).
Regarding claim 4, the combined invention of Hung117 and Kanapady teaches the limitation of claim 3 upon which it depends.
The combined invention does not specifically disclose wherein the insulation layer has hydrophobic performance.
Referring to the invention of Khaderbad, Khaderbad discloses filling trenches 104/106/108 (Para 61) in dielectric layers 87/88/102 with conductive material 114/116/118, and wherein the surfaces of the trenches can be treated to cause the surfaces to change from hydrophilic to hydrophobic, or vice versa (Para 61 –thus the surface can have hydrophobic performance).
In view of such teaching by Khaderbad, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the combined invention comprise the teachings of Khaderbad to improve the deposition of the conductive material in the trenches.
Regarding claim 5, Hung117 teaches a semiconductor device wherein the package body comprises a first package body (UF, Para 26, Fig. 1C/I) and a second package body (170, Fig. 1I), wherein the first package body and the second package body are combined to jointly package the chip, the redistribution layer, and the conductive hot melt layer (Fig. 1C/I), wherein the chip is packaged in the first package body (Fig. 1C/I), wherein the pin is exposed outside the first package body (Fig. 1C/I), and wherein both the redistribution layer and the conductive hot melt layer are packaged in the second package body (Fig. 1C/I).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hung117 in view of Kanapady and further in view of Khaderbad et al. [US PGPUB 20190164817] (hereinafter Khaderbad).
Regarding claim 8, the combined invention of Hung117 and Kanapady teaches the limitation of claim 2 upon which it depends.
The combined invention does not specifically disclose wherein the insulation layer has hydrophobic performance.
Referring to the invention of Khaderbad, Khaderbad discloses filling trenches 104/106/108 (Para 61) in dielectric layers 87/88/102 with conductive material 114/116/118, and wherein the surfaces of the trenches can be treated to cause the surfaces to change from hydrophilic to hydrophobic, or vice versa (Para 61 –thus the surface can have hydrophobic performance).
In view of such teaching by Khaderbad, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the combined invention comprise the teachings of Khaderbad to improve the deposition of the conductive material in the trenches.
Regarding claim 9, Hung117 teaches a semiconductor device wherein the package body comprises a first package body (UF, Para 26, Fig. 1C/I) and a second package body (170, Fig. 1I), wherein the first package body and the second package body are combined to jointly package the chip, the redistribution layer, and the conductive hot melt layer (Fig. 1C/I), wherein the chip is packaged in the first package body (Fig. 1C/I), wherein the pin is exposed outside the first package body (Fig. 1C/I), and wherein both the redistribution layer and the conductive hot melt layer are packaged in the second package body (Fig. 1C/I).
Allowable Subject Matter
Claims 13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ISMAIL A MUSE/
Primary Examiner, Art Unit 2812
