DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Merget (Publication No.: US 2018/0180826 A1).
Regarding claim 7, 1, 5, Merget teaches An optical subassembly comprising a substrate (e.g. “substrate” as in paragraph [0081] and throughout; reference numeral 200 in Figure 2a) ; an electrical interconnection layer (reference numeral 107, 207a, 207b in Figure 2a and Figure 2b) disposed on the substrate, wherein the electrical interconnection layer comprises at least a first electrical interconnection line (reference numeral 209a in Figure 2b) ; a waveguide (reference numeral 101, 102, 103 in Figure 2b) formed on the interconnection layer, wherein the waveguide comprises a core layer (reference numeral 101 in Figure 2b) positioned between two cladding layers (reference numeral 102, 103 in Figure 2b), wherein the core layer comprises a first optical axis configured to show a first propagation direction of optical signals in the waveguide (e.g. as illustrated in Figure 2a), wherein the core layer and the cladding layers comprise silicon oxynitride (e.g. “silicon oxi-nitride (SiON)” auxiliary cladding layer(s) as in paragraph [0065]; “SiON core layer” as in paragraph [0066]; “one or more auxiliary cladding layers” as in paragraph [0063]); an encapsulation layer (reference numeral 200b in Figure 2a) disposed on the waveguide to cover at least side surfaces of the core layer and the cladding layers (e.g. as illustrated in Figure 2b); a cavity (reference numeral 200b in Figure 2c; e.g. “cavity” as in paragraph [0009] and throughout) formed on and through the encapsulation layer; wherein the waveguide comprises a facet (reference numeral 122 in Figure 2c) coupled to the cavity, wherein the cavity is configured to house a device (e.g. “flip-chip photonic chip (FCPC)” as in paragraph [0003] and throughout; reference numeral 100 in Figure 2a) with the device configured to communicate optically with the waveguide, a first alignment aid element (leftmost reference numeral 223 in Figure 2b, Figure 2c) formed in the cavity, wherein the first alignment aid comprises a first outer surface (reference numeral 221 in Figure 2c), wherein the first outer surface is separated by a first distance with the first optical axis (e.g. as illustrated in Figure 2c), wherein the first distance is configured to match with a second distance (e.g. the distance from the top of reference numeral 203 to the optical axis of waveguide 201 in Figure 2c), wherein the second distance is a separation between a second outer surface of the device (reference numeral 121 in Figure 2c) and a second optical axis of the device with the second optical axis configured to show a second propagation direction of optical signals to or from the device (e.g. the optical axis of waveguide 201 in Figure 2c illustrated as “B” in Figure 2a), wherein the device is configured to be electrically coupled to the at least a first electrical interconnection line (reference numeral 107, 207a, 207b, 209a, 209b in Figure 2a and Figure 2b), wherein the matching is configured to allow an alignment of the first optical axis with the second optical axis when the device is assembled in the cavity on the substrate with the second outer surface contacting with the first outer surface (e.g. “alignment” as in paragraph [0081] and as illustrated in Figure 2b, Figure 2c).
Regarding claim 2, Merget teaches An optical subassembly as in claim 1, wherein the at least a first electrical interconnection line (reference numeral 209a in Figure 2b) is configured to be electrically coupled to a first terminal (reference numeral 107 in Figure 2b) of a first device disposed on the electrical interconnection layer, wherein the first device comprises an optical component or an optoelectrical component (e.g. “flip-chip photonic chip (FCPC)” as in paragraph [0003] and throughout) configured to be aligned with the waveguide.
Regarding claim 3, 4, 6, Merget teaches An optical subassembly as in claim 1, wherein the at least a first electrical interconnection line (reference numeral 209a in Figure 2b) is configured to be electrically coupled to a first terminal of a first device disposed on the electrical interconnection layer (reference numeral 107 in Figure 2b), wherein the first device comprises an optical element or an optoelectrical element configured to be aligned with the waveguide (e.g. “flip-chip photonic chip (FCPC)” as in paragraph [0003] and throughout), the optical assembly further comprising a second device (e.g. “a second photonic device” as in paragraph [0026]) fabricated on the substrate under the electrical interconnection layer, wherein the at least a first electrical interconnection line or a second electrical interconnection line (reference numeral 209b in Figure 2a) in the electrical interconnection layer is coupled to a second terminal of the second device, wherein the second device is configured for electrically communication with the first device (e.g. via electrical interconnects 207a, 207b, 209a, 209bas illustrated in Figure 2a).
Regarding claim 8, Merget teaches A substrate as in claim 7, further comprising a second alignment aid element (e.g. rightmost reference numeral 223 in Figure 2b, Figure 2c) comprising a third outer surface (e.g. rightmost reference numeral 221 in Figure 2b) parallel to the first outer surface, wherein the third outer surface is in a vicinity of the first optical axis (e.g. as illustrated in Figure 2a, Figure 2b), wherein the second alignment aid element comprises a fiducial pattern (reference numeral 223 in Figure 2a, Figure 2b) configured for assisting in placing the device in the cavity on the substrate.
Regarding claim 9, Merget teaches A substrate as in claim 7, further comprising a third alignment aid element (e.g. lower leftmost reference numeral 221 in Figure 2a) comprising a fourth outer surface not parallel to the first outer surface (e.g. any of the vertical outer surfaces of columns 223 not parallel with outer surfaces 221 of rightmost column 223 as illustrated in Figures 2a, Figure 2b, Figure 2c), wherein the fourth outer surface is configured to be separated with a fifth outer surface of the device (e.g. lower leftmost reference numeral 121 in Figure 2a) by a distance less than an alignment tolerance between the first and second optical axes (e.g. “improved alignment” as in paragraph [0080]).
Regarding claim 10, Merget teaches A substrate as in claim 7, further comprising a fourth alignment aid element (e.g. lower rightmost reference numeral 221 in Figure 2a) comprising an alignment constraint (e.g. the column 223 as illustrated in Figure 2b) for laterally aligning an optical fiber, wherein the alignment constraint is configured to align an optical axis of the optical fiber with the first optical axis in a lateral direction (e.g. “alignment” as in paragraph [0081] and as illustrated in Figure 2b, Figure 2c).
Regarding claim 11, Merget teaches A substrate as in claim 7, wherein the first or second alignment aid element comprises a pillar (e.g. the column 223 as illustrated in Figure 2b) or a recess (reference numeral 123 in Figure 2c) comprising a top layer (reference numeral 121 in Figure 2c) comprising a top surface with the top surface being the first or third outer surface, respectively.
Regarding claim 12, Merget teaches A substrate as in claim 7, wherein the first or second alignment aid element comprises a top layer (reference numeral 221 in Figure 2c) comprising an etch selectivity as compared to the core and cladding layers of the waveguide (e.g. “etching process is selective” as in paragraph [0034] and throughout).
Regarding claim 13, Merget teaches A substrate as in claim 7, wherein the first or second alignment aid element comprises a top layer comprising Al, AlOx, Au, Ag, Ni, Pt, Ti, TiOx, Ta, TaOx (e.g. “tentalum oxide” (sic) as in paragraph [0065]), or an allow thereof (e.g. “aluminum nitride” as in paragraph [0065]).
Regarding claim 14, Merget teaches A substrate as in claim 7, wherein the first alignment aid element and the second alignment aid element comprise a top hard mask layer (reference numeral 221 in Figure 2b) with top surfaces of the hard mask layer being the first outer surface and the third outer surface.
Regarding claim 15, Merget teaches A substrate as in claim 7, wherein the third outer surface is aligned with the first surface with a tolerance of a photolithography process (e.g. via “lithographic step” as in paragraph [0069]) .
Regarding claim 16, Merget teaches A substrate as in claim 7, wherein the fourth outer surface (e.g. any of the vertical outer surfaces of columns 223 not parallel with outer surfaces 221 of rightmost column 223 as illustrated in Figures 2a, Figure 2b, Figure 2c) is configured to establish a limit for the device optical component to travel in a direction parallel to the lateral plane to be within the alignment tolerance.
Regarding claim 17, Merget teaches A substrate as in claim 16, wherein the alignment tolerance is less than 2 microns (e.g. “micrometer to sub-micrometer precision in their relative alignment” as in paragraph [0004]; e.g. “with an accuracy better than one of ±1 μm, ±1.5 μm or ±2 μm” as in paragraph [0083]).
Regarding claim 18, Merget teaches A substrate as in claim 7, wherein the fourth outer surface (e.g. any of the vertical outer surfaces of columns 223 not parallel with outer surfaces 221 of rightmost column 223 as illustrated in Figures 2a, Figure 2b, Figure 2c) is separated with the fifth outer surface by a distance less than 1 micron (e.g. “Four stop areas 121 on the photonic device 100 are in engagement with four corresponding stop surfaces 221 that belong to the PIC chip 200” as in paragraph [0081]).
Regarding claim 19, Merget teaches A substrate as in claim 7, wherein the third alignment aid element (e.g. lower leftmost reference numeral 221 in Figure 2a) is configured to prevent misalignments of the second optical axis with the first optical axis by limiting movements of the device during a soldering aligning process.
Regarding claim 20, Merget teaches A substrate as in claim 7, wherein the fourth alignment aid element (e.g. lower leftmost reference numeral 221 in Figure 2a) comprises a v-groove alignment aid (e.g. the surface that engages surface 123 in Figure 2b) disposed along the optical fiber (reference numeral 101 in Figure 2b).
Conclusion
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/AGUSTIN BELLO/Primary Examiner, Art Unit 2635