DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been presented and pending in the application.
About the Invention
Examiner notes that, when the examiner applies Broadest Reasonable Interpretation, the claimed invention of a broadly recited claims 1 or 2 appear to be directed to a generic input/output-controlled data transferring system (i.e., the “claimed server system” & “debug log” are not utilized/supported by the claimed invention); therefore, clear metes and bounds of the claimed invention appears to be hidden or not clearly claimed by the claimed recitations in view of the support of the specification. In other words, for example, a typically well-known/available computing device performs or provides the capacity/functionality of the claimed invention of generic input/output-controlled data transferring functions/operations; therefore, the metes and bounds of the claimed invention is unclear from the context of the claimed invention, without more recitations.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims; consequently, the further limiting dependent claims 4-20 are similarly allowable for the reasons of the parent claim 3.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Puthillathe et al. (US 2018/0314611 A1).
The examiner relies on the entire teachings of the Puthillathe reference for this rejection; hence, the examiner advises the applicant to carefully consider the entire teachings of the Puthillathe reference to better understand the examiner position and the examiner’s interpretations applied to the claimed invention with respect to the teachings of the Puthillathe reference.
The Puthillathe reference teaches functionally equivalent limitations/recitations of the claimed invention, when the examiner applies Broadest Reasonable Interpretation, as follows:
CLAIMS 1-2
Puthillathe REF Teachings (emphasis underlined)
1.A server system, comprising:
Fig 2, par 19, “information handling system 100 is configured as a host server 200”
a first control circuit, wherein the first control circuit comprises:
Fig 1-2, par 14, “information handling system 100 can include…one or more processors…102 and 104”
a first controller;
Fig 1-2, par 14, “information handling system 100 can include…one or more processors…102 and 104” (examiner notes that either one of the processors teaches the controller)
a second controller;
Fig 1-2, par 14, “information handling system 100 can include…one or more processors…102 and 104” (examiner notes that either one of the processors teaches the controller)
a first input/output circuit coupled to the first controller; and a second input/output circuit coupled to the second controller and the first input/output circuit;
Fig 1-2, par 15, “I/O channel 112 includes…PCI…PCIe…or combination thereof…Chipset 110 can also include one or more other I/O interfaces…ISA…SCSI…I2C…SPI…USB…”; par 17, “I/O interface 170 to add-on resource 174 and to network interface 180…Peripheral interface 172…” (examiner notes that Chipset, I/O interface and/or I/O channel teaches claimed input/output circuits)
wherein the second controller is configured to transmit a debug log of the first control circuit to the second input/output circuit, and the second input/output circuit is configured to transmit the debug log of the first control circuit to the first input/output circuit; and
Par 19, “BMC 204…has its own processor 206, memory device 208, and networking capabilities…204 has one or more physical communications links and interfaces to the motherboard 202…may thus monitor and report the functions and performance of the host server 200 via a separate network interface…”; par 20, “204 may diagnose, or debug the operating system 216” (examiner notes that the BMC having processor, similar to the 102/104, teaches the transmit a debug log by the second controller of the claimed invention)
a second control circuit coupled between the first input/output circuit and the second input/output circuit, wherein the second control circuit is configured to selectively control data to be transmitted from the first input/output circuit to the second input/output circuit.
Fig 4, par 25, “controller 204 may thus have…USB input/output multiplexer 252 that maps data 254 swapped between the first virtual debug device 250a and the second virtual debug device 250b during debugging operation 214…data 254 associated with the dedicated debug 218…may be redirected to the USB bus controller 212…data 254 associated with the virtual target device 232…may be passed or redirected to the virtual host device 230” (examiner notes that the combinations of the USB I/O Multiplexer 252 & USB Hub 212 teaches the claimed selectively controlling data to be transmitted); the above similar teachings can be found on figs 5-8 with accompanying descriptions
The examiner notes that the Puthillathe reference appears, not expressly disclose only two claimed input/output circuits, to redundantly & openly teaches two or more input/output circuits for providing the functionally equivalent limitations of the claimed invention; however, utilizing two or more input/output circuits for performing are well-known and commonly practices in the art of transferring data between two points, as clearly evidenced by the teachings of the Puthillathe reference detailed above that teaches functionally equivalent limitations of the claimed invention; therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to come up with the claimed invention from the functionally equivalent teachings of the Puthillathe reference for the detailed teachings and reasons provided above.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Puthillathe et al. (US 2018/0314611 A1) in view of Tsirkin et al. (US 2021/0342463 A1).
The teachings of the recited claimed limitations of the claim 1 discussed above are similarly applied.
Dependent claim 2 further adds the following limitation not expressly disclosed by the Puthillathe reference ---
Claims 2. The server system according to claim 1, further comprising: a circuit board having a development stage board number value, wherein the first control circuit and the second control circuit are disposed on the circuit board, the second control circuit further comprises a second storage unit, the second storage unit is configured to store an authorization value, and the second control circuit is configured to execute a control procedure according to the development stage board number value and the authorization value to control the data to be transmitted from the first input/output circuit to the second input/output circuit. ---
As can be seen from the underlined limitations of the claim 2, the functionally equivalent teachings of the controlling data transmission according to stored values in memory were well-known & practiced in the art of debug processing systems. As evidence, the Tsirkin, in figures 1-2 with accompanying description (paragraphs 45-49) teaches functionally equivalent teachings of controlling data transfer according to stored data such as “Debug Log 262”, “Encrypted File 264”, “Validation Measurement 266”, “Access History 268” and/or “Access Key 270”; as a result, the Tsirkin reference teaches to provide better/secured data transfer control between I/O circuits of the respective communication parties (e.g., figure 1, 110 & 150). Since the Puthillathe references and the Tsirkin references are both directed to the debug processing systems/circuits or the same endeavor, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to add the functionally equivalent teachings of the Tsirkin reference to the functionally equivalent teachings of the Puthillathe reference for a secured controlling of data transfer according to stored data such as “Debug Log 262”, “Encrypted File 264”, “Validation Measurement 266”, “Access History 268” and/or “Access Key 270”, for the reasons and detailed teachings discussed above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B SHIN whose telephone number is (571)272-4159. The examiner can normally be reached 8:00-4:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached at 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER B SHIN/Primary Examiner, Art Unit 2181
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