DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7-9, 15-16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20240053898), in view of Shen (US 20220317924).
Regarding Claim 1, Zhang teaches
wherein the memory controller causes data of the first pseudo channel and the second pseudo channel to be time multiplexed over a memory bus, (Zhang [0007] there is provided a high-bandwidth DDR DIMM, including: a first sub-channel, a second sub-channel, and a combined data buffer, where each of the sub-channels comprises a first pseudo channel and a second pseudo channel [0061] when the register and divided clock driver receives a read command (RD) in big cycle 0, it sends the read command (referred to CMD PC0 for pseudo channel PC0 and CMD PC1 for pseudo channel PC1) to pseudo channels PC0 and PC1 simultaneously… the combined data buffer interleaves the first data (D0) received from pseudo channel PC0 and the first data (D0) received from pseudo channel PC1, and interleaves the second data (D1) received from pseudo channel PC0 and the second data (D1) received from pseudo channel PC1, and so on.)
Zhang does not teach A memory controller, comprising: a command queue stage for storing decoded memory access requests; a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage; and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage; wherein each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.
However, Shen teaches A memory controller, comprising: a command queue stage for storing decoded memory access requests; (Shen [0011] A memory controller includes a command queue and an arbiter.)
a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage; and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage; (Shen [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541. [0054] [0054] Arbiter 238 includes a set of sub-arbiters 605 and a final arbiter 650. Sub-arbiters 605 include a sub-arbiter 610, a sub-arbiter 620)
wherein each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, (Shen [0056] In operation, arbiter 238 selects memory access commands from command queue 220 and refresh control logic 232 by taking into account the current mode (indicating whether a read streak or write streak is in progress), the page status of each entry, the priority of each memory access request, and the dependencies between requests.)
and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition. (Shen [0057] Cross-mode enable and DLAW logic 604 operates to cause and manage streaks of read commands and streaks of write commands over the memory channel. During a current streak of either type of commands, cross-mode enable and DLAW logic 604 monitors an indicator of data bus efficiency of the memory channel.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Regarding Claim 2, Zhang and Shen teach
Zhang does not teach but Shen teaches the first type of accesses comprises one of read accesses and write accesses; and the second type of accesses comprises another one of the read accesses and the write accesses. (Shen [0057] cross-mode enable and DLAW logic 304 stops the current streak, starts a streak of the other type, and changes the current mode in current mode register 602.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Regarding Claim 7, Zhang and Shen teach
Zhang does not teach but Shen teaches a dispatch queue having first and second upstream ports coupled to the first arbiter and the second arbiter, respectively, (Shen FIG. 6 [0054] Arbiter 238 includes a set of sub-arbiters 605 and a final arbiter 650. Sub-arbiters 605 include a sub-arbiter 610, a sub-arbiter 620 [0055] Cross-mode enable logic 604 has an input connected to current mode register 602, and input connected to command queue 220, an input and output connected to final arbiter 650, and an input and output connected to page hit arbiter 610, page conflict arbiter 620, and page miss arbiter 630.)
and a downstream port for conducting first data from the first arbiter that is time-multiplexed with second data from the second arbiter. (Shen [0051] In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541. Rank sub-field 542 stores information about the rank selected on the selected memory channel.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Regarding Claim 8, Zhang teaches
wherein the memory controller causes data of the first pseudo channel and the second pseudo channel to be time multiplexed over a memory bus, (Zhang [0007] there is provided a high-bandwidth DDR DIMM, including: a first sub-channel, a second sub-channel, and a combined data buffer, where each of the sub-channels comprises a first pseudo channel and a second pseudo channel [0061] when the register and divided clock driver receives a read command (RD) in big cycle 0, it sends the read command (referred to CMD PC0 for pseudo channel PC0 and CMD PC1 for pseudo channel PC1) to pseudo channels PC0 and PC1 simultaneously… the combined data buffer interleaves the first data (D0) received from pseudo channel PC0 and the first data (D0) received from pseudo channel PC1, and interleaves the second data (D1) received from pseudo channel PC0 and the second data (D1) received from pseudo channel PC1, and so on.)
Zhang does not teach A data processing system, comprising: a plurality of data processor cores each of which is operable to generate memory access requests ; a memory having a first pseudo channel and a second pseudo channel; and a memory controller operable to receive the memory access requests from the plurality of data processor cores and provide memory commands to the memory, wherein the memory controller includes a first arbiter and a second arbiter each operable to select a first streak of a first type of accesses, and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.
However, Shen teaches A data processing system, comprising: a plurality of data processor cores each of which is operable to generate memory access requests; (Shen [0011] A memory controller includes a command queue and an arbiter. [0012] A data processing system includes a memory accessing agent for providing memory access requests)
a memory having a first pseudo channel and a second pseudo channel; (Shen [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541. [0054] [0054] Arbiter 238 includes a set of sub-arbiters 605 and a final arbiter 650. Sub-arbiters 605 include a sub-arbiter 610, a sub-arbiter 620)
and a memory controller operable to receive the memory access requests from the plurality of data processor cores and provide memory commands to the memory, wherein the memory controller includes a first arbiter and a second arbiter each operable to select a first streak of a first type of accesses, (Shen [0056] In operation, arbiter 238 selects memory access commands from command queue 220 and refresh control logic 232 by taking into account the current mode (indicating whether a read streak or write streak is in progress), the page status of each entry, the priority of each memory access request, and the dependencies between requests.)
and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition. (Shen [0057] Cross-mode enable and DLAW logic 604 operates to cause and manage streaks of read commands and streaks of write commands over the memory channel. During a current streak of either type of commands, cross-mode enable and DLAW logic 604 monitors an indicator of data bus efficiency of the memory channel.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Regarding Claim 9, Zhang and Shen teach
Zhang does not teach but Shen teaches the first type of accesses comprises one of read accesses and write accesses; and the second type of accesses comprises another one of the read accesses and the write accesses. (Shen [0057] cross-mode enable and DLAW logic 304 stops the current streak, starts a streak of the other type, and changes the current mode in current mode register 602.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Regarding Claim 15, Zhang teaches
causing data of the first pseudo channel and the second pseudo channel to be time multiplexed over a memory bus; (Zhang [0007] there is provided a high-bandwidth DDR DIMM, including: a first sub-channel, a second sub-channel, and a combined data buffer, where each of the sub-channels comprises a first pseudo channel and a second pseudo channel [0061] when the register and divided clock driver receives a read command (RD) in big cycle 0, it sends the read command (referred to CMD PC0 for pseudo channel PC0 and CMD PC1 for pseudo channel PC1) to pseudo channels PC0 and PC1 simultaneously… the combined data buffer interleaves the first data (D0) received from pseudo channel PC0 and the first data (D0) received from pseudo channel PC1, and interleaves the second data (D1) received from pseudo channel PC0 and the second data (D1) received from pseudo channel PC1, and so on.)
Zhang does not teach A method for accessing a memory, comprising: storing memory access requests in a command queue stage, wherein each memory access request accesses one of a first pseudo channel and a second pseudo channel of the memory; arbitrating among the memory access requests in an arbitration stage to obtain first arbitration winners for the first pseudo channel using a first arbiter and the second pseudo channel using a second arbiter; selecting a first streak of a first type of accesses by the first arbiter; and changing to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.
However, Shen teaches A method for accessing a memory, comprising: storing memory access requests in a command queue stage, (Shen [0011] A memory controller includes a command queue and an arbiter. [0012] A data processing system includes a memory accessing agent for providing memory access requests)
wherein each memory access request accesses one of a first pseudo channel and a second pseudo channel of the memory; (Shen [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541. [0054] [0054] Arbiter 238 includes a set of sub-arbiters 605 and a final arbiter 650. Sub-arbiters 605 include a sub-arbiter 610, a sub-arbiter 620)
arbitrating among the memory access requests in an arbitration stage to obtain first arbitration winners for the first pseudo channel using a first arbiter and the second pseudo channel using a second arbiter; (Shen [0056] In operation, arbiter 238 selects memory access commands from command queue 220 and refresh control logic 232 by taking into account the current mode (indicating whether a read streak or write streak is in progress), the page status of each entry, the priority of each memory access request, and the dependencies between requests.)
selecting a first streak of a first type of accesses by the first arbiter; and changing to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition. (Shen [0057] Cross-mode enable and DLAW logic 604 operates to cause and manage streaks of read commands and streaks of write commands over the memory channel. During a current streak of either type of commands, cross-mode enable and DLAW logic 604 monitors an indicator of data bus efficiency of the memory channel.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Regarding Claim 16, Zhang and Shen teach
Zhang does not teach but Shen teaches Shen teaches selecting the first streak of the first type of accesses by the first arbiter comprises the first streak of one of read accesses and write accesses; and changing to selecting the second streak of the second type of accesses comprises changing to another one of the read accesses and the write accesses. (Shen [0056] In operation, arbiter 238 selects memory access commands from command queue 220 and refresh control logic 232 by taking into account the current mode (indicating whether a read streak or write streak is in progress) [0057] cross-mode enable and DLAW logic 304 stops the current streak, starts a streak of the other type, and changes the current mode in current mode register 602.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Regarding Claim 20, Zhang and Shen teach
Zhang does not teach but Shen teaches receiving memory access requests; decoding an address of the memory access requests to form decoded memory access requests, the decoding comprising scrambling the memory accesses between the first pseudo channel and the second pseudo channel based on one or more address bits of a normalized address; (Shen [0029] The memory access requests include access addresses in the physical address space represented in a normalized format. Address generator 222 converts the normalized addresses into a format that can be used to address the actual memory devices in memory system 130 This format includes a region identifier that associates the memory access request with a particular rank, a row address, a column address, a bank address, and a bank group. [0051] Decoded address field 540 stores information identifying the location in memory system 130 of the corresponding memory access. It includes any mapping or transformation (such as scrambling or swizzling of memory addresses) performed on the physical address received by address generator 222)
and providing the decoded memory access requests to the command queue stage according to a pseudo-channel number. (Shen [0036] address generator 222 decodes the address information into predecoded information including rank, row address, column address, bank address, and bank group in the memory system, and command queue 220 stores the predecoded information.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Claim(s) 3-6, 10-14, 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20240053898), in view of Shen (US 20220317924), further in view of Balakrishnan (US 20180018133).
Regarding Claim 3, Zhang and Shen teach
Zhang does not teach but Shen teaches for both the first pseudo channel and the second pseudo channel in the command queue stage (Shen [0050] Priority sub-field 532 indicates the priority for the opposite type entry or entries in command queue 220. [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Zhang-Shen does not teach the cross mode condition is based on a total number of the second type of accesses
However, Balakrishnan teaches the cross mode condition is based on a total number of the second type of accesses (Balakrishnan [0044] arbiter 538 uses a set of threshold counters that take into account command type (e.g. reads or writes) as well as priority level (low, medium, and high). a total write threshold to force arbiter 538 to firmly interrupt reads to service writes;)
Zhang, Shen and Balakrishnan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang, Shen and Balakrishnan to modify the Zhang-Shen‘s memory system with Balakrishnan’s teaching of cross mode condition. The motivation for doing so would be (Balakrishnan [0035]) to select memory accesses efficiently.
Regarding Claim 4, Zhang, Shen and Balakrishnan teach
Zhang-Shen teaches for both the first pseudo channel and the second pseudo channel in the command queue stage (Shen [0050] Priority sub-field 532 indicates the priority for the opposite type entry or entries in command queue 220. [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541.)
Zhang-Shen does not teach but Balakrishnan teaches the cross mode condition is further based on a history of the first type of accesses selected (Balakrishnan [0045] Arbiter 538 counts the number of reads/writes present in command queue 520 at any given time to determine if any of the thresholds are met.)
Zhang, Shen and Balakrishnan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang, Shen and Balakrishnan to modify the Zhang-Shen‘s memory system with Balakrishnan’s teaching of cross mode condition. The motivation for doing so would be (Balakrishnan [0035]) to select memory accesses efficiently.
Regarding Claim 5, Zhang and Shen teach
Zhang does not teach but Shen teaches for a respective pseudo channel in the command queue stage and another one of the first arbiter and the second arbiter indicating that it is ready to switch to selecting the second streak of the second type of accesses. (Shen [0050] Priority sub-field 532 indicates the priority for the opposite type entry or entries in command queue 220. [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Zhang-Shen does not teach the cross mode condition is based on a total number of the second type of accesses
However, Balakrishnan teaches the cross mode condition is based on a total number of the second type of accesses (Balakrishnan [0044] arbiter 538 uses a set of threshold counters that take into account command type (e.g. reads or writes) as well as priority level (low, medium, and high). a total write threshold to force arbiter 538 to firmly interrupt reads to service writes;)
Zhang, Shen and Balakrishnan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang, Shen and Balakrishnan to modify the Zhang-Shen‘s memory system with Balakrishnan’s teaching of cross mode condition. The motivation for doing so would be (Balakrishnan [0035]) to select memory accesses efficiently.
Regarding Claim 6, Zhang, Shen and Balakrishnan teach
Zhang does not teach but Shen teaches an address decoder having an upstream port for receiving memory access requests, (Shen [0012] The memory controller includes a command queue and an arbiter. The command queue is for receiving and storing decoded memory commands [0033] Arbiter 238 is bidirectionally connected to command queue 220 and is the heart of memory channel controller 210.)
and a downstream port coupled to the command queue stage for providing the decoded memory access requests according to a pseudo-channel number, (Shen [0036] address generator 222 decodes the address information into predecoded information including rank, row address, column address, bank address, and bank group in the memory system, and command queue 220 stores the predecoded information.)
wherein the address decoder further scrambles memory accesses between the first pseudo channel and the second pseudo channel based on one or more address bits of a normalized address. (Shen [0051] Decoded address field 540 stores information identifying the location in memory system 130 of the corresponding memory access. It includes any mapping or transformation (such as scrambling or swizzling of memory addresses) performed on the physical address received by address generator 222)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Regarding Claim 10, Zhang and Shen teach
Zhang does not teach but Shen teaches for both the first pseudo channel and the second pseudo channel in the command queue stage (Shen [0050] Priority sub-field 532 indicates the priority for the opposite type entry or entries in command queue 220. [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Zhang-Shen does not teach the cross mode condition is based on a total number of the second type of accesses
However, Balakrishnan teaches the cross mode condition is based on a total number of the second type of accesses (Balakrishnan [0044] arbiter 538 uses a set of threshold counters that take into account command type (e.g. reads or writes) as well as priority level (low, medium, and high). a total write threshold to force arbiter 538 to firmly interrupt reads to service writes;)
Zhang, Shen and Balakrishnan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang, Shen and Balakrishnan to modify the Zhang-Shen‘s memory system with Balakrishnan’s teaching of cross mode condition. The motivation for doing so would be (Balakrishnan [0035]) to select memory accesses efficiently.
Regarding Claim 11, Zhang, Shen and Balakrishnan teach
Zhang-Shen teaches for both the first pseudo channel and the second pseudo channel in the command queue stage (Shen [0050] Priority sub-field 532 indicates the priority for the opposite type entry or entries in command queue 220. [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541.)
Zhang-Shen does not teach but Balakrishnan teaches the cross mode condition is further based on a history of the first type of accesses selected (Balakrishnan [0045] Arbiter 538 counts the number of reads/writes present in command queue 520 at any given time to determine if any of the thresholds are met.)
Zhang, Shen and Balakrishnan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang, Shen and Balakrishnan to modify the Zhang-Shen‘s memory system with Balakrishnan’s teaching of cross mode condition. The motivation for doing so would be (Balakrishnan [0035]) to select memory accesses efficiently.
Regarding Claim 12, Zhang and Shen teach
Zhang does not teach but Shen teaches for a respective pseudo channel in the command queue stage and another one of the first arbiter and the second arbiter indicating that it is ready to switch to selecting the second streak of the second type of accesses. (Shen [0050] Priority sub-field 532 indicates the priority for the opposite type entry or entries in command queue 220. [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Zhang-Shen does not teach the cross mode condition is based on a total number of the second type of accesses
However, Balakrishnan teaches the cross mode condition is based on a total number of the second type of accesses (Balakrishnan [0044] arbiter 538 uses a set of threshold counters that take into account command type (e.g. reads or writes) as well as priority level (low, medium, and high). a total write threshold to force arbiter 538 to firmly interrupt reads to service writes;)
Zhang, Shen and Balakrishnan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang, Shen and Balakrishnan to modify the Zhang-Shen‘s memory system with Balakrishnan’s teaching of cross mode condition. The motivation for doing so would be (Balakrishnan [0035]) to select memory accesses efficiently.
Regarding Claim 13, Zhang, Shen and Balakrishnan teach
Zhang does not teach but Shen teaches an address decoder having an upstream port for receiving memory access requests, (Shen [0012] The memory controller includes a command queue and an arbiter. The command queue is for receiving and storing decoded memory commands [0033] Arbiter 238 is bidirectionally connected to command queue 220 and is the heart of memory channel controller 210.)
and a downstream port coupled to the command queue stage for providing the decoded memory access requests according to a pseudo-channel number, (Shen [0036] address generator 222 decodes the address information into predecoded information including rank, row address, column address, bank address, and bank group in the memory system, and command queue 220 stores the predecoded information.)
wherein the address decoder further scrambles memory accesses between the first pseudo channel and the second pseudo channel based on one or more address bits of a normalized address. (Shen [0051] Decoded address field 540 stores information identifying the location in memory system 130 of the corresponding memory access. It includes any mapping or transformation (such as scrambling or swizzling of memory addresses) performed on the physical address received by address generator 222)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Regarding Claim 14, Zhang, Shen and Balakrishnan teach
Zhang does not teach but Shen teaches a dispatch queue having first and second upstream ports coupled to the first arbiter and the second arbiter, respectively, (Shen FIG. 6 [0054] Arbiter 238 includes a set of sub-arbiters 605 and a final arbiter 650. Sub-arbiters 605 include a sub-arbiter 610, a sub-arbiter 620 [0055] Cross-mode enable logic 604 has an input connected to current mode register 602, and input connected to command queue 220, an input and output connected to final arbiter 650, and an input and output connected to page hit arbiter 610, page conflict arbiter 620, and page miss arbiter 630.)
and a downstream port for conducting first data from the first arbiter that is time-multiplexed with second data from the second arbiter; (Shen [0051] In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541. Rank sub-field 542 stores information about the rank selected on the selected memory channel.)
and a physical interface circuit coupled to an output of the dispatch queue and to the memory, wherein the memory comprises a multiplexed-rank dual inline memory module (MRDIMM). (Shen [0024] Memory system 130 includes a memory channel 131 and a memory channel 133. Memory channel 131 includes a set of dual inline memory modules (DIMMs) connected to a DDRx bus 132, including representative DIMMs 134, 136, and 138 that in this example correspond to separate ranks. Likewise, memory channel 133 includes a set of DIMMs connected to a DDRx bus 129, including representative DIMMs 135, 137, and 139.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Regarding Claim 17, Zhang and Shen teach
Zhang does not teach but Shen teaches for both the first pseudo channel and the second pseudo channel in the command queue stage (Shen [0050] Priority sub-field 532 indicates the priority for the opposite type entry or entries in command queue 220. [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Zhang-Shen does not teach the cross mode condition is based on a total number of the second type of accesses
However, Balakrishnan teaches the cross mode condition is based on a total number of the second type of accesses (Balakrishnan [0044] arbiter 538 uses a set of threshold counters that take into account command type (e.g. reads or writes) as well as priority level (low, medium, and high). a total write threshold to force arbiter 538 to firmly interrupt reads to service writes;)
Zhang, Shen and Balakrishnan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang, Shen and Balakrishnan to modify the Zhang-Shen‘s memory system with Balakrishnan’s teaching of cross mode condition. The motivation for doing so would be (Balakrishnan [0035]) to select memory accesses efficiently.
Regarding Claim 18, Zhang, Shen and Balakrishnan teach
Zhang-Shen teaches for both the first pseudo channel and the second pseudo channel in the command queue stage (Shen [0050] Priority sub-field 532 indicates the priority for the opposite type entry or entries in command queue 220. [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541.)
Zhang-Shen does not teach but Balakrishnan teaches the cross mode condition is further based on a history of the first type of accesses selected (Balakrishnan [0045] Arbiter 538 counts the number of reads/writes present in command queue 520 at any given time to determine if any of the thresholds are met.)
Zhang, Shen and Balakrishnan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang, Shen and Balakrishnan to modify the Zhang-Shen‘s memory system with Balakrishnan’s teaching of cross mode condition. The motivation for doing so would be (Balakrishnan [0035]) to select memory accesses efficiently.
Regarding Claim 19, Zhang and Shen teach
Zhang does not teach but Shen teaches for a respective pseudo channel in the command queue stage and another one of the first arbiter and the second arbiter indicating that it is ready to switch to selecting the second streak of the second type of accesses. (Shen [0050] Priority sub-field 532 indicates the priority for the opposite type entry or entries in command queue 220. [0051] Sub-channel sub-field 541 indicates a sub-channel for memory controllers that support a mode known as virtual controller mode. In virtual controller mode, a single memory controller can efficiently support separate memory channels using the same memory controller hardware, and demultiplexing the decoded memory accesses onto two physical channels known as “sub-channels” using the sub-channel value stored in sub-channel sub-field 541.)
Zhang and Shen are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang and Shen to modify Zhang’s memory system with pseudo channels with Shen‘s teaching of arbitration and cross-mode enable logic. The motivation for doing so would be (Shen [0033]) arbiter improves efficiency by intelligent scheduling of accesses to improve the usage of the memory bus.
Zhang-Shen does not teach the cross mode condition is based on a total number of the second type of accesses
However, Balakrishnan teaches the cross mode condition is based on a total number of the second type of accesses (Balakrishnan [0044] arbiter 538 uses a set of threshold counters that take into account command type (e.g. reads or writes) as well as priority level (low, medium, and high). a total write threshold to force arbiter 538 to firmly interrupt reads to service writes;)
Zhang, Shen and Balakrishnan are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Zhang, Shen and Balakrishnan to modify the Zhang-Shen‘s memory system with Balakrishnan’s teaching of cross mode condition. The motivation for doing so would be (Balakrishnan [0035]) to select memory accesses efficiently.
Response to Arguments
Applicant's arguments filed 11/20/2025 have been fully considered.
The amended limitations are addressed in new rejection based on the amendment.
Applicant argued that Shen teaches sub-channels that are different than pseudo channels. Zhang teaches sub-channel comprises pseudo channels.
The combination of Zhang and Shen discloses the limitations of claim 1. Please see office action for details.
Next, for claim 8, 15, Applicant argues as similar to claim 1.
Applicant’s argument for dependent claims 2-7, 9-14 and 16-20 are based on their respective base independent claim 1, 8 and 15, which are addressed above.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Nale (US 20220229790) teaches data buffers for the pseudo channels time multiplex the data from pseudo channels onto the host data bus.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WEI MA/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135