DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (KR 20230105034A and Yang hereinafter) in view of Drogi et al. (US 2024/0080005) further in view of Imai et al. (US 2023/0261622 and Imai hereinafter).
Regarding claim 1, Yang discloses circuitry [200, fig. 2], comprising: driver amplification circuitry [a drive amplifier 210]; phase offset circuitry [phase offset compensator 220]; balun circuitry [balun in 210]; carrier amplifier circuitry [carrier amplifier 231]; and peaking amplifier circuitry [peaking amplifier 232], wherein the phase offset circuitry comprises: a first line [221] connected to the driver amplification circuitry and configured to provide a first single-ended signal [output 221] and a second line [222] connected to the driver amplification circuitry and configured to provide a second single-ended signal [output 222]. Yang does not explicitly disclose a first phase delay and a second phase delay different from the first phase delay of the first single-ended signal of the first line and first balun circuitry connected between the first line and the carrier amplifier circuitry; and second balun circuitry connected between the second line and the peaking amplifier circuitry.
However, Drogi discloses Doherty power amplifier [220, fig. 6] wherein a first phase delay [90-degree phase delay/ 225] and a second phase delay [180-degree phase delay /226] different from the first phase delay of the first single-ended signal of the first line. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang by incorporating phase delay to the carrier and peaking line as taught in Drogi to provide phase offsets necessary to achieve desired performance. Yang in view of Drogi does not explicitly disclose first balun circuitry connected between the first line and the carrier amplifier circuitry; and second balun circuitry connected between the second line and the peaking amplifier circuitry.
However, Imai discloses first balun circuitry [41, fig. 1] connected between the first line [ARF1] and the carrier amplifier circuitry [51Cp/51Cm]; and second balun circuitry [46] connected between the second line [ARF2] and the peaking amplifier circuitry [51P0/51Pm]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang/ Drogi by incorporating the balun circuit connected between the first line/second line and the carrier /peaking amplifier circuitry as taught in Imai to provide improved power amplifier circuit.
Regarding claim 2, Yang in view of Drogi further in view of Imai discloses wherein the first line of the phase offset circuitry is configured to provide the first single-ended signal corresponding to a first output signal of the driver amplification circuitry [output to 221], wherein the second line of the phase offset circuitry is configured to provide the second single-ended signal corresponding to a second output signal of the driver amplification circuitry [output to 222], and wherein a phase difference [see fig.6 of ref. Drogi] between the first single-ended signal and the second single-ended signal corresponds to 90-degrees.
Regarding claim 10, Yang in view of Drogi further in view of Imai discloses [fig. 2] wherein the first line is connected to a first output of the driver amplification circuitry [output of 210 to 221] in differential mode, and wherein the second line is connected to a second output of the driver amplification circuitry [output of 210 to 221] in differential mode.
Claims 3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Drogi et al. and Imai et al. further in view of Oakley et al. (US 2010/0148877 and Oakley hereinafter).
Regarding claim 3, Yang in view of Drogi further in view of Imai discloses all the features with respect to claim 1 as indicated above. Yang in view of Drogi further in view of Imai further discloses wherein the first balun circuitry comprises a first transformer [42, fig. 1] having a first input port for obtaining the first single-ended signal, a first ground port [port ARF1], and a first carrier input port [port ARF3] and a second carrier input port [port ARF4] connected to the carrier amplifier circuitry, and wherein the second balun circuitry comprises a second transformer [47, fig. 1] having a second input port [port ARF2] for obtaining the second single-ended signal, a second ground port [port ARF5], and a first peaking input port [port ARF6] and a second peaking input port connected to the peaking amplifier circuitry. Yang in view of Drogi further in view of Imai does not explicitly discloses wherein the first balun circuitry comprises first transformer having a first ground port and the second balun comprises a second transformer having a second ground port.
However, Oakley discloses first balun circuitry [605, fig. 6] comprises first transformer [transformer in 605] having a first ground port [ground port in 605] and second balun [604] comprises a second transformer [transformer in 605] having a second ground port [ground port in 604]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang/ Drogi/Imai by incorporating the balun circuit with a ground port as taught in Oakley in order to utilize known transformer.
Regarding claim 9, Yang in view of Drogi further in view of Imai discloses all the features with respect to claim 1 as indicated above. Yang in view of Drogi further in view of Imai does not explicitly disclose wherein the second line, in a capacitor-inductor-capacitor (C-L-C) structure, comprises a first capacitor disposed in parallel, a second capacitor disposed in parallel, and an inductor disposed in series between the first capacitor and the second capacitor.
However, Oakley discloses wherein a line [see fig. 5 and 611, fig. 6], in a capacitor-inductor-capacitor (C-L-C) structure, comprises a first capacitor disposed in parallel, a second capacitor disposed in parallel, and an inductor disposed in series between the first capacitor and the second capacitor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang/ Drogi/Imai by incorporating capacitor-inductor-capacitor (C-L-C) structure as taught in Oakley in order to provides the appropriate positive or negative quarter wave phase shifting and delay [par, 0039].
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Drogi et al. and Imai et al. and Oakley et al. further in view of Peng et al. (CN 115882791A and Peng hereinafter).
Regarding claim 4, Yang in view of Drogi further and Imai further in view of Oakley discloses all the features with respect to claim 3 as indicated above. Yang in view of Drogi further and Imai further in view of Oakley does not explicitly disclose wherein the first ground port and the second ground port are shorted at one node, and wherein each of the first ground port and the second ground port is electrically connected to the ground through a capacitor connected to the one node.
However, Peng discloses transformer [3] a first ground port [gnd] and second ground port are shorted at one node [gnd node], and wherein each of the first ground port and the second ground port is electrically connected to the ground through a capacitor [C11] connected to the one node. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang/ Drogi/Imai/Oakley by incorporating the transformer as taught in Peng in order to utilize known transformer.
Regarding claim 5, Yang in view of Drogi and Imai and Oakley further in view of Peng discloses [see fig. 6] wherein the carrier amplifier circuitry comprises a plurality of first field effect transistors (FETs) [top two transistors of 601] connected to the first carrier input port and a plurality of second FETs [lower two transistors of 601] connected to the second carrier input port, and wherein the peaking amplifier circuitry comprises a plurality of third FETs [top two transistors of 602] connected to the first peaking input port and a plurality of fourth FETs [lower two transistors of 602] connected to the second peaking input port.
Regarding claim 6, Yang in view of Drogi and Imai and Oakley further in view of Peng discloses wherein the driver amplification circuitry [fig. 2] comprises; balun circuitry for a radio frequency (RF) input signal [input 201, fig. 2 of Yang], and a driver amplifier [210] comprising a first field effect transistor (FET) [top transistor in 210] connected to a first output of the balun circuitry and a second FET connected [lower transistor in 210] to a second output of the balun circuitry,
Regarding claim 7, Yang in view of Drogi and Imai and Oakley further in view of Peng discloses [see fig. 2] wherein a drain voltage for the drain of the first FET is provided through the one node and the ground port of the first balun circuitry, and wherein a drain voltage for the drain of the second FET is provided through the one node and the ground port of the second balun circuitry.
Regarding claim 8, Yang in view of Drogi and Imai and Oakley further in view of Peng discloses [see fig. 2 and pages 4-5] wherein the first balun circuitry is configured to match a first input impedance of the carrier amplifier circuitry to an impedance having a specified magnitude, wherein the second balun circuitry is configured to match a second input impedance of the peaking amplifier circuitry to the impedance having the specified magnitude, and wherein the specified magnitude corresponds to a half of magnitude of an impedance from the driver amplification circuitry to the offset circuitry.
Claims 11-12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Imai et al. further in view of Jann et al. (US 2023/0283311 and Jann hereinafter).
Regarding claim 11, Yang discloses an electronic [fig. 2] component, comprising: a plurality of radio frequency (RF) paths comprising RF circuitry [path 222/231 and 221/232], wherein each of the plurality of RF paths comprises a power amplifier [230], wherein the power amplifier comprises driver amplification circuitry [210], phase offset circuitry [220], balun circuitry [balun in 210], carrier amplifier circuitry [231], and peaking amplifier circuitry [232], wherein the phase offset circuitry comprises a first line [221] and a second line [222] and the balun circuitry [balun in 210]. Yang does not explicitly disclose a power divider comprising circuitry; and wherein each of the plurality of RF paths comprises a phase shifter and wherein the balun circuitry comprises a first transformer for the carrier amplifier circuitry and a second transformer for the peaking amplifier circuitry, wherein the first line is configured to provide a first single-ended signal to the first transformer, and wherein the second line is configured to provide a second single-ended signal to the second transformer.
However, Imai discloses balun circuitry [41/46], wherein the balun circuitry comprises a first transformer [42] for the carrier amplifier circuitry and a second transformer [47] for the peaking amplifier circuitry, wherein first line [101a] is configured to provide a first single-ended signal [RF1] to the first transformer, and wherein second line [101b] is configured to provide a second single-ended signal [RF2] to the second transformer. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang by incorporating the balun circuit that connect the driver amplification circuitry and the first line/second line as taught in Imai to provide improved power amplifier circuit. Yang in view of Imai does not explicitly disclose a power divider comprising circuitry; and wherein each of the plurality of RF paths comprises a phase shifter.
However, Jann discloses a power divider [374, fig. 3C] comprising circuitry; and wherein each of the plurality of RF paths [fig. 10] comprises a phase shifter [1006-1~10064, fig. 10] and a power amplifier [1004-1~1004-4]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang/Imai as taught in Jann to utilize known RF path and phase shifter of power amplifier circuit.
Regarding claim 12, Yang discloses in view of Imai further in view of Jann discloses wherein the first line [221] of the phase offset circuitry [220, fig. 2] is configured to provide the first single-ended signal corresponding to a first output signal of the driver amplification circuitry [output to 221], wherein the second line [222] of the phase offset circuitry is configured to provide the second single-ended signal corresponding to a second output signal of the driver amplification circuitry [output to 222], and wherein a phase difference [see fig.6 of ref. Drogi] between the first single-ended signal and the second single-ended signal corresponds to 90-degrees.
Regarding claim 19, Yang discloses in view of Imai further in view of Jann discloses wherein the first line is connected to a first output of the driver amplification circuitry [output of 210 to 221] in differential mode, and wherein the second line is connected to a second output of the driver amplification circuitry [output of 210 to 221] in differential mode.
Claims 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Imai et al. and Jann further in view of Oakley et al.
Regarding claim 13, Yang in view of Imai further in view of Jann discloses all the features with respect to claim 12 as indicated above. Yang in view of Imai further in view of Jann further discloses wherein the first balun circuitry comprises a first transformer [42, fig. 1] having a first input port for obtaining the first single-ended signal, a first ground port [port ARF1], and a first carrier input port [port ARF3] and a second carrier input port [port ARF4] connected to the carrier amplifier circuitry, and wherein the second balun circuitry comprises a second transformer [47, fig. 1] having a second input port [port ARF2] for obtaining the second single-ended signal, a second ground port [port ARF5], and a first peaking input port [port ARF6] and a second peaking input port connected to the peaking amplifier circuitry. Yang in view of Imai further in view of Jann does not explicitly discloses wherein the first balun circuitry comprises first transformer having a first ground port and the second balun comprises a second transformer having a second ground port.
However, Oakley discloses first balun circuitry [605, fig. 6] comprises first transformer [transformer in 605] having a first ground port [ground port in 605] and second balun [604] comprises a second transformer [transformer in 605] having a second ground port [ground port in 604]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang/ Imai/Jann by incorporating the balun circuit with a ground port as taught in Oakley in order to utilize known transformer.
Regarding claim 18, Yang in view of Imai further in view of Jann discloses all the features with respect to claim 1 as indicated above. Yang in view of Imai further in view of Jann does not explicitly disclose wherein the second line, in a capacitor-inductor-capacitor (C-L-C) structure, comprises a first capacitor disposed in parallel, a second capacitor disposed in parallel, and an inductor disposed in series between the first capacitor and the second capacitor.
However, Oakley discloses wherein a line [see fig. 5 and 611, fig. 6], in a capacitor-inductor-capacitor (C-L-C) structure, comprises a first capacitor disposed in parallel, a second capacitor disposed in parallel, and an inductor disposed in series between the first capacitor and the second capacitor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang/Imai/Jann by incorporating capacitor-inductor-capacitor (C-L-C) structure as taught in Oakley in order to provides the appropriate positive or negative quarter wave phase shifting and delay [par, 0039].
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. in view of Imai et al. and Jann and Oakley further in view of Peng et al.
Regarding claim 14, Yang in view of Imai and Jann further in view of Oakley discloses all the features with respect to claim 13 as indicated above. Yang in view of Imai and Jann further in view of Oakley does not explicitly disclose wherein the first ground port and the second ground port are shorted at one node, and wherein each of the first ground port and the second ground port is electrically connected to the ground through a capacitor connected to the one node.
However, Peng discloses transformer [3] a first ground port [gnd] and second ground port are shorted at one node [gnd node], and wherein each of the first ground port and the second ground port is electrically connected to the ground through a capacitor [C11] connected to the one node. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang/Imai/Jann/Oakley by incorporating the transformer as taught in Peng in order to utilize known transformer.
Regarding claim 15, Yang in view of Imai and Jann and Oakley further in view of Peng discloses [see fig. 6] wherein the carrier amplifier circuitry comprises a plurality of first field effect transistors (FETs) [top two transistors of 601] connected to the first carrier input port and a plurality of second FETs [lower two transistors of 601] connected to the second carrier input port, and wherein the peaking amplifier circuitry comprises a plurality of third FETs [top two transistors of 602] connected to the first peaking input port and a plurality of fourth FETs [lower two transistors of 602] connected to the second peaking input port.
Regarding claim 16, Yang in view of Imai and Jann and Oakley further in view of Peng discloses wherein the driver amplification circuitry [fig. 2] comprises: a transformer [transformer in 210] for a radio frequency (RF) input signal [input to 201, fig. 2 of Yang], and a driver amplifier [in 210] comprising a first field effect transistor (FET) [top transistor in 210] connected to the first output of the transformer and a second FET connected to a second output of the transformer [lower transistor in 210].
Regarding claim 17, Yang in view of Imai and Jann and Oakley further in view of Peng discloses, [see fig. 2] wherein a drain voltage for the drain of the first FET is provided through the one node and the ground port of the first transformer, and wherein a drain voltage for the drain of the second FET is provided through the one node and the ground port of the second transformer.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jann et al. (US 2023/0283311 and Jann hereinafter) in view of Yang et al. further in view of Imai et al.
Regarding claim 20, Jann discloses electronic device [see figs. 1, 3A-3D, 10 and 12], comprising: a plurality of antennas [1002-1~1002-4, fig. 10]; radio frequency integrated circuitry (RFIC) [100, fig. 1] for the plurality of antennas; and at least one processor [105, fig. 1], comprising processing circuitry, wherein the RFIC comprises a power divider [374, fig. 3] comprising circuitry and a plurality of RF paths [fig. 10], wherein each of the plurality of RF paths comprises a phase shifter [1006-1~1006-4, fig. 10] and a power amplifier [1004-1~1004-4, fig. 10]. Jann does not explicitly disclose wherein the power amplifier comprises driver amplification circuitry, phase offset circuitry, balun circuitry, carrier amplifier circuitry, and peaking amplifier circuitry, wherein the phase offset circuitry comprises lines connecting the driver amplification circuitry and the balun circuitry, wherein the balun circuitry comprises a first transformer for the carrier amplifier circuitry and a second transformer for the peaking amplifier circuitry, wherein a first line of the lines is configured to provide a first single-ended signal to the first transformer, and wherein a second line of the lines is configured to provide a second single-ended signal to the second transformer.
However, Yang discloses wherein a power amplifier [200, fig. 2] comprises driver amplification circuitry [210], phase offset circuitry [220], balun circuitry [balun in 210], carrier amplifier circuitry [231], and peaking amplifier circuitry [231], wherein the phase offset circuitry comprises lines [221/222] connecting the driver amplification circuitry. Jann in view of Yang does not explicitly disclose a first transformer for the carrier amplifier circuitry and a second transformer for the peaking amplifier circuitry, wherein a first line of the lines is configured to provide a first single-ended signal to the first transformer, and wherein a second line of the lines is configured to provide a second single-ended signal to the second transformer.
However, Imai discloses balun circuitry [41/46], wherein the balun circuitry comprises a first transformer [42] for the carrier amplifier circuitry and a second transformer [47] for the peaking amplifier circuitry, wherein first line [101a] is configured to provide a first single-ended signal [RF1] to the first transformer, and wherein second line [101b] is configured to provide a second single-ended signal [RF2] to the second transformer. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the apparatus of Yang by incorporating the balun circuit that connect the driver amplification circuitry and the first line/second line as taught in Imai to provide improved power amplifier circuit.
Conclusion
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2836
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