Prosecution Insights
Last updated: August 17, 2026
Application No. 18/891,579

MEMORY SYSTEM, OPERATING METHOD OF MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY CONTROLLER

Final Rejection §103
Filed
Sep 20, 2024
Priority
Sep 21, 2023 — RE 10-2023-0126408 +2 more
Examiner
LI, ZHUO H
Art Unit
2133
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
8m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
522 granted / 586 resolved
+34.1% vs TC avg
Minimal +4% lift
Without
With
+3.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
15 currently pending
Career history
607
Total Applications
across all art units

Statute-Specific Performance

§101
6.2%
-33.8% vs TC avg
§103
52.6%
+12.6% vs TC avg
§102
15.5%
-24.5% vs TC avg
§112
10.0%
-30.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 586 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment This Office action is in response to amendment filed 4/9/2026. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 8-12 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US Pub. 2020/0026465 A1, hereinafter June) in view of Kim et al. (US 2021/0096985 A1, hereinafter Kim). Regarding claim 1, Jung discloses a memory system (figure 1, 10), comprising: a memory device (figure 1, 120); and a memory controller (figure 1, 110) connected to the memory device, wherein the memory controller is configured to: analyze a pattern of the suspend schedule command a plurality of times to obtain a plurality of analysis results ([0068], write control component 20 may also analyze the workload by considering a time interval between the read commands and the size of read data, or other factor indicating the processing of read commands relative to other in order to analyze the tendency of the host commands); select an operating mode from among a plurality of operating modes based on the plurality of analysis results, the plurality of operating modes comprising a latency mode and a throughput mode ([0069]-[0070], write control component 20 may select the first write mode, read as latency mode, or deprived write command execution, read as throughput mode); determine a suspend schedule based on the operating mode ([0071]-[0072], it is determined whether the write commands are being held for a relatively long period of time or both write and read commands are provided and the workload is not deprived of write command execution); and perform a memory operation on the memory device based on the suspend schedule, the memory operation comprising at least one of a read operation or a write operation ([0071]-[0072], the write control component 20 may select the first write mode to execute the held write commands when it is determined that a mix of write and read commands are provided and the workload is deprived of write command execution, and the write control component 20 may select the second write mode, e.g., the normal program mode, when both write and read commands are provided and the workload is not deprived of write command execution). Jung differs from the claimed invention in not specifically teaching that the memory controller is further configured to adjust at least one of a suspended latency or a write resume time point latency based on the suspend schedule. However, Kim teaches a memory controller (figure 1, 100) having a suspend-limit changer (figure 3, 40) calculates a write consistency-level and a read consistency-level based on the write/read latency data structure, for use in evaluating variations of the latencies ([0052]) such that the suspend-limit changer configured to dynamically change an erase/program suspend-limit, i.e., suspend latency, based on the calculated write/read latencies, i.e., suspend schedule ([0058] and [0067]) in order to improve quality of service ([0005]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jung in having that the memory controller is further configured to adjust at least one of a suspended latency or a write resume time point latency based on the suspend schedule, as per teaching of Kim, in order to improve quality of service. Regarding claim 2, Jung discloses that the memory controller is further configured to identify a suspend pattern included in the suspend schedule command ([0058] and [0063], the workload analyzer 203 may determine the tendency of the commands provided from the host device by referring to the parsing result of the command analyzer and may determine that the corresponding workload is deprived of write command execution). Regarding claim 3, Jung teaches that the memory controller is further configured to change the suspend schedule in real time ([0060], write mode decision component 205 may select either the cache program mode or the normal program mode as the write mode based on the analysis result of the workload analyzer 203). Regarding claims 4 and 5, Jung teaches that the memory controller is further configured to determine, based on the changing of the suspend schedule, the suspend latency based on a preset reference or the write resume time point latency based on a preset reference ([0061]-[0063], the write mode decision component 205 may select the cache program mode when the analysis result of the host commands indicates that they mostly include write commands, and when analysis of the host commands indicates that a mix of write and read commands are being provided, the write mode decision component 205 may select the normal program mode). Regarding claim 8, the claimed limitations are rejected as the same reasons as set forth in claim 1. Regarding claim 9, the claimed limitations are rejected as the same reasons as set forth in claim 2. Regarding claim 10, the claimed limitations are rejected as the same reasons as set forth in claim 3. Regarding claims 11-12, the claimed limitations are rejected as the same reasons as set forth in claims 4-5. Regarding claim 15, the claimed limitations are rejected as the same reasons as set forth in claim 1. Regarding claim 16, the claimed limitations are rejected as the same reasons as set forth in claim 2. Regarding claim 17, the claimed limitations are rejected as the same reasons as set forth in claim 3. Regarding claim 18, the claimed limitations are rejected as the same reasons as set forth in claims 4-5. 8. Claims 6-7, 13-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US Pub. 2020/0026465 A1) in view of Kim et al. (US 2021/0096985 A1, hereinafter Kim), as applied in claims above, and further in view of Karr (US Pub. 2023/0393742 A1, herein after Karr). Regarding claims 6-7, the combination of Jung and Kim differs from the claimed invention in not specifically disclosing that the memory controller is further configured to: based on a determination that a number of read operations is greater than a number of write operations based on the analysis of the pattern of the suspend schedule command: determine the suspend schedule based on the throughput mode; and determine the suspend schedule by grouping the read operations, and wherein the memory controller is further configured to: based on a determination that a number of read operations is less than a number of write operations based on the analysis of the pattern of the suspend schedule command: determine the suspend schedule based on the latency mode; and determine the suspend schedule, and maintain a pattern of the read operations. However, Karr teaches a scheduler may suspend the write operation to enable the storage device to perform one or more read operations to read data from the storage device ([0310]-[0311]) such that a processing logic completes the flash programming operation if the processing logic determines that the flash programming operation does not delay the read request by the threshold amount of time, i.e., determining the suspend schedule based on the throughput mode based on determining that a number of read operations is greater than a number of write operations based on the pattern of the suspend schedule command, and the processing logic determines if the flash programming operation can be interrupted upon determining that the flash programming operation delays the read request by the threshold amount of time, i.e., determining the suspend schedule based on the latency mode based on determining that a number of read operations is less than a number of write operations based on the pattern of the suspend schedule command,([0349]-[0351]) in order to reduce the latency and improve the performance of the storage system. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jung and Kim in having that the determining of the suspend schedule further comprises determining the suspend schedule based on the throughput mode, based on determining that a number of read operations is greater than a number of write operations based on the pattern of the suspend schedule command, wherein the suspend schedule is further determined by grouping the read operations, and determining the suspend schedule based on the latency mode based on determining that a number of read operations is less than a number of write operations based on the pattern of the suspend schedule command, and wherein the suspend schedule is determined to maintain a pattern of the read operations, as per teaching of Karr, in order to reduce the latency and improve the performance of the storage system. Regarding claims 13-14, the claimed limitations are rejected as the same reasons as set forth in claims 6-7. Regarding claims 19-20, the claimed limitations are rejected as the same reasons as set forth in claims 6-7. Response to Arguments Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al. (US 2019/0171360 A1) discloses a program control method of a memory controller for controlling a memory device to include transmitting a suspend command to the memory device, responsive to the receiving the request for the data operation with the higher priority, receiving, from the memory device, a signal indicating that the program operation has been suspended, responsive to the transmitting the suspend command (abstract and [0007]). Cariello (US 12,645,391 B2) discloses that a memory system may receive, from a host system, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based on limiting a suspension of write operations (abstract). Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at (571)-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZHUO H LI/Primary Examiner, Art Unit 2133
Read full office action

Prosecution Timeline

Show 1 earlier event
Dec 08, 2025
Non-Final Rejection (signed) — §103
Jan 14, 2026
Non-Final Rejection mailed — §103
Feb 10, 2026
Interview Requested
Feb 17, 2026
Examiner Interview Summary
Feb 17, 2026
Applicant Interview (Telephonic)
Apr 09, 2026
Response Filed
Jun 24, 2026
Final Rejection mailed — §103
Jul 21, 2026
Interview Requested

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
93%
With Interview (+3.9%)
2y 7m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 586 resolved cases by this examiner. Grant probability derived from career allowance rate.

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