Prosecution Insights
Last updated: August 17, 2026
Application No. 18/891,854

MULTILAYER ELECTRONIC COMPONENT

Non-Final OA §102
Filed
Sep 20, 2024
Priority
Nov 21, 2023 — RE 10-2023-0162294
Examiner
MCFADDEN, MICHAEL P
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
725 granted / 840 resolved
+18.3% vs TC avg
Strong +20% interview lift
Without
With
+19.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
31 currently pending
Career history
849
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
61.5%
+21.5% vs TC avg
§102
30.2%
-9.8% vs TC avg
§112
4.7%
-35.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 840 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 12-20 are objected to because of the following informalities: Claim 12 has the limitation “the same dielectric layer first dielectric layer” it is believed this should read “the same dielectric layer”. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 7, and 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Beck et al (US 2019/0267193). Regarding claim 1, Beck discloses a multilayer electronic component (Fig. 1-6), comprising: a body (Fig. 4, 6) including a plurality of first dielectric layers (Fig. 4, 9), an internal electrode (Fig. 4, 10/11/12) including first (Fig. 4, 10) and second internal electrodes (Fig. 4, 11) spaced apart from each other on the same first dielectric layer (Fig. 4), and floating electrodes (Fig. 4, 12) alternately disposed with the internal electrode in a first direction (Fig. 4, up and down) with the first dielectric layer interposed therebetween (Fig. 4); and first and second external electrodes (Fig. 4, 7/8) disposed on the body and connected to the first and second internal electrodes, respectively (Fig. 4), wherein the body includes a double internal electrode comprising bilayered internal electrodes (Fig. 4, 10 above and below 13) disposed adjacently to each other in the first direction with a second dielectric layer (Fig. 4, 13) interposed therebetween (Fig. 4). Regarding claim 2, Beck further discloses that the double internal electrode is disposed in a center portion of the body in the first direction (Fig. 4). Regarding claim 3, Beck further discloses that the number of the double internal electrode is one (Fig. 4). Regarding claim 4, Beck further discloses that the second dielectric layer has a different composition from a composition of the first dielectric layers ([0024]). Regarding claim 7, Beck further discloses that when an average size of the first dielectric layer in the first direction is referred to as td1 and an average size of the second dielectric layer in the first direction is referred to as td2, td2 < td1 is satisfied (Fig. 4, 9 has thicker portions than 13). Regarding claim 10, Beck further discloses that the floating electrodes partially overlap the first and second internal electrodes in the first direction to form capacitance (Fig. 4). Regarding claim 11, Beck further discloses that the double internal electrode comprises: double first internal electrodes (Fig. 4, 10) including a double first-first internal electrode and a double first-second internal electrode (Fig. 4, 10 above and below 13) alternatively arranged with the second dielectric layer interposed therebetween (Fig. 4); and double second internal electrodes (Fig. 4, 11) including a double second-first internal electrode and a double second-second internal electrode (Fig. 4, 11 above and below 13) alternatively arranged with the second dielectric layer interposed therebetween (Fig. 4), wherein the double first-first internal electrode and the double second-first internal electrode are spaced apart from each other and disposed on one surface of the second dielectric layer (Fig. 4, indirectly on the surface of 13), and wherein the double first-second internal electrode and the double second-second internal electrode are spaced apart from each other and disposed on another surface of the second dielectric layer (Fig. 4, indirectly on the surface of 13). Claim(s) 12-13, 18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SEO et al (US 2015/0179339). Regarding claim 12, SEO discloses a multilayer electronic component (Fig. 1-3), comprising: a body (Fig. 3, 110) including a plurality of first dielectric layers (Fig. 3, 111), an internal electrode (Fig. 3, 121/122) including first (Fig. 3, 121) and second internal electrodes (Fig. 3, 122) spaced apart from each other on the same dielectric layer (Fig. 3), and floating electrodes (Fig. 3, 123) alternately arranged with the internal electrode in a first direction (Fig. 3, up and down) with the first dielectric layer interposed therebetween (Fig. 3); and first and second external electrodes disposed on the body and connected to the first and second internal electrodes (Fig. 3, 131/132), respectively, wherein the body includes a double floating electrode (Fig. 3, 123/123’) comprising bilayered floating electrodes disposed adjacently to each other in the first direction with a second dielectric layer interposed therebetween (Fig. 3, 123 in center, 111 between 123 is considered a second dielectric layer). Regarding claim 13, SEO further discloses that the double floating electrode is disposed in a center portion of the body in the first direction (Fig. 3). Regarding claim 18, SEO further discloses that when an average size of the first dielectric layer in the first direction is referred to as td1 and an average size of the second dielectric layer in the first direction is referred to as td2, td2 < td1 is satisfied (Fig. 3, 111 between layers is smaller Table 1). Regarding claim 20, SEO further discloses that the floating electrodes partially overlap the first and second internal electrodes in the first direction to form capacitance (Fig. 3). Allowable Subject Matter Claims 5-6, 8-9, 14-17, and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 5, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein when the number of pores per 1 μm2 included in a cross-section of the first dielectric layer is referred to as A, and the number of pores per 1 μm2 included in a cross-section of the second dielectric layer is referred to as B, B < A is satisfied” in combination with the other claim limitations. Regarding claim 6, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein when the number of pores per 1 μm2 included in a cross-section of the second dielectric layer is referred to as B, 1000 × B ≤ 5.00 is satisfied” in combination with the other claim limitations. Regarding claim 8, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein 8 × td2 ≤ td1 is satisfied” in combination with the other claim limitations. Regarding claim 9, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein when an average size of the first dielectric layer in the first direction is referred to as td1 and an average size of at least one of the floating electrodes in the first direction is referred to as te3, 2 × te3 < td1 is satisfied” in combination with the other claim limitations. Regarding claim 14, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein the number of the double internal electrode is one” in combination with the other claim limitations. Regarding claim 15, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein the second dielectric layer has a different composition from a composition of the first dielectric layer” in combination with the other claim limitations. Regarding claim 16, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein when the number of pores per 1 μm2 included in a cross-section of the second dielectric layer is referred to as B, and the number of pores per 1 μm2 included in a cross-section of the first dielectric layer is referred to as A, B < A is satisfied” in combination with the other claim limitations. Regarding claim 17, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein when the number of pores per 1 μm2 included in a cross-section of the second dielectric layer is referred to as B, 1000 × B ≤ 5.00 is satisfied” in combination with the other claim limitations. Regarding claim 19, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein 8 × td2 ≤ td1 is satisfied” in combination with the other claim limitations. Additional Relevant Prior Art: Ellmore et al (US 2015/0146343) teaches relevant art in Fig. 1-2. Bultitude (US 2018/0012706) teaches relevant art in Fig. 1-11. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Sep 20, 2024
Application Filed
Jul 16, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+19.8%)
2y 2m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 840 resolved cases by this examiner. Grant probability derived from career allowance rate.

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