Prosecution Insights
Last updated: October 02, 2026
Application No. 18/891,993

PEAK CURRENT DETECTION FOR SELECTING BETWEEN MEMORY POWER SUPPLY RAILS

Non-Final OA §102§103
Filed
Sep 20, 2024
Examiner
DEROSE, VOLVICK
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Qualcomm Incorporated
OA Round
3 (Non-Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
576 granted / 640 resolved
+35.0% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
19 currently pending
Career history
654
Total Applications
across all art units

Statute-Specific Performance

§101
3.8%
-36.2% vs TC avg
§103
52.8%
+12.8% vs TC avg
§102
29.7%
-10.3% vs TC avg
§112
4.5%
-35.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§102 §103
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claims 1-20 are presented for examination Reopen Prosecution Prosecution of this application has been reopened due to a newly prior art found Allowable Subject Matter Claim 20 is allowed because none of the prior arts of record taken singly or in combination fail to teach, anticipate, suggest, or render obvious the foregoing limitations. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – ((a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2, 5-8, 10-12, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uan-zo-li (US Patent Application 20170160777). As per claim 1, Uan-zo-li teaches an apparatus [100, fig. 1] for power control, comprising: a memory [109, fig. 1] configured to consume power from a first voltage rail [102, fig. 1] [0026-0027, as pointed out component 109 which is a load can be viewed as memory that connected to the standard rail 102. For example, the one or more sensors 106 are coupled to microcontroller 108 to monitor a load associated with the components 109, 111 and 112 that are coupled via the ports 113, 114 and 115 to the standby power supply rail 102]. a controller [108, fig. 1] configured to: detect whether current consumption from the first voltage rail is greater than or equal to a current threshold [0026, as pointed out the controller make determination by comparing the power consumed to a threshold of the standard rail 102. For example, in one embodiment, the one or more sensors 106 are coupled to microcontroller 108 to compare the load with a predetermined threshold stored in memory 108. In one embodiment, the predetermined threshold is calculated based on the power consumed by the one or more components, the standby rail power capacity, or a combination thereof. In one embodiment, the predetermined threshold is a maximum load allowed for the standby power supply rail according to an ATX specification to prevent the system from crashing, or any other threshold determined by design. If the load is greater than the predetermined threshold, the one or more sensors 106 are coupled to microcontroller 108 to send a signal to switch 104 to disconnect the standby power supply rail 102 from the ports 113, 114 and 115 and to connect main power supply rail 103 to the ports 113, 114 and 115]. determine whether a voltage of a second voltage rail is greater than a voltage threshold in response to the current consumption being greater than or equal to the current threshold [0027-0028, fig. 2, the power can be comparted to a threshold stored in the memory. For example, the one or more sensors 106 are coupled to microcontroller 108 to monitor the load associated with one or more components coupled via the one or more ports to the main power supply rail 103. In one embodiment, the one or more sensors 106 are coupled to microcontroller 108 to compare the load with a predetermined threshold stored in memory 108. In one embodiment, the predetermined threshold is a maximum load for the standby power supply rail. As shown in paraph 0028, it is determined if at least one of a power or a load associated with the one or more components greater than a predetermined threshold]. cause the memory to consume current from the second voltage rail instead of the first voltage rail based on the voltage being greater than the voltage threshold [0028, as pointed out when the power of one component is greater than a threshold, the second power rail is turn on and the component is switched to the second power rail. For example, if the at least one of the power or the load associated with the one or more components is greater than the predetermined threshold, the second power supply is turned on, and at block 203 the one or more components are switched from the first power supply rail to a second power supply rail. In one embodiment, the second power supply rail is a main power supply rail, as described above]. As per claim 2, Uan-zo-li teaches the controller is configured to detect whether the current consumption is greater than or equal to the current threshold by detecting whether the current consumption is at a peak current capability associated with the first voltage rail [0026, as pointed out, the predetermined threshold is a maximum load allowed for the standby power supply rail according to an ATX specification to prevent the system from crashing, or any other threshold determined by design]. As per claim 5, Uan-zo-li teaches the controller is further configured to determine whether the voltage of the second voltage rail is less than or equal to a voltage of the first voltage rail, wherein the controller is configured to cause the memory to consume the current from the second voltage rail further based on the voltage of the second voltage rail being less than or equal to the voltage of the first voltage rail [0028, as pointed out, if the at least one of the power or the load associated with the one or more components is greater than the predetermined threshold, the second power supply is turned on, and at block 203 the one or more components are switched from the first power supply rail to a second power supply rail]. As per claim 6, Uan-zo-li teaches the controller is further configured to cause the voltage of the second voltage rail to increase above the voltage threshold based on the determination that the voltage of the second voltage rail is less than the voltage threshold [0018, reconfiguration of the rail after power increases]. and the controller is configured to cause the memory to consume the current from the second voltage rail after the voltage of the second voltage rail has been increased above the voltage threshold [0018, 0028, reconfiguration of the rail based on the increases of power consumed by the components]. As per claim 7, Uan-zo-li t teaches a multiplexer [104, fig. 1] including a first input coupled to the first voltage rail [102, fig. 1], a second input coupled to the second voltage rail [103, fig. 1], and an output coupled to a power supply input of the memory, wherein to cause the memory to consume the current from the second voltage rail, the controller is configured to control the multiplexer [0026, as shown in figure 1, switch 104 which is viewed as a multiplexer is connected to rail 102 and 103 where the output is connected to component 114 which can be viewed as memory]. As per claim 8, Uan-zo-li teaches, the controller is configured to cause the memory to consume current from the second voltage rail instead of throttling one or more components configured to consume power from the first voltage rail [0015, as pointed out, the one or more components are switched to a second power supply rail when the at least one of the load or power is greater than a predetermined threshold]. As per claim 10, Uan-zo-li teaches, the first voltage rail is coupled to a power supply input of the other memory [0024, as shown in figure 1, the voltage rail 102 is connected to power supply 101]. As per claims 11-12, 15-17, and 19, they do not teach or further define the limitations recited in the rejected claims above. Therefore, claims 11-12, 15-17, and 18 are also anticipated by Uan-zo-li for the same reasons set forth in the rejected claims above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3-4, 9, 13-14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Uan-zo-li (US Patent Application 20170160777) in the view of Lee (US Patent Application 20150058644). As per claim 3, Uan-zo-li does not teach the memory is associated with a CPU [1412, fig. 14] [as shown in figure 14, CPU 1412]. However, Lee teaches the memory is associated with a CPU [1412, fig. 14] [as shown in figure 14, CPU 1412]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Uan-zo-li to include the method of Lee to include a CPU as a load. As per claim 4, Uan-zo-li does not teach the CPU memory comprises a cache for the CPU. However, Lee teaches the CPU memory comprises a cache [1408, fig. 14] for the CPU [as shown in figure 14. Cash 1408 is associated or connected to CPU 1412]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Uan-zo-li to include the method of Lee to include a CPU as a load. As per claims 9, 13-14, and 18, they do not teach or further define over the limitations recited in the rejected claims above. Therefore, claims 9, 13-14, and 18 are also rejected as being unpatentable over Uan-zo-li in view of Lee for the same reasons set forth in the rejected claims above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VOLVICK DEROSE whose telephone number is (571)272-6260. The examiner can normally be reached on Monday-Friday 9AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 571.270.1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VOLVICK DEROSE/Primary Examiner, Art Unit 2176
Read full office action

Prosecution Timeline

Sep 20, 2024
Application Filed
Feb 24, 2026
Non-Final Rejection mailed — §102, §103
May 08, 2026
Response Filed
Jun 03, 2026
Final Rejection mailed — §102, §103
Jul 24, 2026
Response after Non-Final Action
Aug 11, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+11.1%)
2y 2m (~2m remaining)
Median Time to Grant
High
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allowance rate.

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