DETAILED ACTION
This action is responsive to the following: the application filed on September 20, 2024 and foreign priority documents received on October 16, 2024.
Claims 1-20 are pending. Claims 1, 16 and 20 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 8-9, 11,16, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takita et al (US 6628564 B1).
Regarding Independent Claim 1, A memory device (Fig. 21), comprising:
a memory cell array (Fig. 23: 100) comprising a plurality of rows of memory cells and a word line (Fig. 23: 150) coupled to each of the plurality of rows of memory cells; and
a peripheral circuit (Fig. 23: 400) coupled with a corresponding row of memory cells via the word line (Fig. 23: 200), and comprising a first power supply circuit (col 5 line 55-56 “Vbb represents the back-bias voltage of the cell transistor” ) and a second power supply circuit (Fig. 23: 400), wherein:
the first power supply circuit is configured to start outputting a first voltage to a substrate of a first transistor (Fig. 6: 22, 23) that is comprised in a first word line drive circuit (Fig. 6: 2) coupled to a first unselected word line (Fig. 6: SWL) at a first time instant (col 5 lines 64-67 col 6 lines 1-4 “The negative potential Vbb is applied as the back-bias to the cell transistor so as (1) to prevent the forward-bias of the p-n junction inside the chip and to prevent also the destruction of the data and latch-up, (2) to reduce the change of the threshold voltage of the MOS transistor, (3) to reduce the junction capacitance by the back-bias (i.e., reverse-bias), and (4) to improve the transistor characteristics by increasing the threshold voltage of a parasitic MOS transistor.” It’s understood that the back bias would be applied at power up in order to function as described, which would precede any mode the word lines used in.); and
the second power supply circuit (Fig. 23: 400) is configured to start outputting a second voltage (Fig. 6: Vnwl) to a terminal of the first transistor (Fig. 6: 22, 23) at a second time instant (Fig. 7: Standby),
wherein the first time instant is earlier than the second time instant (col 5 lines 64-67 col 6 lines 1-4 “The negative potential Vbb is applied as the back-bias to the cell transistor so as (1) to prevent the forward-bias of the p-n junction inside the chip and to prevent also the destruction of the data and latch-up, (2) to reduce the change of the threshold voltage of the MOS transistor, (3) to reduce the junction capacitance by the back-bias (i.e., reverse-bias), and (4) to improve the transistor characteristics by increasing the threshold voltage of a parasitic MOS transistor.” It’s understood that the back bias would be applied at power up in order to function as described, which would precede any mode the word lines used in.).
Regarding Claim 2, Takita teaches the limitations of Claim 1. Takita further teaches wherein the first voltage and the second voltage are negative voltages (Fig. 4: Vbb, Vnwl).
Regarding Claim 3, Takita teaches the limitations of Claim 1. Takita further teaches wherein the plurality of rows of memory cells (Fig. 23: 150) comprise a plurality of memory cells, and each of the plurality of memory cells comprises a second transistor and a capacitor (col 1 lines 40-43 “Generally, each of a plurality of memory cells that constitute a memory cell array in the DRAM includes one cell transistor for reading or writing data and one cell capacitor connected to the source of this cell transistor.”),
wherein a first terminal of the second transistor is connected with a terminal of the capacitor (col 1 lines 39-42 “Generally, each of a plurality of memory cells that constitute a memory cell array in the DRAM includes one cell transistor for reading or writing data and one cell capacitor connected to the source of this cell transistor.”), a second terminal of the second transistor is connected with a bit line corresponding to the second transistor (col 4 lines 58-60 “The source and the drain of the cell transistor are connected to one of the ends of the capacitance and to the bit line”), and a control terminal of the second transistor is connected with a word line corresponding to the second transistor (col 1 lines 43-48 “The cell capacitor stores a charge depending on the logic "1" or "0" of the data written into the memory cell. A word line is connected to the gate of each cell transistor so as to supply a voltage necessary for bringing this cell transistor into an operating state (activated state).”), and
wherein the first power supply circuit is further configured to provide the first voltage to a substrate of the second transistor (col 5 lines 64-65 “The negative potential Vbb is applied as the back-bias to the cell transistor”).
Regarding Claim 8, Takita teaches the limitations of Claim 1. Takita further teaches wherein the peripheral circuit further comprises a third power supply circuit (Fig. 5: 110-0), wherein:
the first power supply circuit is further configured to start outputting the first voltage to a substrate of a third transistor that is comprised in a second word line drive circuit coupled with a second unselected word line at the first time instant; and
the third power supply circuit (Fig. 5: 110-0) is configured to start outputting a third voltage (Fig. 6: VPP) to a terminal of the third transistor (Fig. 6: 11) at a third time instant (Fig. 7: active),
wherein the first time instant is earlier than the third time instant (col 5 lines 64-67 col 6 lines 1-4 “The negative potential Vbb is applied as the back-bias to the cell transistor so as (1) to prevent the forward-bias of the p-n junction inside the chip and to prevent also the destruction of the data and latch-up, (2) to reduce the change of the threshold voltage of the MOS transistor, (3) to reduce the junction capacitance by the back-bias (i.e., reverse-bias), and (4) to improve the transistor characteristics by increasing the threshold voltage of a parasitic MOS transistor.” It’s understood that the back bias would be applied at power up in order to function as described, which would precede any mode the word lines used in.).
Regarding Claim 9, Takita teaches the limitations of Claim 8. Takita further teaches wherein the memory cell array (Fig. 23) comprises a plurality of memory blocks (Fig. 23: 800-0 to 800-n), and each of the plurality of memory blocks comprises the plurality of rows of memory cells (Fig. 23: 150) and the word line (Fig. 23: 150) coupled to each of the plurality of rows of memory cells, and
wherein the second unselected word line comprises a word line belonging to the same memory block as a selected word line.
Regarding Claim 11, Takita teaches the limitations of Claim 9. wherein the first unselected word line comprises an unselected word line other than the second unselected word line (Fig. 23: 150; Takita teaches multiple word lines in an array).
Regarding Independent Claim 16, Takita teaches A power supply method for a memory device, comprising:
starting generating a first voltage at a first time instant (col 5 lines 64-67 col 6 lines 1-4 “The negative potential Vbb is applied as the back-bias to the cell transistor so as (1) to prevent the forward-bias of the p-n junction inside the chip and to prevent also the destruction of the data and latch-up, (2) to reduce the change of the threshold voltage of the MOS transistor, (3) to reduce the junction capacitance by the back-bias (i.e., reverse-bias), and (4) to improve the transistor characteristics by increasing the threshold voltage of a parasitic MOS transistor.” It’s understood that the back bias would be applied at power up in order to function as described, which would precede any mode the word lines used in.);
providing the first voltage to a substrate of a first transistor (Fig. 6: 22, 23) that is comprised in a first word line drive circuit (Fig. 6: 2) coupled to a first unselected word line (Fig. 6: SWL); and
starting generating a second voltage (Fig. 7: Vnwl) at a second time instant Fig. 7: NODE n03 Standby); and
providing the second voltage (Fig. 6: Vnwl) to a terminal of the first transistor (Fig. 6: 22, 23),
wherein the first time instant is earlier than the second time instant (col 5 lines 64-67 col 6 lines 1-4 “The negative potential Vbb is applied as the back-bias to the cell transistor so as (1) to prevent the forward-bias of the p-n junction inside the chip and to prevent also the destruction of the data and latch-up, (2) to reduce the change of the threshold voltage of the MOS transistor, (3) to reduce the junction capacitance by the back-bias (i.e., reverse-bias), and (4) to improve the transistor characteristics by increasing the threshold voltage of a parasitic MOS transistor.” It’s understood that the back bias would be applied at power up in order to function as described, which would precede any mode the word lines used in.).
Regarding Claim 19, Takita teaches the limitations of claim 16. Takita further teaches providing the first voltage to a substrate of a second transistor that is comprised in a memory cell comprised in the memory device (col 5 lines 64-65 “The negative potential Vbb is applied as the back-bias to the cell transistor”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Takita et al (US 6628564 B1) in view of Kim et al (US 20090261792 A1).
Regarding Claim 13, Takita teaches the limitations of claim 1. Takita teaches a first power supply circuit (Fig. .
However, Takita fails to teach a first comparator.
Kim teaches wherein power supply circuit (Fig. 7) comprises a first comparator (Fig. 7: 200) and a voltage generator (Fig. 7: 300), wherein:
the first comparator (Fig. 7: 200) is configured to compare a reference voltage (Fig. 7: VREF1) with a first feedback voltage (Fig. 7: VFB), and output a first control signal (Fig. 7: DRV) according to a comparison result; the first feedback voltage (Fig. 7: VFB) is obtained according to the first voltage output by the voltage generator (Fig. 7: 300); and
the voltage generator (Fig. 7: 300) is configured to output the first voltage (Fig. 7: VNN) according to the first control signal (Fig. 7: DRV).
This type of power supply generator is useful because leakage is an issue in DRAM therefore keeping the gates of cells at voltages below ground when not in use can greatly reduce leakage on the bit line and reduce the risk of read disturb when reading cells.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kim to the teachings of Takita in order to produce a power supply circuit that comprises a first comparator and voltage generator circuit to produce a negative voltage that can be applied to word lines.
Regarding Claim 14, Takita and Kim teach the limitations of claim 13. Kim further teaches wherein the first power supply circuit further comprises: a feedback generator (Fig. 7: 320) configured to receive the first voltage (Fig. 7: VNN) and output the first feedback voltage (Fig. 7: VFB) according to the first voltage; and
a reference generator (Fig. 10: 524) configured to output the reference voltage (Fig. 7: VREF1).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20090261792 A1; hereafter called Kim ‘792) in view of Kim et al (US 20230146885 A1; hereafter called Kim ‘885).
Regarding Independent Claim 20, Kim 792 teaches A charge pump circuit, comprising: a feedback generator (Fig. 7: 320), a reference generator (Fig. 9: 510), a first comparator (Fig. 7: 300), and a voltage generator (Fig. 7: 300), wherein:
the feedback generator (Fig. 7: 320) is connected between a first node (Fig. 7: PM2 gate) and an output terminal (Fig. 7: E) of the voltage generator (Fig. 7: 300) and an output terminal of the feedback generator (Fig. 7: 320) is connected with a first input terminal (Fig. 7: PM2 gate) of the first comparator (Fig. 7: 200);
the reference generator (Fig. 10: 524) is connected between the first node (Fig. 10: VR) and ground, and an output terminal (Fig. 7: VREF1) of the reference generator is connected with a second input terminal of the first comparator (Fig. 7: 200);
an output terminal of the first comparator (Fig. 7: DRV) is connected with an input terminal of the voltage generator (Fig. 7: NM3, gate); and
the output terminal of the voltage generator (Fig. 7: VNN) outputs a negative voltage (para 7 “a high voltage VPP is provided when enabling a wordline, and a negative voltage VNN lower than the ground level is provided when disabling a wordline.”).
Kim ‘792 fails to teach and has an input terminal to which a first enable signal is input.
Kim ‘885 teaches and has an input terminal to which a first enable signal (Fig. 5: SW3) is input.
Disabling feedback can be done to as part of non-active or standby modes for power supplies. Reducing power consumption when not in use and preventing wear on circuit components that may be experiencing significant voltage differential that can damage components over time. Therefore, the ability to disable feedback would be useful to add to a power supply circuit.
It therefore would have been obvious to one of ordinary skill in the art prior to filing date of the claimed invention to apply the teachings of Kim ‘885 to the teachings of Kim ‘792 to produce a power supply generating circuit that has a feedback generating circuit that can be enabled or disabled.
Allowable Subject Matter
Claims 4-7, 10, 12, 15, and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4, Claim 4 would be allowable for teaching that first power supply is output in response to the an enable signal. Takita teaches a first power supply. But is silent with respect to whether it is controlled by an enable signal. Therefore, this claim would be allowable if written in independent form.
Claims 5-7 would be allowable for being dependent on claim 4.
Claim 10, would be allowable for teaching that word lines are shared between multiple blocks. Takita and Kim ‘885 teach multiple word lines and multiple blocks, but both are silent with respect to word lines being shared between multiple blocks. Therefore, this claim would be allowable if written in independent form.
Claim 12, would be allowable for disclosing that the absolute value of the third voltage is larger than the absolute value of the second target value of the second voltage. All of the references applied are silent with respect to this relative magnitude of the voltages with respect to each other. Therefore, this claim would be allowable if written in independent form.
Claim 15 would be allowable for teach that the clock drive circuit generates a fourth control signal. Takita teaches a subcircuit of the voltage generator that receives the first control signal but fails to teach generating and internal fourth control signal. Therefore, this claim would be allowable if written in independent form.
Claim 17 would be allowable for requiring that the ratio of the preset targe voltage value and first target voltage value must be between 50% and 90%. All of the applied references are silent with respect to the ratio of voltage values to one another. Therefore, this claim would be allowable if written in independent form.
Claim 18 would be allowable for being dependent on Claim 17.
Conclusion
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825
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