DETAILED ACTION
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
In claims 1 and 12, the claim term “a respective output register”, “a specified output register” has no antecedent basis to specification.
Claim Objections
Claim 1 is objected to because of the following informalities:
In claim 1, line 5, change “each include” to “each includes”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Shiell (US 6,338,137).
Referring to claims 1 and 12, Shiell discloses a circuit device comprising:
a processor core (fig. 1, DSP) that includes:
a functional unit (fig. 1, S1/L2/M1/D1, S2/L2/M2/D2; 8:4-6, functional units); and
a plurality of address generators (fig. 2, subsection 288; 8:31-35, address calculation) coupled to the functional unit that each includes a respective output register (2:59-3:19, bits 17-13, register; fig. 1, register file 125) to store a respective address value (fig. 2, address for access to memory),
wherein the processor core is to:
receive an instruction (2:59-3:19, instruction) that includes a field that specifies a specified output register (2:59-3:19, bits 17-13, offset fig. 2, offset 208) from among the respective output registers of the plurality of address generators; and
execute the instruction (fig. 2, control logic output; 2:47-58 execute processor instructions) using the functional unit (fig. 2, such as control A to F, command for L/S) and the respective address value stored in the specified output register (fig. 2, output from subsection 288, address for access to memory).
As to claims 2 and 13, Shiell discloses the device of claim 1, wherein:
the respective address value stored in the specified output register is an offset address value (fig. 2, offset register 208); and
the functional unit is to add a base address (fig. 2, adder 290) to the offset address value stored in the specified output register to determine a source address (fig. 2, address for access memory).
As to claims 3 and 14, Shiell discloses the device of claim 2, wherein the functional unit includes a base address register (fig. 2, base address register 207) to store the base address.
As to claims 4 and 15, Shiell discloses the device of claim 2, comprises a register file (fig. 2, register file 125) coupled to the functional unit and to store the base address.
As to claims 5 and 16, Shiell discloses the device of claim 2, wherein the instruction to perform a load instruction (fig. 2, load multiple unit; 5:1-4, LDM instruction) using the source address.
As to claims 6 and 17, Shiell discloses the device of claim 2, wherein the instruction to perform a store instruction (fig. 2, store multiple unit; 5:1-4, STM instruction) using the source address.
As to claims 7 and 18, Shiell discloses the device of claim 1, wherein the instruction specifies whether to increment the respective address value (6:16-23, 0:no-update, 1:auto-increment) stored in the specified output register.
As to claims 8 and 19, Shiell discloses the device of claim 1, wherein:
each of the plurality of address generators includes a respective control register (2:26-28, control registers) to store a respective set of loop iteration counters (4:39-43, iterations, 32-bit control register); and
each of the plurality of address generators is to produce the respective address value based on the respective set of loop iteration counts (fig. 2, output of subsection 288).
As to claims 9 and 20, Sheill discloses the device of claim 6, wherein the respective control register of each of the plurality of address generators is to store a respective measure of elements between iterations of a respective loop (4:39-43, iterations, 32-bit control register).
As to claim 10, Sheill discloses the device of claim 5, wherein each of the plurality of address generators includes a respective predicate register (2:58-63, bits 31-28, register) to store a predicate value (2:58-63, predicated value).
As to claim 11, Sheill discloses the device of claim 1, wherein:
the functional unit is a first functional unit (fig. 1, S1/L1/M1/D1 of A-side);
the instruction is a first instruction (fig. 2, load multiple unit; 5:1-4, LDM instruction);
the specified output register is a first specified output register (fig. 1, register file A 125);
the processor core includes a second functional unit (fig. 1, S2/L2/M2/D2 of B-side) coupled to the plurality of address generator; and
the processor core is to:
receive a second instruction (fig. 2, store multiple unit; 5:1-4, STM instruction) that includes a field specifying a second specified output register (fig. 2, output from subsection 288, address for access to memory) from among the respective output registers of the plurality of address generators,
wherein the first specified output register and the second specified output register are independent (fig. 1, A-side 115A and B-side 115B are independent); and
execute the second instruction (fig. 2, control logic output) using the respective address value stored in the second specified output register (fig. 2, output from subsection 288, address for access to memory).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See M.P.E.P 707.05(c).
US 2017/0,308,381 discloses streaming engine has address generator with base and offset addresses, predicate register, and loop iteration counter.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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