DETAILED ACTION
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
In claims 1 and 12, the claim terms “a respective output register” and “an output register” have no antecedent basis to specification.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitations are:
“a respective output register configured to …” in claim 1. There is no specific register element found in specification.
“base address register configured to …” in claim 3. There is no specific register element found in specification.
“processor core configured to: …” in claims 1 and 12 having corresponding structure such as CPU core 310.
“functional unit configure to …” in claim 2 with corresponding structure such as functional units 351/361 in fig. 3.
“control register configured to …” in claim 8 with corresponding structure of control registers 144 in fig. 2.
“address generator configured to …” in claims 9 and 12 with corresponding structure such as SAG0/SAG1/SAG2/SAG3 found in fig. 3.
“respective predicate register configured to …” in claim 10. In para.0052, the specification describes a predicate is generated by SAGs, and stored in respective predicate streaming address registers 60/61.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 3 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim limitations “respective output register” and “base address register” invoke 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Shiell (US 6,338,137).
Referring to claims 1 and 12, Shiell discloses a circuit device comprising:
a processor core (fig. 1, DSP) that includes:
a functional unit (fig. 1, A-Side 115A S1/L2/M1/D1, B-Size 115B S2/L2/M2/D2; 8:4-6, functional units); and
a plurality of address generators (fig. 2, subsection 288; 8:31-35, address calculation; fig. 1, LM/STM unit 130) coupled to the functional unit,
wherein each of the plurality of address generators includes a respective output register (fig. 1, register file 125; 2:59-3:19, bits 17-13, register) to store a respective address value (fig. 2, address for access to memory; address output register 285; 10:54-57) generated by the respective address generator,
wherein the processor core is to:
receive an instruction (fig. 1, instruction 110; 2:59-3:19, instruction) that includes a field that specifies an output register (2:59-3:19, bits 31:0, destination register bits 27:23 among registers from operation sides A/B bit 8:1) from among the respective output registers of the plurality of address generators; and
execute the instruction (fig. 2, operating sides A/B 115A/115B; 2:47-58, execute processor instructions) using the functional unit (fig. 2, S, L, M, D units 120; 8:8-16) and the respective address value stored in the output register (fig. 2, output from subsection 288, address for access to memory; 2:59-3:19, bits 31:0, destination register bits 27:23 among registers from operation sides A/B bit 8:1) specified by the instruction.
As to claims 2 and 13, Shiell discloses the device of claim 1, wherein:
the respective address value stored in the output register specified by the instruction is an offset address value (fig. 2, offset register 280); and
the functional unit is to add (fig. 2, adder 290) a base address (fig. 2, base address register contents 207) to the offset address value stored in the output register specified by the instruction to determine a source address (fig. 2, address for access memory; 2:59-3:19, bits 31:0, source register bits 27:23 among registers from operation sides A/B bit 8:1).
As to claims 3 and 14, Shiell discloses the device of claim 2, wherein the functional unit includes a base address register (fig. 2, base address register 207) to store the base address.
As to claims 4 and 15, Shiell discloses the device of claim 2, comprises a register file (fig. 2, register file 125) coupled to the functional unit and to store the base address.
As to claims 5 and 16, Shiell discloses the device of claim 2, wherein the instruction to perform a load instruction (fig. 2, load multiple unit; 5:1-4, LDM instruction) using the source address.
As to claims 6 and 17, Shiell discloses the device of claim 2, wherein the instruction to perform a store instruction (fig. 2, store multiple unit; 5:1-4, STM instruction) using the source address.
As to claims 7 and 18, Shiell discloses the device of claim 1, wherein the instruction specifies whether to increment the respective address value (6:16-23, 0:no-update, 1:auto-increment) stored in the specified output register specified by the instruction (fig. 1, instruction 110; 2:59-3:19, bits 31:0).
As to claims 8 and 19, Shiell discloses the device of claim 1, wherein:
each of the plurality of address generators includes a respective control register (2:26-28, control registers) to store a respective set of loop iteration counters (4:39-43, iterations, 32-bit control register); and
each of the plurality of address generators is to produce the respective address value based on the respective set of loop iteration counts (fig. 2, output of subsection 288).
As to claims 9 and 20, Sheill discloses the device of claim 6, wherein the respective control register of each of the plurality of address generators is to store a respective measure of elements between iterations of a respective loop (4:39-43, iterations, 32-bit control register).
As to claim 10, Sheill discloses the device of claim 5, wherein each of the plurality of address generators includes a respective predicate register (2:58-63, bits 31-28, register) to store a predicate value (2:58-63, predicated value).
As to claim 11, Sheill discloses the device of claim 1, wherein:
the functional unit is a first functional unit (fig. 1, S1/L1/M1/D1 of A-side);
the instruction is a first instruction (fig. 2, load multiple unit; 5:1-4, LDM instruction);
the output register specified by the instruction (2:59-3:19, bits 31:0, destination bits) is a first output register (fig. 1, register file A 125);
the processor core includes a second functional unit (fig. 1, S2/L2/M2/D2 of B-side) coupled to the plurality of address generator; and
the processor core is to:
receive a second instruction (fig. 2, store multiple unit; 5:1-4, STM instruction) that includes a field specifying a second output register (fig. 2, output from subsection 288, address for access to memory) from among the respective output registers of the plurality of address generators,
wherein the first output register and the second output register are independent (fig. 1, A-side 115A and B-side 115B are independent); and
execute the second instruction (fig. 2, control logic output) using the respective address value stored in the second output register (fig. 2, output from subsection 288, address for access to memory).
Response to Arguments
Applicant’s arguments have been fully considered, but they are not deemed to be persuasive.
Applicant argues that the claim terms “a respective output register” and “an output register” have clear support or antecedent basis found in specification (pp. 7-8).
The exact term “output register” has never been showing in specification. The term “output” related to “register” can be found in paras.0051 and 0055. The paragraphs describe outputting to offset registers. The specification does not have different terminologies to distinguish between output registers and respective output register; therefore there is no sufficient support or antecedent basis for such two terms.
Further, each address generator is disclosed with output registers of 1) predicate streaming address register PSA 60, or 2) streaming address offset register SA 390 as in fig. 3. It is unclear which register the claimed “output register” is referring to if without proper antecedent basis.
Applicant argues that the cited prior art does not disclose “output register”, and Shiell’s offset is supplied as input (pp. 8-10).
Shiell discloses executing instructions that causes address generator 288 to generate “address for access to memory” as in fig. 2. The instruction includes source and destination registers as in 2:58-3:19. The output register is specified in the instruction with destination fields and a result of address for access register 285 and offset register 280 as in fig. 2.
Shiell discloses two output registers from LM/STM unit 130 of A/B sides, and each with respective output register from LM/STM unit 130 specified by destination filed of instruction.
Conclusion
This action is made final. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire in three months from the mailing date of this action. In the event a first reply is filled within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date of the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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