DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 01/07/2026. Claims 1 and 19 have been amended. Claims 17-18 have been cancelled. Claims 21-22 have been added. Claims 1-16 and 19-22 are pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application, 16/731586 filed on 12/31/2019, under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully considered, with the Examiner’s response set forth below.
(1)In view of Applicant’s remarks regarding the double patenting rejection in that Applicant requests that this rejection be held in abeyance, the double patenting rejection has been maintained in the present Office action as a reminder for Applicant to timely file a terminal disclaimer.
(2) Applicant contends that, regarding claims 1 and 19, Higgins does not teach the amended limitation “determines access frequency of the data based on a combination of values of two or more classification parameters including a first classification parameter being the one or more of the read errors, the number of invalid pages per block, or the read disturb counter and a second classification parameter being a BER associated with the data”. Specifically, “the Office Action (at 11) points to Higgins' disclosure in para. [0113] of predicting read frequency based on ‘one or more’ of an analysis of bit error rates and an amount of read disturbs. However, this would not teach or suggest ‘determine[ing] access frequency of the data based on a combination of values of two or more classification parameters including a first classification parameter being the one or more of the read errors, the number of invalid pages per block, or the read disturb counter and a second classification parameter being a BER associated with the data’ as more explicitly set forth in the claims”. The Examiner respectfully disagrees.
The amended limitation in claim 1 requires an access frequency of a particular data be determined by using a combination of values of two classification parameters, where a first parameter is one or more of the read errors, the number of invalid pages per block, or the read disturb counter; and a second parameter is a bits error rate (BER) associated with the data. Higgins expressly discloses in paragraph [0113] that “the storage device predicts the read frequency for the particular data based on one or more of: (1) an analysis of bit error rates associated with the particular data, (2) an amount of read disturbs associated with the particular data”. The phrase “one or more of” explicitly encompasses the use of both listed factors (BER and read disturbs) together. Thus, Higgins teaches determining read frequency based on both bit error rates and read disturbs in combination. Furthermore, both parameters, “bit error rates” and “an amount of read disturbs”, are inherently quantifiable and represented by numerical values. Accordingly, determining read frequency based on both factors necessarily involves determining access frequency based on a combination of values of two classification parameters, as recited in the claim. Therefore, Higgins teaches the claimed limitation of determining access frequency of data based on a combination of values of two or more classification parameters, including a read disturb-based parameter and a BER-based parameter.
(3) The rest of Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(4) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5-8, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Higgins et al. (US 2017/0371559), hereinafter Higgins in view of Kong et al. (US 2014/0115239), hereinafter Kong.
Regarding claims 1 and 19, taking claim 1 as exemplary, Higgins teaches a Solid State Drive (SSD) device (Higgins, [0035], SSD), comprising:
a non-volatile memory storage (Higgins, [0035], In some embodiments, storage medium 132 is a single flash memory device while in other embodiments storage medium 132 includes a plurality of flash memory devices); and
a controller (Higgins, [0035], a storage device 120 (also sometimes called an information storage device, or a data storage device, or a memory device), which includes a storage controller 124 … storage controller 124 is a solid-state drive (SSD) controller) that:
determines one or more of read errors, a number of invalid pages per block, or a read disturb counter for the data (Higgins, [0091], FIG. 3 is a block diagram of a read disturb counts table 230, which stores read disturb counts 302 for corresponding non-volatile memory block zones);
determines access frequency of the data based on a combination of values of two or more classification parameters including a first classification parameter being the one or more of the read errors, the number of invalid pages per block, or the read disturb counter and a second classification parameter being a BER associated with the data (Higgins, [0113], the storage device predicts the read frequency for the particular data based on one or more of: (1) an analysis of bit error rates associated with the particular data, (2) an amount of read disturbs associated with the particular data);
partitions the non-volatile memory storage into a plurality of regions based on the access frequency (Higgins, [0094], In some embodiments, the logical address space comprises a plurality of regions (e.g., region 402-1 through 402-M). Tracking table 400 (also sometimes called a read table or read tracker) includes read accumulators 406 for tracking the amount and/or proportion of reads from each region. In some embodiments, tracking table 400 also includes bucket IDs 404 corresponding to each region. In some embodiments, bucket identifications (IDs) 404 are used to correlate read accumulators 406 with regions 402. In some embodiments, bucket IDs 404 are used to categorize each region. In some embodiments, the data in tracking table 400 is used to rank and/or categorize the regions by read frequency (also sometimes called read temperature). As an example, an address space is divided into a plurality of equal sized regions (e.g., 1024 regions) and the regions are categorized into a plurality of buckets (e.g., 3 buckets). In this example, the regions are re-categorized after a certain number of reads (e.g., 4 billion reads); [0056], memory controller 126 and NVM controllers 130 work in conjunction to perform any of the operations described herein with respect to storage device 120; [0069]; [0111], [0109]; Fig.2B; Note – Higgins implicitly teaches partitioning the non-volatile memory storage into a plurality of regions based on the determined access frequency as the controller appears to categorize the regions into buckets based on determined read frequency and performs the re-categorization periodically), each of the plurality of regions comprises one or more blocks (Higgins, [0096], FIG. 5A further shows regions 512 of non-volatile memory (e.g., particular regions of storage medium 132); [0046], a storage medium (e.g., storage medium 132) is divided into a number of addressable and individually selectable blocks).
Higgins does not explicitly teach a controller partitions the non-volatile memory storage into a plurality of regions based on the access frequency, as claimed.
However, Higgins in view of Kong explicitly teach a controller solid state drive (SSD) device comprising a controller (Kong, [0090], the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to form a solid state drive (SSD)) that: partitions the non-volatile memory storage into a plurality of regions based on the access frequency (Kong, [0037], the nonvolatile memory device includes a hot region and a cold region. The hot region may include first through nth blocks B1 through Bn (where n is a positive integer), and the cold region may include first through mth blocks C1 through Cm (where m is a positive integer); [0038], The hot region is a region that is frequently updated by the host).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Higgins to incorporate teachings of Kong to have a SSD controller to partition memory device into a plurality of regions based on access frequency. A person of ordinary skill in the art would have been motivated to combine the teachings of Higgins with Kong because it improves efficiency and performance of the storage system disclosed in Higgins by performing garbage collection operations on memory blocks with similar frequencies which reduces the number of blocks to be garbage collected (Kong, [0039]).
Claim 19 has similar limitations as claim 1 and is rejected for the similar reasons. Furthermore, regarding claim 19, Higgins teaches writing data to a non-volatile memory storage of a Solid State Drive (SSD) (Higgins, [0046], the encoding format of the storage media (i.e., TLC, MLC, or SLC and/or a chosen data redundancy mechanism or ECC code) is a choice made when data is received at the storage device or when written to the storage medium).
Regarding claim 3, the combination of Higgins teaches all the features with respect to claim 1 as outlined above. The combination of Higgins further teaches the SSD of claim 1, wherein the controller comprises an error correction system (Higgins, [0039], storage controller 124 includes … and, optionally, one or more additional module(s) 125, such as an error correction module and/or a garbage collection module; Fig.1A) that determines the read errors when the data is read from the non-volatile storage (Higgins, [0043], When encoded data (e.g., one or more codewords) is read from NVM devices 134, the decoder applies a decoding process to the encoded data to recover the data, and to correct errors in the recovered data within the error correcting capability of the error-correcting code; [0045], Storage medium interface 128 provides the raw read data (e.g., comprising one or more codewords) to a decoder (e.g., in additional module(s) 125) … if the decoding is not successful, storage controller 124 may resort to a number of remedial actions or provide an indication of an irresolvable error condition).
Regarding claim 5, the combination of Higgins teaches all the features with respect to claim 1 as outlined above. The combination of Higgins further teaches the SSD of claim 1, wherein the controller determines the access frequency of the data by: determining a first access frequency of data written on each of first blocks of the non-volatile memory storage (Kong, [0037], hot region may include first through nth blocks B1 through Bn (where n is a positive integer)); and determining a second access frequency of data written on each of second blocks of the non-volatile memory storage (Kong, [0037], cold region may include first through mth blocks C1 through Cm (where m is a positive integer) (Higgins, [0109], the storage device tracks (704) a number of read operations corresponding to a particular region of a plurality of regions in a logical address space), the first access frequency being higher than the second access frequency (Kong, [0038], The hot region is a region that is frequently updated by the host).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Higgins to incorporate teachings of Kong to have a SSD controller to partition memory device into a plurality of regions based on access frequency. A person of ordinary skill in the art would have been motivated to combine the teachings of Higgins with Kong because it improves efficiency and performance of the storage system disclosed in Higgins by performing garbage collection operations on memory blocks with similar frequencies which reduces the number of blocks to be garbage collected (Kong, [0039]).
Regarding claim 6, the combination of Higgins teaches all the features with respect to claim 5 as outlined above. The combination of Higgins further teaches the SSD of claim 5, wherein the controller partitions the non-volatile memory storage into the plurality of regions by: determining a first region comprising the first blocks (Kong, [0037], hot region may include first through nth blocks B1 through Bn (where n is a positive integer)); and determining a second region comprising the second blocks (Kong, [0037], cold region may include first through mth blocks C1 through Cm (where m is a positive integer)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Higgins to incorporate teachings of Kong to have a SSD controller to partition memory device into a plurality of regions based on access frequency. A person of ordinary skill in the art would have been motivated to combine the teachings of Higgins with Kong because it improves efficiency and performance of the storage system disclosed in Higgins by performing garbage collection operations on memory blocks with similar frequencies which reduces the number of blocks to be garbage collected (Kong, [0039]).
Regarding claim 7, the combination of Higgins teaches all the features with respect to claim 6 as outlined above. The combination of Higgins further teaches the SSD of claim 6, wherein first data determined to be frequently accessed is written in one of the first blocks in the first region; and second data determined to be infrequently accessed is written in one of the second blocks in the second region (Higgins, [0122], the predicted read frequency indicates (722) that the particular data is hot read data and the one or more preferred storage locations are denoted as having a fast read response; Kong, [0038], [0051], Pages of a cold region may be updated, albeit not as frequently as those of a hot region).
Regarding claim 8, the combination of Higgins teaches all the features with respect to claim 7 as outlined above. The combination of Higgins further teaches the SSD of claim 7, wherein the controller performs garbage collection more frequently in the first region than in the second region (Kong, [0038], Blocks included in the hot region undergo frequent page updates and garbage collection; Claim 17, performing garbage collection on the hot region of the nonvolatile memory more frequently than garbage collection is performed on the cold region of the nonvolatile memory.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Higgins to incorporate teachings of Kong to have a SSD controller to partition memory device into a plurality of regions based on access frequency. A person of ordinary skill in the art would have been motivated to combine the teachings of Higgins with Kong because it improves efficiency and performance of the storage system disclosed in Higgins by performing garbage collection operations on memory blocks with similar frequencies which reduces the number of blocks to be garbage collected (Kong, [0039]).
Claim 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins and Kong as applied to claim 1 above, and further in view of Lee et al. (US 2009/0310408), hereinafter Lee.
Regarding claim 2, the combination of Higgins teaches all the features with respect to claim 1 as outlined above. The combination of Higgins does not explicitly teach the SSD of claim 1, wherein the read errors comprises one or more of read-disturb sense errors or data retention errors, as claimed.
However, the combination of Higgins in view of Lee teaches the SSD of claim 1, wherein the read errors comprises one or more of read-disturb sense errors or data retention errors (Lee, [0409], The flash memory may be experiencing a bit error due to program or read disturbance).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Lee to work with flash memory errors caused by read disturbance. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Lee because it improves efficiency and reliability of the storage system disclosed in the combination of Higgins by reducing read errors caused by stress-based defect (Lee, [0644]).
Claim 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins and Kong as applied to claim 1 above, and further in view of Trichina et al. (US 2009/0157948), hereinafter Trichina.
Regarding claim 4, the combination of Higgins teaches all the features with respect to claim 1 as outlined above. The combination of Higgins further teaches the SSD of claim 1, wherein the controller determines the access frequency of the data by: determining that the access frequency is high in response to determining that a number of the read errors is low (Higgins, [0110], if the bit error rates for the particular data are lower than bit error rates for other data (e.g., neighboring data), then a high past read frequency is presumed); and determining that the access frequency is low in response to determining that the number of the read errors is high.
The combination of Higgins does not explicitly teach determining that the access frequency is low in response to determining that the number of the read errors is high, as claimed.
However, the combination of Higgins in view of Trichina teaches determining that the access frequency is low in response to determining that the number of the read errors is high (Trichina, [0053], Relatively unused or " cold" files can be copied during reclamation (e.g., garbage collection) scans of the memory component 102 into "low quality" erase blocks of the memory array 104 (e.g. … and/or erase blocks that have a predetermined number of data errors associated therewith; [0084], Allocating data that will tend to be used more often and more immediately to more physically sound areas of the memory structure can conserve those areas that have seen greater usage).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Trichina to associate less frequently accessed erase blocks with low quality memory. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Trichina because it improves efficiency and reliability of the storage system disclosed in the combination of Higgins by extending the life of memory devices (Trichina, [0084]).
Claims 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins and Kong as applied to claims 1 and 19 respectively above, and further in view of Ryu (US 2020/0218653), hereinafter Ryu.
Regarding claims 9 and 20, taking claim 9 as exemplary, the combination of Higgins teaches all the features with respect to claim 1 as outlined above. The combination of Higgins does not explicitly teach the SSD of claim 1, wherein the controller: writes the data to the non-volatile memory storage by writing first data to a first location on the non-volatile memory storage; determines that the first data is frequently accessed based on a first frequency by which the first data is accessed; and in response to determining that the first data is frequently accessed, relocating the first data to a second location on the non-volatile memory storage, the second location being in a first region of the non-volatile memory storage allocated to store data that is frequently accessed, as claimed.
However, the combination of Higgins in view of Ryu teaches the SSD of claim 1, wherein the controller: writes the data to the non-volatile memory storage by writing first data to a first location on the non-volatile memory storage (Ryu, [0063], data stored in the data storage area of the nonvolatile memory apparatus 100);
determines that the first data is frequently accessed based on a first frequency by which the first data is accessed; and in response to determining that the first data is frequently accessed, relocating the first data to a second location on the non-volatile memory storage, the second location being in a first region of the non-volatile memory storage allocated to store data that is frequently accessed (Ryu, [0065], the data storage device 10 may move the data such that hot data having update frequency equal to or more than the preset threshold update frequency and data having update frequency equal to or less than the preset threshold update frequency are separately stored).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Ryu to relocate data to a hot region when the data is determined to be frequently accessed. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Ryu because it improves efficiency of the system disclosed in the combination of Higgins by performing garbage collection based on update frequency of data, which extends lifetime of data storage devices (Ryu, [0009], [0057]).
Claim 20 is similar limitations as claim 9 and is rejected for the similar reasons.
Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins, Kong, and Ryu as applied to claim 9 above, and further in view of Mataya et al. (US 2012/0239990), hereinafter Mataya.
Regarding claim 10, the combination of Higgins teaches all the features with respect to claim 9 as outlined above. The combination of Higgins further teaches the SSD of claim 9, wherein the non-volatile memory storage comprises one or more NAND flash memory devices having blocks (Higgins, [0035], storage medium 132 is NAND-type flash memory; [0038], Memory devices (e.g., NVM 134-1, NVM 134-2, etc.) of storage medium 132 include addressable and individually selectable blocks), each of the blocks comprising multiple pages (Higgins, [0038], each block is further divided into a plurality of pages);
the first location is a first page located outside of the first region (Ryu, [0065], Note - data is written in a block outside of the hot region originally, which is the reason why the data needs to be moved to the hot region later);
the first location is identified by a first physical address;
the second location is a second page located inside of the first region (Ryu, [0065]);
the second location is identified by a second physical address different from the first physical address; and
the first region comprises one or more of the blocks (Ryu, [0047], the data storage areas in the nonvolatile memory apparatus 100 may refer to the die, the plane, the super block).
The combination of Higgins does not explicitly teach the first location is identified by a first physical address and the second location is identified by a second physical address different from the first physical address, as claimed.
However, the combination of Higgins with Mataya teaches the first location is identified by a first physical address; the second location is identified by a second physical address different from the first physical address (Mataya, [0019], Each of the storage blocks is further divided into multiple data segments or pages addressable by controller 20 using a physical page address or offset from a physical block address of the storage block containing the referenced page).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Mataya to identify memory pages using physical addresses. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Mataya because it improves efficiency of the system disclosed in the combination of Higgins by accessing data stored in memory pages using physical page addresses (Mataya, [0019]).
Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins, Kong, and Ryu as applied to claim 9 above, and further in view of Fisher et al. (US 2017/0003880), hereinafter Fisher.
Regarding claim 11, the combination of Higgins teaches all the features with respect to claim 9 as outlined above. The combination of Higgins does not explicitly teach the SSD of claim 9, wherein the first data corresponds to a first Logical Block Address (LBA); and wherein the controller: receives update data and the first LBA from a host; and relocates the first data to the second location by writing the update data to the second location, as claimed.
However, the combination of Higgins in view of Fisher teaches the SSD of claim 9, wherein the first data corresponds to a first Logical Block Address (LBA) (Fisher, [0030], an IOP received by flash controller 140 from a host device, such as a processor system 102, contains the logical block address (LBA) at which the data is to be accessed (read or written)); and
wherein the controller: receives update data and the first LBA from a host (Fisher, [0047], In response to a write IOP received from a host, such as a processor system 102, a data placement function 910 of flash controller 140 determines by reference to LPT table 900 whether the target LBA(s) indicated in the write request is/are currently mapped to physical memory page(s) in NAND flash memory system 150); and
relocates the first data to the second location by writing the update data to the second location (Ryu, [0065]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Fisher to receive a write request from a host with LBA identifying locations to store write data. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Fisher because it improves efficiency and usability of the storage system disclosed in the combination of Higgins by allowing host to access the storage system using logical block addresses (Fisher, [0030]).
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins and Kong as applied to claim 1 above, and further in view of Fitzpatrick et al. (US 2013/0061019), hereinafter Fitzpatrick.
Regarding claim 12, the combination of Higgins teaches all the features with respect to claim 1 as outlined above. The combination of Higgins does not explicitly teach the SSD of claim 1, wherein the controller: writes the data to the non-volatile memory storage by writing second data to a third location on the non-volatile memory storage; determines that the second data is infrequently accessed based on a second frequency by which the second data is accessed; and in response to determining that the second data is infrequently accessed, relocates the second data to a fourth location on the non-volatile memory storage, the fourth location being in a second region of the non-volatile memory storage allocated to store data that is infrequently accessed, as claimed.
However, the combination of Higgins in view of Fitzpatrick teaches the SSD of claim 1, wherein the controller: writes the data to the non-volatile memory storage by writing second data to a third location on the non-volatile memory storage (Fitzpatrick, [0062], the logical addresses 302 are written by the host system 108);
determines that the second data is infrequently accessed based on a second frequency by which the second data is accessed; and in response to determining that the second data is infrequently accessed, relocates the second data to a fourth location on the non-volatile memory storage, the fourth location being in a second region of the non-volatile memory storage allocated to store data that is infrequently accessed (Fitzpatrick, [0062], Since cold data is not written by the host system 108 very often, the cold data or the logical addresses 302 can be moved to the less-written subdrive 312; [0027], The memory sub-system 102 can include a solid-state disk drive (SSD).).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Fitzpatrick to move cold data to a less frequently accessed storage area in a SSD. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Fitzpatrick because it improves efficiency of the system disclosed in the combination of Higgins by reducing write amplification as hot data can be recycled less often (Fitzpatrick, [0064]).
Claim 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins, Kong, and Fitzpatric as applied to claim 12 above, and further in view of Mataya et al. (US 2012/0239990), hereinafter Mataya.
Regarding claim 13, the combination of Higgins teaches all the features with respect to claim 12 as outlined above. The combination of Higgins further teaches the SSD of claim 12, wherein the non-volatile memory storage comprises one or more NAND flash memory devices having blocks (Higgins, [0035], storage medium 132 is NAND-type flash memory; [0038], Memory devices (e.g., NVM 134-1, NVM 134-2, etc.) of storage medium 132 include addressable and individually selectable blocks), each of the blocks comprising multiple pages (Higgins, [0038], each block is further divided into a plurality of pages);
the third location is a third page located outside of the second region (Fitzpatric, [0062], Note - data is written in a block outside of the cold region originally, which is the reason why the data needs to be moved to the cold region later);
the third location is identified by a third physical address;
the fourth location is a fourth page located inside of the second region (Fitzpatrick, [0062]);
the fourth location is identified by a fourth physical address different from the third physical address; and
the second region comprises one or more of the blocks (Fitzpatrick, [0095], [0099], [0128]).
The combination of Higgins does not explicitly teach the third location is identified by a third physical address and the fourth location is identified by a fourth physical address different from the third physical address, as claimed.
However, the combination of Higgins in view of Mataya teaches third location is identified by a third physical address and the fourth location is identified by a fourth physical address different from the third physical address (Mataya, [0019], Each of the storage blocks is further divided into multiple data segments or pages addressable by controller 20 using a physical page address or offset from a physical block address of the storage block containing the referenced page).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Mataya to identify memory pages using physical addresses. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Mataya because it improves efficiency of the system disclosed in the combination of Higgins by accessing data stored in memory pages using physical page addresses (Mataya, [0019]).
Claim 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins, Kong, and Fitzpatric as applied to claim 12 above, and further in view of Fisher et al. (US 2017/0003880), hereinafter Fisher.
Regarding claim 14, the combination of Higgins teaches all the features with respect to claim 12 as outlined above. The combination of Higgins does not explicitly teach the SSD of claim 12, wherein the second data corresponds to a second Logical Block Address (LBA); wherein the controller: receives update data and the second LBA from a host; and relocates the second data to the fourth location by writing the update data to the fourth location, as claimed.
However, the combination of Higgins in view of Fisher teaches the SSD of claim 12, wherein the second data corresponds to a second Logical Block Address (LBA) (Fisher, [0030], an IOP received by flash controller 140 from a host device, such as a processor system 102, contains the logical block address (LBA) at which the data is to be accessed (read or written));
wherein the controller: receives update data and the second LBA from a host (Fisher, [0047], In response to a write IOP received from a host, such as a processor system 102, a data placement function 910 of flash controller 140 determines by reference to LPT table 900 whether the target LBA(s) indicated in the write request is/are currently mapped to physical memory page(s) in NAND flash memory system 150); and
relocates the second data to the fourth location by writing the update data to the fourth location (Fitzpatrick, [0062]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Fisher to receive a write request from a host with LBA identifying locations to store write data. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Fisher because it improves efficiency and usability of the storage system disclosed in the combination of Higgins by allowing host to access the storage system using logical block addresses (Fisher, [0030]).
Claim 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins and Kong as applied to claim 1 above, and further in view of Maharana et al. (US 2019/0243552), hereinafter Maharana.
Regarding claim 15, the combination of Higgins teaches all the features with respect to claim 1 as outlined above. The combination of Higgins does not explicitly teach the SSD of claim 1, wherein the non-volatile memory storage is partitioned into the plurality of regions by deep learning based on the access frequency, as claimed.
However, the combination of Higgins in view of Maharana teaches the SSD of claim 1, wherein the non-volatile memory storage is partitioned into the plurality of regions by deep learning based on the access frequency (Maharana, [0049]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Maharana to partition memory tiers and carry out data movements using an artificial neural network system. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Maharana because it improves efficiency and performance of the system disclosed in the combination of Higgins by applying artificial intelligence such as deep learning in storage management (Maharana, [0023]).
Claim 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins and Kong as applied to claim 1 above, and further in view of Barndt et al. (US 2018/0190362), hereinafter Barndt and Lin (US 2020/0142835), hereinafter Lin.
Regarding claim 16, the combination of Higgins teaches all the features with respect to claim 1 as outlined above. The combination of Higgins does not explicitly teach the SSD of claim 1, wherein the controller further determines an average expected level of errors based on the number of invalid pages per block and the read disturb counter, wherein the access frequency is determined based on a Bit Error Rate (BER), the average expected level of errors, and an error threshold, as claimed.
However, the combination of Higgins in view of Barndt teaches the SSD of claim 1, wherein the controller further determines an average expected level of errors based on the number of invalid pages per block and the read disturb counter, wherein the access frequency is determined based on a Bit Error Rate (BER), the average expected level of errors, and an error threshold (Higgins, [0110], if the bit error rates for the particular data are lower than bit error rates for other data (e.g., neighboring data), then a high past read frequency is presumed, and a high future read frequency is predicted; Barndt, [0039], first error level or error measure of a first page in a block of the NVM that occur over a predetermined number of read accesses … determining a second error measure or error level of at least one adjacent page … over the predetermined number of read accesses; [0040], determining whether the second error level is above a first predetermined threshold as shown at block 506; [0041], comparing the first error level to the second error level when the second error level is above the first predetermined threshold to determine whether the second error level is greater than the first error level by a predefined factor as shown in block 508 … determination of whether the amount of errors in a victim page are sufficiently high enough in comparison to the adjacent aggressor page to warrant a determination of a Read Disturb situation occurring as illustrated in block 510; [0026];).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Barndt to determine if a second error level is greater than a first error level by a predetermined amount. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Barndt because it improves efficiency of the storage system disclosed in Higgins by implementing preventative measures when read disturb errors are detected, which reduces write amplification of the storage system (Barndt, [0016]).
The combination of Higgins does not explicitly teach an average expected level of errors is based on the number of invalid pages per block, as claimed.
However, the combination of Higgins in view of Lin teaches an average expected level of errors is based on the number of invalid pages per block (Lin, [0029]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Lin to determine number of error bits based on number of valid/invalid pages. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Lin because it improves efficiency of the system disclosed in the combination of Higgins by selecting appropriated source blocks for garbage collection operations (Lin, [0029]).
Claim 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins and Kong as applied to claim 1 above, and further in view of Tai et al. (US2018/0188984), hereinafter Tai.
Regarding claim 21, the combination of Higgins teaches all the features with respect to claim 1 as outlined above. The combination of Higgins does not explicitly teach the SSD of claim 1, wherein data stored in pages exhibiting a combination of a high BER and in blocks with a low read disturb counter are determined by the controller to have a low access frequency, as claimed.
However, the combination of Higgins in view of Tai teaches the SSD of claim 1, wherein data stored in pages exhibiting a combination of a high BER and in blocks with a low read disturb counter are determined by the controller to have a low access frequency (Higgins, [0111], if data neighboring the particular data has had a high amount of read disturbs, then the past read frequency for the particular data is presumed to be high, and the future read frequency for the particular data is predicted to be high (Note – thus low read disturbs corresponds to low read frequency); Tai, [0023], In some cases, a few blocks may each return a high bit error rate even though each block has not suffered from a read disturb or a data retention error. The high bit error rate may be due to one or more cell imperfections during the manufacturing process. These types of memory blocks will likely always return a high bit error rate, no matter what).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Tai to determine read frequency of a particular data to be low when BER of the particular data is high and read disturb of the particular data is low. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Tai because it improves efficiency of the storage system disclosed in the combination of Higgins by accurately determining wear level of memory cells in nonvolatile memory devices in order to properly manage lifespan of the memory devices.
Claim 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Higgins and Kong as applied to claim 1 above, and further in view of Muchherla et al. (US2020/0133585), hereinafter Muchherla.
Regarding claim 22, the combination of Higgins teaches all the features with respect to claim 1 as outlined above. The combination of Higgins does not explicitly teach the SSD of claim 1, wherein data stored in pages exhibiting a combination of a high BER and in blocks with a high read disturb counter are determined by the controller to have a high access frequency, as claimed.
However, the combination of Higgins in view of Muchherla teaches the SSD of claim 1, wherein data stored in pages exhibiting a combination of a high BER and in blocks with a high read disturb counter are determined by the controller to have a high access frequency (Muchherla, [0056], Higgins, [0111]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Higgins to incorporate teachings of Muchherla to determine read frequency of a particular data to be high when BER of the particular data is high and read disturb of the particular data is also high. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Higgins with Muchherla because it improves efficiency of the storage system disclosed in the combination of Higgins by accurately determining wear level of memory cells in nonvolatile memory devices in order to properly manage lifespan of the memory devices.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NANCI N WONG/Primary Examiner, Art Unit 2136