DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to communication received on 03/12/2026. Claims 2 -21 are pending and stand as previously presented.
The Examiner recommends filing a written authorization for Internet communication in response to the present action. Doing so permits the USPTO to communicate with Applicant using Internet email to schedule interviews or discuss other aspects of the application. Without a written authorization in place, the USPTO cannot respond to Internet correspondence received from Applicant. The preferred method of providing authorization is by filing form PTO/SB/439, available at: https://www.uspto.gov/patent/forms/forms. See MPEP § 502.03 for other methods of providing written authorization.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of US Patent No. 11,575,495. Although the claims at issue are not identical, they are not patentably distinct from each other because claims of the instant application recite a broader set of limitations as compared to US 11,575,495. US 11,575,495 teach all the limitations of the instant application, see table below:
18/892,720
US 11,689,440
2. A network device configured to communicate via a communication link, the network device comprising: a memory; and a processor coupled to the memory, the processor configured to:
perform multiple timestamping methods, the multiple timestamping methods including: i) a one-step timestamping method, and ii) a two-step timestamping method,
receive, from a communication interface separate from the communication link, i) a first packet to be transmitted by the processor via the communication link, and ii) information that indicates a particular timestamping method to be used by the processor for communicating timing information corresponding to transmission of the first packet by the processor via the communication link to a receiving device, wherein the particular timestamping method is selected from the multiple timestamping methods, and
determine the particular timestamping method to be performed by the processor in connection with transmitting the first packet based on analyzing the information that indicates the particular timestamping method;
wherein the processor includes a timestamping engine configured to: determine timing information corresponding to the transmission of the first packet via the communication link to the receiving device using a first clock circuit,
in response to the processor determining that the particular timestamping method is the one-step method, embed the timing information in a first field of the first packet that is different than a second field of the packet having a timestamp that was determined using a second clock circuit that is different than the first clock circuit, the timestamp determined using the second clock circuit corresponding to transmission of the first packet by the processor via the communication link, and
in response to the processor determining that the timestamping method is the two- step method, store the timing information determined using the first clock circuit in the memory for subsequent inclusion in a second packet that is to be transmitted by the processor via the communication link after transmitting the first packet;
wherein the processor is further configured to transmit the first packet via the communication link, the first packet as transmitted having, when the timestamping method is the one-step method, i) the timestamp determined using the second clock circuit and ii) the timing information determined using the first clock circuit.
1. A network device, comprising: a network interface configured to transmit packets via a network link that is external to the network device;
timestamp circuitry configured to modify a packet that is to be transmitted by the network interface by embedding a future timestamp in the packet to generate a timestamped packet that is formatted for transmission with the embedded future timestamp via the network link that is external to the network device, the future timestamp associated with a transmit time at which the timestamped packet is to be transmitted by the network interface, the transmit time occurring after the timestamp circuitry embeds the future timestamp in the packet,
the timestamp circuitry further configured to generate timing information that is outside of the timestamped packet and that includes the transmit time; one or more circuitry stages configured to i) receive the timestamped packet, and ii) synchronize passage of the timestamped packet through the one or more circuitry stages with passage of the timing information through the one or more circuitry stages; and time gating circuitry that includes, or is coupled to, a clock circuit that maintains a first time clock, the time gating circuitry configured to i) receive the timestamped packet and the timing information from the one or more circuitry stages, ii) determine when a current time indicated by the clock circuit reaches the transmit time that is included in the timing information, iii) hold the timestamped packet from proceeding to the network interface prior to the current time reaching the transmit time, and iv) release the timestamped packet, embedded with the future timestamp that is associated with the transmit time, in response to the current time reaching the transmit time so that the timestamped packet, embedded with the future timestamp that is associated with the transmit time, is transmitted by the network interface at the transmit time via the network link that is external to the network device, the future timestamp being embedded in the packet to indicate to a receiving device that receives the packet via the network link a time at which the timestamped packet was transmitted by the network device to enable the receiving device to synchronize a second time clock of the receiving device to the first time clock.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2, 5-9 and 12, and 15-19 are rejected under 35 U.S.C. 102a1,a2 as being anticipated by Zemach US 2020/0252320.
Regarding claim 2 and 12, Zemach teaches a network device configured to communicate via a communication link, the network device comprising: a memory; and a processor coupled to the memory, the processor configured to
[0021] The network device 100 includes a memory 104 to store packets that are to be transmitted by the network device 100. For example, the memory 104 may act as a transmit queue for storing packets until a communication link is available for transmitting the packets. In various embodiments, the memory 104 comprises a random access memory (RAM) or another suitable type of memory device.
:perform multiple timestamping methods, the multiple timestamping methods including: i) a one-step timestamping method, and ii) a two-step timestamping method(processing stage of PTP system can embed timestamp in packet or generate and send timestamp information separate from packet, ¶s 26, 27),
[0026] The plurality of processing stages 120 includes time stamping circuitry 124 that is configured to modify a packet to embed a timestamp in the packet. The timestamp embedded in the packet by the time stamping circuitry 124 corresponds to a future time at which the packet is to be transmitted via the network interface 112 (sometimes referred to herein as a “transmit time” for a packet). For example, the future time (or transmit time) corresponds to a time offset added to a current time at which the packet is received at the time stamping circuitry 124, where the time offset corresponds to a maximum latency of one or more processing stages in the plurality of processing stages 120 that are to process the packet after the time stamping circuitry 124.
[0027] The time stamping circuitry 124 is also configured to generate timing information, separate from the timestamp in the packet, that indicates the transmit time, according to an embodiment. As will be discussed below, the timing information (separate from the timestamp in the packet) is for use by time gating circuitry 128 in the plurality of processing stages 120. In particular, the time gating circuitry 128 uses the timing information to determine when a packet is to be released to the network interface 112, as will be described below.
receive, from a communication interface separate from the communication link, i) a first packet to be transmitted by the processor via the communication link, and ii) information that indicates a particular timestamping method to be used by the processor for communicating timing information corresponding to transmission of the first packet by the processor via the communication link to a receiving device, wherein the particular timestamping method is selected from the multiple timestamping methods, and(packet is received with control information that indicates timestamp embedded packet or not embedding timestamp gating of packet, ¶s 63, 64)
[0063] In some embodiments, the time stamping circuitry 200 does not timestamp every packet that the time stamping circuitry 200 receives, e.g., the time stamping circuitry 200 selectively timestamps packets. For example, the packet generator/packet processor 108 determines which packets are to be timestamped and informs the time stamping circuitry 200 of which packets are to be timestamped, according to an embodiment. Thus, in some embodiments, the time stamping circuitry 200 includes control circuitry (not shown) that receives timestamping control information corresponding to a packet and that indicates whether the packet is to be timestamped, and the control circuitry controls the time stamping circuitry 200 to selectively add a timestamp to the packet based on the timestamping control information. For example, when the timestamping control information indicates that the packet is to be timestamped, the control circuitry controls the time stamping circuitry 200 to include a timestamp in the packet as discussed above; on the other hand, when the timestamping control information indicates that the packet is not to be timestamped, the control circuitry controls the time stamping circuitry 200 to not include a timestamp in the packet.
[0064] In an embodiment, the time stamping circuitry 200 receives the timestamping control information (e.g., from the packet generator/packet processor 108) separate from the packet but corresponding to the packet. In another embodiment, the timestamping control information (e.g., from the packet generator/packet processor 108) is appended to the packet, e.g., in a tag appended to the packet. In an embodiment in which the packet received by the tune stamping circuitry 200 includes a tag that indicates the packet is to be timestamped, the time stamping circuitry 200 modifies the tag to include the transmit time in the tag. In another embodiment in which the packet received by the time stamping circuitry 200 includes a tag that indicates the packet is to be timestamped, the time stamping circuitry 200 adds an additional tag to the packet, the additional tag including the transmit time. In another embodiment in which the packet received by the time stamping circuitry 200 includes a tag that indicates the packet is to be timestamped, the time stamping circuitry 200 removes the tag and adds a new tag to the packet, the new tag including the transmit time.
determine the particular timestamping method to be performed by the processor in connection with transmitting the first packet based on analyzing the information that indicates the particular timestamping method( control information indicates which method is to be perform timestamped packet or timing information separate from packet, ¶s 63, 64)
wherein the processor includes a timestamping engine configured to: determine timing information corresponding to the transmission of the first packet via the communication link to the receiving device using a first clock circuit(clock circuit provides time information for transmit time calculation, ¶59)
[0059] The timestamping circuitry 200 is coupled to, or includes, a clock circuit 204, and receives a current time value generated by the clock circuit 204. The timestamping circuitry 200 also includes an adder circuit 208 that is configured to add a time offset to the current time from the clock circuit 204 to generate a future time value corresponding to a time at which the packet is to be transmitted (e.g., a transmit time). The time offset corresponds to a maximum latency of one or more processing stages in a plurality of processing stages that are to process the packet after the time stamping circuitry 200, In embodiments in which the time stamping circuitry 200 is used in the network device 100, the time offset corresponds to a maximum latency of the one or more processing stages 140. In an embodiment in which authentication circuitry is to generate authentication information for the packet after the time stamping circuitry 200 has added a timestamp to the packet, the time offset accounts for at least a maximum latency of the authentication circuitry. In an embodiment in which encryption circuitry is to encrypt contents of the packet after the time stamping circuitry 200 has added a timestamp to the packet, the time offset accounts for at least a maximum latency of the encryption circuitry.
in response to the processor determining that the particular timestamping method is the one-step method, embed the timing information in a first field of the first packet that is different than a second field of the packet having a timestamp that was determined using a second clock circuit that is different than the first clock circuit, the timestamp determined using the second clock circuit corresponding to transmission of the first packet by the processor via the communication link, and(timestamp is embedded to indicate a transit time where such timestamping is performed by a local clock of each processing stage using time(current time) provided by a source clock(master clock), timing control in a separate field to indicate one or two step ,¶s 4,5,26)
[0004] The Precision Time Protocol (PTP) defines a scheme for distributing an accurate time across a communication network. In PTP, a general master (GM) maintains an accurate source time clock. Additionally, nodes in the network exchange timestamped packets to determine transmit latencies between pairs of nodes. In particular, a transmit node typically adds a timestamp to a packet immediately prior to transmitting the packet, where the timestamp indicates a transmit time of the packet. A node that receives the packet then uses the timestamp in the packet and a receive time of the packet to measure a transmit latency between the transmit node and the receive node.
[0005] With PTP, a current value of the source time clock of the GM is distributed through the communication network so that nodes can synchronize their local clocks, and each node adjusts its local clock to account for a transmit latency associated with a path through the network by which the value of the source time clock was received.
[0026] The plurality of processing stages 120 includes time stamping circuitry 124 that is configured to modify a packet to embed a timestamp in the packet. The timestamp embedded in the packet by the time stamping circuitry 124 corresponds to a future time at which the packet is to be transmitted via the network interface 112 (sometimes referred to herein as a “transmit time” for a packet). For example, the future time (or transmit time) corresponds to a time offset added to a current time at which the packet is received at the time stamping circuitry 124, where the time offset corresponds to a maximum latency of one or more processing stages in the plurality of processing stages 120 that are to process the packet after the time stamping circuitry 124.
in response to the processor determining that the timestamping method is the two- step method, store the timing information determined using the first clock circuit in the memory for subsequent inclusion in a second packet that is to be transmitted by the processor via the communication link after transmitting the first packet(in two step method timing information sent in a first output second output that sends packet with timestamp, ¶28)
wherein the processor is further configured to transmit the first packet via the communication link, the first packet as transmitted having, when the timestamping method is the one-step method, i) the timestamp determined using the second clock circuit and ii) the timing information determined using the first clock circuit(if one step is indicated from timing control information transmit timestamp include in packet, timestamp calculated using local clock and master/source clock , ¶50).
[0050] In some situations, the position of the timestamp in the packet may vary from packet to packet because, for example, of variable length fields in packet headers, different packets having different/additional headers, etc. Thus, in some embodiments, the time stamping circuitry 168 provides to the time gating circuitry 172 offset information (not shown) that indicates a position of the timestamp within the packet; and the time gating circuitry 172 uses the offset information to retrieve the timestamp within the packet. In an embodiment, the time stamping circuitry 168 outputs the offset information separately from the packet, e.g., via a first output of the time stamping circuitry 168, which is separate from a second output of the time stamping circuitry 168 that outputs the packet that includes the timestamp. In another embodiment, the timing information is appended to the packet, e.g., in a tag appended to the packet, the tag being removed from the packet prior to transmitting the packet via the network interface 112 so that the tag is not transmitted via the network interface 112.
Regarding claims 5 and 15, Zemach teaches wherein the first packet, as received by the processor, includes the information that indicates the timestamping method(time stamping control information ¶29).
[0029] In some embodiments, the time stamping circuitry 124 does not timestamp every packet that is processed by the plurality of processing stages 120, e.g., the time stamping circuitry 124 selectively timestamps packets. For example, the packet generator/packet processor 108 determines which packets are to he timestamped and informs the time stamping circuitry 124 of which packets are to be timestamped, according to an embodiment. In an embodiment, the time stamping circuitry 124 receives timestamping control information (e.g., from the packet generator/packet processor 108) separate from the packet but corresponding to the packet, the timestamping control information indicating whether the time stamping circuitry 124 is to timestamp the packet. In another embodiment, the timestamping control information (e.g., from the packet generator/packet processor 108) is appended to the packet, e.g., in a tag appended to the packet. In an embodiment in which the packet received by the time stamping circuitry 124 includes a tag that indicates the packet is to be timestamped, the time stamping circuitry 124 modifies the tag to include the transmit time in the tag, and separate from the timestamp in the packet. In another embodiment in which the packet received by the time stamping circuitry 124 includes a tag that indicates the packet is to be timestamped, the time stamping circuitry 124 adds an additional tag to the packet, the additional tag including the transmit time. In another embodiment in which the packet received by the time stamping circuitry 124 includes a tag that indicates the packet is to be timestamped, the time stamping circuitry 124 removes the tag and adds a new tag to the packet, the new tag including the transmit time.
Regarding claim 6 and 16, Zemach teaches wherein: the first packet, as received by the processor, includes a control header having the information that indicates the timestamping method; and the processor is configured to determine the particular timestamping method to be performed by the processor at least based on analyzing the information that indicates the timestamping method within the control header(header of packet used to indicate and hold timing control information that indicates embedded or separate timing information mode, ¶50) .
[0050] In some situations, the position of the timestamp in the packet may vary from packet to packet because, for example, of variable length fields in packet headers, different packets having different/additional headers, etc. Thus, in some embodiments, the time stamping circuitry 168 provides to the time gating circuitry 172 offset information (not shown) that indicates a position of the timestamp within the packet; and the time gating circuitry 172 uses the offset information to retrieve the timestamp within the packet. In an embodiment, the time stamping circuitry 168 outputs the offset information separately from the packet, e.g., via a first output of the time stamping circuitry 168, which is separate from a second output of the time stamping circuitry 168 that outputs the packet that includes the timestamp. In another embodiment, the timing information is appended to the packet, e.g., in a tag appended to the packet, the tag being removed from the packet prior to transmitting the packet via the network interface 112 so that the tag is not transmitted via the network interface 112.
Regarding claims 7 and 17, Zemach teaches header with field but does not teach wherein: the control header, as received by the processor, includes an extension field having the information that indicates the timestamping method; and the processor is configured to determine the particular timestamping method to be performed by the processor at least based on analyzing the information that indicates the timestamping method within the extension field of the control header.
[0040] In an embodiment, a PHY device (e.g., the PHY device 108-1) is configured to generate the control header 300 for a received timing packet, and to insert the control header at a predetermined location within the timing packet. For example, the PHY device 108-1 is configured to replace, with the control header 300, a preamble at a beginning of the timing packet. The PHY device 108-1 is configured to include, in the extension field 308 of the control header 300, a timestamp corresponding to a receipt time of the packet. The PHY device 108-1 is also configured to set the value of the extension field type field 306 to indicate that the extension field 308 includes a timestamp. In an embodiment, the timestamp included in the extension field 308 occupies 32 bits of the extension field 308. In another embodiment, the timestamp included in the extension field 308 occupies a number of bits different from 32 bits (e.g., 16 bits, 48 bits, 64 bits or any other suitable number of bits). In an embodiment, the PHY device 108-1 is configured to include the timestamp as a 32-bit unsigned value, in nanoseconds, of the PHY clock 113 at the time of receipt of the packet. In another embodiment, the PHY device 108-1 is configured to include the timestamp in another suitable format. For example, in an embodiment in which the PHY device 108-1 is configured to utilize an IEEE time application interface (TAI) format, the PHY device 108-1 is configured to convert a nanosecond value of the PHY clock 113 at the time of receipt of the packet into a 2-bit seconds value followed by a 29-bit nanoseconds value, which includes a two's compliment of the nanosecond value, in an embodiment.
It would have been obvious to a person of ordinary skill in the art before the effective filing of the invention to modify Zemach with a use of extension fields in packet headers as taught by Dror.. The reason for this modification would be to improve time synchronization between hops in packet networks providing portions of packet headers to indicate packet handling/processing to be applied to the packet.
Regarding claims 8 and 18, Zemach teaches wherein the first packet, as received by the processor, encapsulates, with one or more communication protocol headers, a timing message(header are with various field are added to packet(ie. encapsulated) such information making the packet a time synchronization I.e. timing message), ¶s42 50).
[0042] In some embodiments, the timing information generated by the timestamping circuitry 124 is provided to the time gating circuitry 128 via the one or more processing stages 140. For example, the processing stage(s) 140 include respective circuitry for forwarding the timing information to a next processing stage in the plurality of processing stages 120 so that the timing information is synchronized with the future timestamped packet. In some embodiments, the processing stage(s) 140 include respective registers, buffers, etc., for temporarily storing the timing information.
[0050] In some situations, the position of the timestamp in the packet may vary from packet to packet because, for example, of variable length fields in packet headers, different packets having different/additional headers, etc. Thus, in some embodiments, the time stamping circuitry 168 provides to the time gating circuitry 172 offset information (not shown) that indicates a position of the timestamp within the packet; and the time gating circuitry 172 uses the offset information to retrieve the timestamp within the packet. In an embodiment, the time stamping circuitry 168 outputs the offset information separately from the packet, e.g., via a first output of the time stamping circuitry 168, which is separate from a second output of the time stamping circuitry 168 that outputs the packet that includes the timestamp. In another embodiment, the timing information is appended to the packet, e.g., in a tag appended to the packet, the tag being removed from the packet prior to transmitting the packet via the network interface 112 so that the tag is not transmitted via the network interface 112.
Regarding claims 9 and 19, Zemach teaches wherein the timing message comprises a Precision Time Protocol (PTP) message(timestamp packet for time synchronization to achieve precision time in PTP protocol, ¶4).
[0004] The Precision Time Protocol (PTP) defines a scheme for distributing an accurate time across a communication network. In PTP, a general master (GM) maintains an accurate source time clock. Additionally, nodes in the network exchange timestamped packets to determine transmit latencies between pairs of nodes. In particular, a transmit node typically adds a timestamp to a packet immediately prior to transmitting the packet, where the timestamp indicates a transmit time of the packet. A node that receives the packet then uses the timestamp in the packet and a receive time of the packet to measure a transmit latency between the transmit node and the receive node.
Claims 2-5 and 12-15 are rejected under 35 U.S.C. 102a1,a2 as being anticipated by Pauwels US 2017/0063481.
Regarding claim 2 and 12, Pauwels teaches a network device configured to communicate via a communication link, the network device comprising: a memory; and a processor coupled to the memory, the processor configured to
[0007] The object of the present invention is to provide a method and a device that allow for accurate clock synchronization even in case of asymmetric delays across sections between two or more nodes within a network. Moreover, the method and device should be simple to implement, require as little modifications to PTP as possible and work efficiently.
:perform multiple timestamping methods, the multiple timestamping methods including: i) a one-step timestamping method, and ii) a two-step timestamping method( timestamp embedded in the packet or timing information send in follow up packet, ¶41)
[0041] The master clock 25 is operable for transmitting time synchronization messages that contain a time stamp that specifies the transmission time of the message measured by the primary reference clock PRC. To this end, the master clock comprises a time stamping arrangement 27 that inserts the transmission time into a field of the synchronization message. In another embodiment, the timestamp is not included in the synchronization message but sent in a separate follow-up message transmitted after the synchronization message. Using a follow-up message allows using hardware that is capable to determine the timestamp for a message but cannot include it into this message. According to the PTP standard, time stamping is applied to PTP event messages. Besides the event messages, PTP uses general messages to which time stamping is not applied and that do typically not contain a timestamp.
receive, from a communication interface separate from the communication link, i) a first packet to be transmitted by the processor via the communication link, and ii) information that indicates a particular timestamping method to be used by the processor for communicating timing information corresponding to transmission of the first packet by the processor via the communication link to a receiving device, wherein the particular timestamping method is selected from the multiple timestamping methods, and(presence of timestamp in packet indicates one step, lack of timestep selects two-step i.e. follow up message contains timing info, ¶41)
[0041] The master clock 25 is operable for transmitting time synchronization messages that contain a time stamp that specifies the transmission time of the message measured by the primary reference clock PRC. To this end, the master clock comprises a time stamping arrangement 27 that inserts the transmission time into a field of the synchronization message. In another embodiment, the timestamp is not included in the synchronization message but sent in a separate follow-up message transmitted after the synchronization message. Using a follow-up message allows using hardware that is capable to determine the timestamp for a message but cannot include it into this message. According to the PTP standard, time stamping is applied to PTP event messages. Besides the event messages, PTP uses general messages to which time stamping is not applied and that do typically not contain a timestamp.
determine the particular timestamping method to be performed by the processor in connection with transmitting the first packet based on analyzing the information that indicates the particular timestamping method(presence of timestamp indicates one step and lack of timestamp indicates a follow up message method(i.e. two-step, ¶s41,42)
wherein the processor includes a timestamping engine configured to: determine timing information corresponding to the transmission of the first packet via the communication link to the receiving device using a first clock circuit(transmit time determined with respect to master clock signal, ¶42)
[0041] The master clock 25 is operable for transmitting time synchronization messages that contain a time stamp that specifies the transmission time of the message measured by the primary reference clock PRC. To this end, the master clock comprises a time stamping arrangement 27 that inserts the transmission time into a field of the synchronization message. In another embodiment, the timestamp is not included in the synchronization message but sent in a separate follow-up message transmitted after the synchronization message. Using a follow-up message allows using hardware that is capable to determine the timestamp for a message but cannot include it into this message. According to the PTP standard, time stamping is applied to PTP event messages. Besides the event messages, PTP uses general messages to which time stamping is not applied and that do typically not contain a timestamp.
[0042] As shown in FIG. 1, some nodes 21, 21b of the network 11 include a Transparent Clock (TC). A transparent clock is a correction mechanism specified in the PTP standard that allows for determining the accumulated residence time of synchronization messages within network nodes. To this end, a transparent clock TC measures the residence time of a synchronization message and adds the measured residence time to a correction value stored in a correction field of the message by means of a residence time correction arrangement 29. In case that the message traverses multiple transparent clocks TC, a correction value stored in the correction field of the message is augmented several times with the respective residence time; and when the message leaves the last transparent clock on its way to a destination node, its time correction field describes the accumulated residence time. The local wall clock 23 of a transparent clock TC may or may not be aligned in phase and time with the master wall clock 25.
in response to the processor determining that the particular timestamping method is the one-step method, embed the timing information in a first field of the first packet that is different than a second field of the packet having a timestamp that was determined using a second clock circuit that is different than the first clock circuit, the timestamp determined using the second clock circuit corresponding to transmission of the first packet by the processor via the communication link, and(timing information can be made using two separate field including arrival time and transmit time all with respect to local clock, ¶51)
[0051] Besides the original and modified correction field, FIG. 4 shows the arrival time TA. In the shown embodiment, the arrival time is represented in the same way as time stamps used in PTP event messages. That is, the arrival time comprises a 48 bits long seconds field s and a 32 bits long nanoseconds field us. Both fields are represented as unsigned integer values. In other embodiments a different representation of the arrival time TA is used. For example, the length of the fields of the arrival time TA may be modified. The resolution of the arrival time may be changed (using increments of multiple ns or a fraction of ns rather than using a resolution of one ns). Moreover, a single field may be used instead of two fields. Regardless of its exact implementation, the arrival time TA can be considered as a time stamp that is generated using the local clock 23 of the node 21 that executes the first method 33 and stored in a memory of this node 21.
in response to the processor determining that the timestamping method is the two- step method, store the timing information determined using the first clock circuit in the memory for subsequent inclusion in a second packet that is to be transmitted by the processor via the communication link after transmitting the first packet(if follow up message type is used timing information sent in follow up message to synch clocks of master to local clock, ¶41)
[0041] The master clock 25 is operable for transmitting time synchronization messages that contain a time stamp that specifies the transmission time of the message measured by the primary reference clock PRC. To this end, the master clock comprises a time stamping arrangement 27 that inserts the transmission time into a field of the synchronization message. In another embodiment, the timestamp is not included in the synchronization message but sent in a separate follow-up message transmitted after the synchronization message. Using a follow-up message allows using hardware that is capable to determine the timestamp for a message but cannot include it into this message. According to the PTP standard, time stamping is applied to PTP event messages. Besides the event messages, PTP uses general messages to which time stamping is not applied and that do typically not contain a timestamp
wherein the processor is further configured to transmit the first packet via the communication link, the first packet as transmitted having, when the timestamping method is the one-step method, i) the timestamp determined using the second clock circuit and ii) the timing information determined using the first clock circuit(packet with timestamp or without timestamp in a follow up message sent downstream from node to node to synch master clock to local clock , ¶47)
[0009] Because the method adjusts the residence time based on the offset time, which is calculated from a time of arrival, the modified clock synchronization message includes information about the arrival time. Thus, a receiving node that receives the forwarded modified clock synchronization message can determine the total residence time of the message within a forwarding arrangement including the transmitting node that executes the method, a receiving node and a transmission medium (e.g. electrical or optical transmission line) for transferring the message from the transmitting node to the receiving node. In other words, the forwarding arrangement provides a distributed transparent clock that includes the transmitting node, the transmission medium and the receiving node. The distributed transparent clock allows for precise clock synchronization even in case of asymmetric delays in the transmitting node, the transmission medium and/or the receiving node because the whole total residence time of the distributed transparent clock may be considered.
[0047] FIG. 3 shows a flowchart of a first method 33 for forwarding a clock synchronization message, e.g. a PTP event message, comprising a time correction field. The first method 73 may he executed by a node of the distributed transparent clock DTC that receives the clock synchronization message from outside of the distributed transparent clock. In the example shown in FIG. 2, downstream clock synchronization messages are received by the interface 31 of the access node. Thus, the first method 33 may be carried out on clock synchronization message received via the interface 31 of the access node 29. Upstream clock synchronization messages enter the respective distributed transparent clock DTC via an interface 31 of the ONT or the CPE. Accordingly, the ONT or the CPE may execute the first method 33 for clock synchronization messages received on one of their interfaces 31.
Regarding claims 3 and 13.Pauwels teachs wherein, when the timestamping method is the one-step method: the timestamp determined using the second clock circuit corresponds to an estimate of a time at which the first packet is transmitted by the processor via the communication link; and the timing information determined using the first clock circuit corresponds to a correction value that improves accuracy of the timestamp(correction field indicate adjustment with respect master clock , ¶s20, 40)
[0020] According to yet another embodiment of the present invention, a second method for forwarding a clock synchronization message is provided, the clock synchronisation message comprising a time correction field the method comprising determining a transmission time of a modified clock synchronization message to be forwarded; calculating a modified residence time from a value of the time correction field and from an offset time derived from the transmission time; modifying the clock synchronization message so that the clock synchronization message includes the modified residence time; and forwarding the modified clock synchronization message comprising the modified residence time. The value of the time correction field may describe a time value such as the modified residence time determined by the first method an embodiment, the second method may modify the clock synchronization message by replacing value stored in the time correction field with the calculated modified residence time.
[0040] Unlike the local wall clocks 23 of the individual network elements NE, the master wall clock 25 has direct access to a precise time base that may be provided by a primary reference clock PRC. The PRC provides a precise reference frequency source as well as a Time of Day (ToD) according to a predefined time scale (e.g. UTC, GPS time scale, etc.). In an embodiment, the primary reference clock PRC includes a Global Positioning System (GPS) receiver for receiving time information from the GPS.
Regarding claims 4 and 14, Pauwels teaches wherein: the processor comprises a physical layer (PHY) processor(physical layer protocol transceiver, ¶76).
[0075] Both methods 33, 45 may be implemented in software, hardware or any combination of software and hardware. In an embodiment at least the operations for replacing the correction field shown in FIGS. 4 and 6 are implemented at least partially in hardware. Using a hardware-supported implementation for replacing the correction field has a better accuracy than an implementation that is base on software only. For example, the methods 33, 45 may be implemented in a protocol entity of any node 21 of the network, in particular of the access node 29 (e.g. OLT or DSLAM or combined access node 29 shown in FIG. 2), the ONT on or the CPE. The protocol entity may be a Media Access Control (MAC) protocol entity (e.g. MAC controller) or a physical layer protocol entity (e.g. transceiver).
Regarding claims 5 and 15, Pauwels teaches wherein the first packet, as received by the processor, includes the information that indicates the timestamping method.
[0050] In FIG. 4—which illustrates the operations of step 41 in more detail the correction field is shown twice. The correction field corr shown on the top of FIG. 4 is the correction field of received clock synchronization message M while the correction field corr′ shown at the bottom of FIG. 4 is a modified correction field to be included into the clock synchronization message M′ to be forwarded to another node of the distributed transparent clock DTC. It should be noted that clock synchronization messages including such a modified correction field corr′ are communicated between nodes of the distributed transparent clock that use the forwarding methods 33, 45 described herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zemach as applied to claims 2 and 12 above, and further in view of Dror US 2021/0297230.
Regarding claims 3 and 13, Zemach teaches wherein, when the timestamping method is the one-step method: the timestamp determined using the second clock circuit corresponds to an estimate of a time at which the first packet is transmitted by the processor via the communication link(timestamp calculated is indication of transmission time for output time gating, ¶26)
[0026] The plurality of processing stages 120 includes time stamping circuitry 124 that is configured to modify a packet to embed a timestamp in the packet. The timestamp embedded in the packet by the time stamping circuitry 124 corresponds to a future time at which the packet is to be transmitted via the network interface 112 (sometimes referred to herein as a “transmit time” for a packet). For example, the future time (or transmit time) corresponds to a time offset added to a current time at which the packet is received at the time stamping circuitry 124, where the time offset corresponds to a maximum latency of one or more processing stages in the plurality of processing stages 120 that are to process the packet after the time stamping circuitry 124.
Zemach does not teach a correction value and thus does not teach the timing information determined using the first clock circuit corresponds to a correction value that improves accuracy of the timestamp. Dror in the same field of endeavor teaches a method and device for time synchronization for packet transmission control. Dror teaches the timing information determined using the first clock circuit corresponds to a correction value that improves accuracy of the timestamp(correction value used to indicate delay in device for adjusting time gating, ¶30).
[0030] Referring now FIGS. 1 and 2, in an embodiment in which the timing message 122 is generated by the host processor 116, such as in an embodiment in which the network device 100 is operating as an ordinary clock or a boundary clock device, the timing module 118 of the host processor 116 sets the timestamp field 208 of the timing message 122 to a current value of the host clock 120, in an embodiment. The timing module 118 also selectively generates a correction field value for the timing message 122, and sets the correction field 206 of the timing message 122 to the generated correction field value. In an embodiment, the timing module 118 generates the correction field value to be equal to the negative value of the nanosecond portion of the timestamp in the timestamp field 208 so that the nanosecond portion of the timestamp can be subsequently updated by a PHY device 108, based on the PHY clock 113, at a time of transmission of the timing packet 119 from the network device 100. In an embodiment, the timing module 118 also adds an egress pipeline delay to the correction field value, where the egress pipeline delay is a preconfigured value of static delay from a point which the PHY device 108 timestamps a timing packet to an egress pin of the PHY device 108 via which the timing packet is egressed from the PHY device 108. In an embodiment, of the timing message 122 includes a checksum trailer field such as the checksum trailer field 210, the timing module 118 is sets the checksum trailer field 210 of the timing packet 119 based on the values of the timestamp field 208 and the correction field 206, to maintain correctness of a checksum, such as a UDP checksum, in the timing packet 119.
It would have been obvious to a person of ordinary skill in the art before the effective filing of the invention to modify Zemach with a correction value in timing synchronization/gating control information indicated in a packet as taught by Dror. The reason for this modification would be to improve time synchronization between hops in packet networks.
Regarding claim 10, and 20, Zemach teaches wherein, when the timestamping method is the one-step method: the timing message includes a timestamp field that includes the timestamp that was set using the first clock circuit; and the processor is configured to(packet in one step includes future transmit time incorporated in packet , ¶s 26, 27),
[0026] The plurality of processing stages 120 includes time stamping circuitry 124 that is configured to modify a packet to embed a timestamp in the packet. The timestamp embedded in the packet by the time stamping circuitry 124 corresponds to a future time at which the packet is to be transmitted via the network interface 112 (sometimes referred to herein as a “transmit time” for a packet). For example, the future time (or transmit time) corresponds to a time offset added to a current time at which the packet is received at the time stamping circuitry 124, where the time offset corresponds to a maximum latency of one or more processing stages in the plurality of processing stages 120 that are to process the packet after the time stamping circuitry 124.
[0027] The time stamping circuitry 124 is also configured to generate timing information, separate from the timestamp in the packet, that indicates the transmit time, according to an embodiment. As will be discussed below, the timing information (separate from the timestamp in the packet) is for use by time gating circuitry 128 in the plurality of processing stages 120. In particular, the time gating circuitry 128 uses the timing information to determine when a packet is to be released to the network interface 112, as will be described below.
Zemach does not teach a correction value and thus does not teach determine the timing information further using a correction value in a correction field of the timing message as received via the communication interface separate from the communication link, the correction field being distinct from the timestamp field, and embed the timing information in the correction field of the timing message. Dror in the same field of endeavor as the invention teaches a correction value and thus does not teach determine the timing information further using a correction value in a correction field of the timing message as received via the communication interface separate from the communication link, the correction field being distinct from the timestamp field, and embed the timing information in the correction field of the timing message(correction value used to indicate delay in device for adjusting time gating, ¶30).
[0030] Referring now FIGS. 1 and 2, in an embodiment in which the timing message 122 is generated by the host processor 116, such as in an embodiment in which the network device 100 is operating as an ordinary clock or a boundary clock device, the timing module 118 of the host processor 116 sets the timestamp field 208 of the timing message 122 to a current value of the host clock 120, in an embodiment. The timing module 118 also selectively generates a correction field value for the timing message 122, and sets the correction field 206 of the timing message 122 to the generated correction field value. In an embodiment, the timing module 118 generates the correction field value to be equal to the negative value of the nanosecond portion of the timestamp in the timestamp field 208 so that the nanosecond portion of the timestamp can be subsequently updated by a PHY device 108, based on the PHY clock 113, at a time of transmission of the timing packet 119 from the network device 100. In an embodiment, the timing module 118 also adds an egress pipeline delay to the correction field value, where the egress pipeline delay is a preconfigured value of static delay from a point which the PHY device 108 timestamps a timing packet to an egress pin of the PHY device 108 via which the timing packet is egressed from the PHY device 108. In an embodiment, of the timing message 122 includes a checksum trailer field such as the checksum trailer field 210, the timing module 118 is sets the checksum trailer field 210 of the timing packet 119 based on the values of the timestamp field 208 and the correction field 206, to maintain correctness of a checksum, such as a UDP checksum, in the timing packet 119.
It would have been obvious to a person of ordinary skill in the art before the effective filing of the invention to modify Zemach with a correction value in timing synchronization/gating control information indicated in a packet as taught by Dror. The reason for this modification would be to improve time synchronization between hops in packet networks.
Regarding claims 11 and 21, Dror teaches wherein, when the timestamping method is the one-step method: the processor is configured to determine the timing information based on adding to the correction value an adjustment value determined using the first clock circuit(correction with respect master/host clock,¶25).
[0025] In an embodiment and/or scenario in which the network device 100 is operating as an ordinary clock device or a boundary clock device, the host processor 116 is configured to generate timing packets originating from the network device 100. In an embodiment, the network device 100 includes or implements a timing module 118 configured to generate timing packets for transmission from the network device 100. In an embodiment, the timing module 118 is configured to generate timing packets to include initial timing information indicative of transmission time of the timing packets. The initial timing information is determined based on a host clock 120 maintained by the host processor 116, in an embodiment. In an embodiment, the timing module 118 is configured to set a timestamp field in a timing packet generated by the timing module 118 to a current value of a host clock 120 maintained by the host processor 116. The timing module 118 is further configured to set a correction field in the timing packet to an initial correction value for compensating the current value of the host clock 120 for transmission delay expected to be experienced by the timing packet between the current time and the time that the timing packet is actually transmitted from the network device 100. The host processor is configured to transfer the timing packet to the MAC processor 114, The MAC processor 114 is configured to, in turn transfer, the timing packet to an appropriate PHY device 108 for transmission of the packet from a network port 104 of the network device 100.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zemach as applied to claim 2 and 12 above, and further in view of Rentschler US 2019/0386763.
Regarding claims 4 and 14, Zemach does not teach wherein: the processor comprises a physical layer (PHY) processor. Rentschler in the same field of endeavor as the invention teaches a system timestamping and time synchronization in networks requiring precision time control. Rentscher teaches wherein: the processor comprises a physical layer (PHY) processor.
[0015] The inventor of the embodiments of the present disclosure has found that a need exists to provide high-precision time synchronization in a packet-based network at minimum cost per node. In particular, a solution is needed to perform PHY-level hardware timestamping and time synchronization on a 10SPE network node. The timestamping and time synchronization may implement performance according to IEEE 1588 or IEEE 802.1AS. Moreover, PHY-level hardware timestamping and time synchronization may be performed on PHY hardware that is simple as the die size to implement the PHY may be limited. The PHY may be implemented without strong requirements that would limit the range of MCUs that may be selected to work with the PHY when implementing an endpoint controller.
It would have been obvious to a person of ordinary skill in the art before the effective filing of the invention to modify Zemach with a timestamp embedding and determination process and hardware at the PHY layer to conform with time synchronization for precision time protocols that known in the protocol to be perform at the physical layer of the OSI model.
Prior Art Cited But Not Used In The Rejection
US 2022/0360423- Accurate Timestamp Correction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tom Y. Chang whose telephone number is 571-270-5938. The examiner can normally be reached on Monday-Friday from 9am to 5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Emmanuel Moise, can be reached on (571)272-3865. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TOM Y CHANG/
Primary Examiner, Art Unit 2455
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