Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application claims the priority benefit of India Provisional Patent Application No. 202441022054, filed Mar. 22, 2024, entitled “OPTI-RAM: Method and System to support External RAM and Flash for MCU,” which is hereby incorporated by reference in its entirety.
DETAILED ACTION
This Office Action is in response to a Non-Provisional Patent Application received on 09/23/2024. In the Application, claims 1-20 have been received for consideration and have been examined.
Specification
Applicant’s submitted specification has been reviewed and found to be in compliance.
Drawings
Applicant’s submitted specification has been reviewed and found to be in compliance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“an address protocol controller configured to”,
“an external memory interface controller coupled to the address protocol controller and configured to” in claim 1,
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, because the claim purports to invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, but fails to recite a combination of elements as required by that statutory provision and thus cannot rely on the specification to provide the structure, material or acts to support the claimed function. As such, the claim recites a function that has no limits and covers every conceivable means for achieving the stated function, while the specification discloses at most only those means known to the inventor. Accordingly, the disclosure is not commensurate with the scope of the claim.
Dependent claims 2-7 inherit these deficiencies.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“an address protocol controller configured to”,
“an external memory interface controller coupled to the address protocol controller and configured to” in claim 1
invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Dependent claims 2-7 inherit these deficiencies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-11, 14-18, and 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Chirca et al., (US20220269607A1).
Regarding claim 1, Chirca discloses:
A device, comprising:
an address protocol controller (i.e., multi-core shared memory controller (MSMC) 200) configured to receive an access request that includes an address associated with an external memory device (i.e., a peripheral device) ([0124] The method 800 includes receiving, at a MSMC, a request from a peripheral device connected to the MSMC to access a memory address, the request corresponding to a read request or to a write request. For example, the MSMC 200 may receive a read request or a write request from a master peripheral connected to one of the coherent slave interfaces 206 (e.g., one of the processor packages 104 or another master peripheral); [0163] Referring to FIG. 21, a method of protecting data within a memory controller is shown. The method 2100 includes receiving, at a controller of a multi-core shared memory controller (MSMC), a request to write a data value to a memory address of an external memory device connected to the MSMC, at 2102); and
an external memory interface controller (i.e., an external memory interleave 220) coupled to the address protocol controller and configured to couple to the external memory device ([0062] The MSMC 200 further includes an external memory interleave 220 connected to the cache tag banks 216 and the RAM banks 218. One or more external memory master interfaces 222 are connected to the external memory interleave 220; [0127] Referring to FIG. 9, a diagram 900 illustrating read-modify-write (RMW) queues that may be included in the MSMC 200 is shown. The diagram 900 illustrates that the MSMC 200 may include a RMW queue 902 for each of the RAM banks 218);
wherein the address protocol controller is configured to:
determine, based on a type of the external memory device, whether to generate a modified address associated with the address in the access request ([0165] The method 2100 further includes transmitting the data value and the Hamming code to an external memory interleave of the MSMC on a common data path connected to components of the MSMC, at 2106. For example, the arbiter circuit 260 may transmit the data and the Hamming code to the external memory interleave 220 through the data path 262 (e.g., via one of the RMW queues 920); [0166] The method 2100 further includes determining, at the external memory interleave, a test Hamming code based on the data value. The method further includes determining whether to send the data value to the external memory device based on a comparison of the test Hamming code and the Hamming code, at 2108);
based on the external memory device being a first type (i.e., first external memory device “EMIF 0”), provide the address to the external memory device ([0166] In response to determining that the Hamming code is equal to the test Hamming code, the external memory interleave 220 may output the data to the external memory master interfaces 222 for writing to an external memory device); and
based on the external memory device being a second type (i.e., a second external memory device “EMIF 1”):
generate the modified address (FIG. 10; [0128] In the illustrated example, an external memory address range supported by the MSMC 200 is generated from a first external memory device “EMIF 0” and a second external memory device “EMIF 1”. EMIF 1 has a large capacity than the EMIF 0. The external memory interleave 220 generates the external memory address range by interleaving ranges 1010 and 1006 from the EMIF 0 with address ranges 1004 and 1008 from the EMIF 1); and
provide the modified address to the external memory interface controller ([0128] The external memory interleave 220 generates the external memory address range by interleaving ranges 1010 and 1006 from the EMIF 0 with address ranges 1004 and 1008 from the EMIF 1. A remaining range of addresses 1002 from the EMIF 0 is added to the external memory address range; [0129] FIGS. 10-11 illustrate different techniques the external memory interleave 220 may use to combine memory address spaces from a plurality of external memory devices into an external memory address range addressable by devices connected to the MSMC 200); and
wherein the external memory interface controller is configured to access the external memory device based on the modified address determined by the address protocol controller ([0062] The MSMC 200 further includes an external memory interleave 220 connected to the cache tag banks 216 and the RAM banks 218. One or more external memory master interfaces 222 are connected to the external memory interleave 220; [0096] Referring back to FIG. 2, the MSMC 200 is configured to provide coherent access to the RAM banks 218 and to memory connected to the external memory master interfaces for master peripherals connected to the to the coherent slave interfaces 206 using the hardware snoop filter banks 212).
Regarding claim 8, it is a system claim and recites similar subject matter as claim 1 and therefore rejected under similar ground of rejection.
Regarding claim 15, it is a method claim and recites similar subject matter as claim 1 and therefore rejected under similar ground of rejection.
Regarding claim 2, Chirca discloses:
The device of claim 1, wherein to generate the modified address, the address protocol controller is configured to convert a value of the address from a first value compatible with the first type of external memory to a second value compatible with the second type of external memory ([0010] The arbiter circuit is further configured to arbitrate access to the data path by the first memory access request and the second memory access request based on a comparison of the first credit threshold to a first number of credits allocated to the first destination device and a comparison of the second credit threshold to a second number of credits allocated to the second destination device; [0084] An address converter 406 helps convert read addresses and write addresses as between address formats (e.g., formats utilizing different numbers of bits) used by the master peripheral and the MSMC).
Regarding claim 9, it is a system claim and recites similar subject matter as claim 2 and therefore rejected under similar ground of rejection.
Regarding claim 16, it is a method claim and recites similar subject matter as claim 2 and therefore rejected under similar ground of rejection.
Regarding claim 3, Chirca discloses:
The device of claim 2, wherein to generate the modified address, the address protocol controller is configured to convert a format of the address from a first format compatible with the first type of external memory to a second format compatible with the second type of external memory ([0056] The MSMC bridge 210 helps convert between the various protocols, to provide bus width conversion, clock conversion, voltage conversion, or a combination thereof; [0084] An address converter 406 helps convert read addresses and write addresses as between address formats (e.g., formats utilizing different numbers of bits) used by the master peripheral and the MSMC).
Regarding claim 10, it is a system claim and recites similar subject matter as claim 3 and therefore rejected under similar ground of rejection.
Regarding claim 17, it is a method claim and recites similar subject matter as claim 3 and therefore rejected under similar ground of rejection.
Regarding claim 4, Chirca discloses:
The device of claim 2, wherein the address protocol controller is further configured to generate a data strobe signal to synchronize the external memory interface controller with the external memory device ([0084] FIG. 4 is a block diagram of a MSMC bridge 400, in accordance with aspects of the present disclosure. The MSMC bridge 400 includes a cluster slave interface 402, which may be coupled to a master peripheral to provide translations services. The cluster slave interface 402 communicates with the master peripheral though a set of channels 404A-404H … The cluster slave interface 402 responds to the master peripheral as a slave and provides the handshake and signal information for communication with the master peripheral as a slave device).
Regarding claim 11, it is a system claim and recites similar subject matter as claim 4 and therefore rejected under similar ground of rejection.
Regarding claim 18, it is a method claim and recites similar subject matter as claim 4 and therefore rejected under similar ground of rejection.
Regarding claim 7, Chirca discloses:
The device of claim 1, wherein to determine to generate the modified address, the address protocol controller is configured to read a mode enable flag that indicates the type of the external memory device ([0102] a flag (or other indicator) in the RAM banks 218 may indicate that the data stored in the fourth way of the second group is invalid or the fourth way of the RAM bank may be allocated to scratch pad memory rather than to cache space).
Regarding claim 14, it is a system claim and recites similar subject matter as claim 7 and therefore rejected under similar ground of rejection.
Regarding claim 20, it is a method claim and recites similar subject matter as claim 7 and therefore rejected under similar ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6, 12-13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chirca et al. (US20220269607A1) in view of Starkweather et al., (US20010041920A1).
Regarding claim 5, Chirca disclose:
The device of claim 2, wherein the type of memories is the external memory ([0052] The multi-core processing system 100 also includes a multi-core shared memory controller (MSMC) 110, through which is connected one or more external memories 114 and direct memory access/input/output (DMA/IO) clients 116).
Chirca does not explicitly disclose:
wherein the first type of [[external]] memory comprises non-volatile memory, and wherein the second type of [[external]] memory comprises volatile memory.
However, Starkweather discloses:
wherein the first type of external memory comprises non-volatile memory, and wherein the second type of external memory comprises volatile memory ([0063] the control electronics of the external communication device are centered around an ASIC that controls and interacts with a number of peripheral modules. These peripheral modules include an LCD display and driver, an IR port and driver, a crystal oscillator, a keypad and keypad interface, power management modules and reset circuitry, external volatile memory (e.g. SRAM) and non-volatile memory (e.g. SEEPROM)).
It would have been obvious to an ordinary person skill in the art before the effective filing date of the claimed invention to modify the multi-core shared memory controller (MSMC) of Chirca and include volatile and non-volatile memories to store data, as disclosed by Starkweather.
The motivation to include volatile and non-volatile memories to store data to enable high-speed data transfers between peripherals and main memory without burdening the CPU. This improves performance and efficiency in various domains.
Regarding claim 12, it is a system claim and recites similar subject matter as claim 5 and therefore rejected under similar ground of rejection.
Regarding claim 19, it is a method claim and recites similar subject matter as claim 5 and therefore rejected under similar ground of rejection.
Regarding claim 6, the combination of Chirca and Starkweather discloses:
The device of claim 5, wherein the non-volatile memory comprises flash memory, and wherein the volatile memory comprises random access memory (RAM) ([0063] the control electronics of the external communication device are centered around an ASIC that controls and interacts with a number of peripheral modules. These peripheral modules include an LCD display and driver, an IR port and driver, a crystal oscillator, a keypad and keypad interface, power management modules and reset circuitry, external volatile memory (e.g. SRAM) and non-volatile memory (e.g. SEEPROM)).
It would have been obvious to an ordinary person skill in the art before the effective filing date of the claimed invention to modify the multi-core shared memory controller (MSMC) of Chirca and include volatile and non-volatile memories to store data, as disclosed by Starkweather.
The motivation to include volatile and non-volatile memories to store data to enable high-speed data transfers between peripherals and main memory without burdening the CPU. This improves performance and efficiency in various domains.
Regarding claim 13, it is a system claim and recites similar subject matter as claim 6 and therefore rejected under similar ground of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED M AHSAN whose telephone number is (571)272-5018. The examiner can normally be reached 8:30 AM - 6:00 PM.
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/SYED M AHSAN/Primary Examiner, Art Unit 2491