DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 6, 9 and 12 are objected to because of the following informalities:
Regarding claim 1, the recitations of “the power supplies” in line 11, “the test power connectors” in lines 11-12 and “the device testing unit” in lines 12-13 lack antecedent basis.
Regarding claim 6, the recitation of “the studs” in line 1 lacks antecedent basis.
Regarding claim 9, the recitation of “the power supplies” in line 2 lacks antecedent basis.
Regarding claim 12, the recitations of “the first connectors” in lines 10-11, “the burn-in board” in line 11, “the power supplies” in line 19, “the test power connectors” in line 20 and “the device testing unit” in line 21 lack antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rascon et al. (US 2021/0255237 A1) in view of Toshio (US 6,181,146 B1).
Regarding claim 1, Rascon et al. teach a burn-in board configured for insertion into a chamber of a semiconductor burn-in machine (burn-in board 400 having device strip 300a; Figs 3-8; burn-in oven system 1000 may a burn-in oven machine 1002 including testing electronics 1020 and at least one thermal chamber 1004 each including a plurality of burn-in board slots 1006, and at least one burn-in board 1008 each received in a respective burn-in board slot 1006; Figs 10A-10B; [0076]), the burn-in board comprising:
a power regulator board (power supply system 1200 arranged to provide power for the example device strip 300a mounted in heated strip socket 402 on the example burn-in board 400; [0083]; Figs 3-4, 12) including:
a main power connector configured to receive main power from a semiconductor burn-in machine (card edge connector 442; FIG. 4A, 10B; burn-in board 1008 is connected with card edge connectors 442 provided on burn-in board 1080, thereby providing electrical connections between testing electronics 1020 and burn-in board circuitry via suitable card edge connectors 442 and interface circuitry 440; [0078]; the burn-in oven system 1000 has main power powering the whole system including the burn-in boards 400); and
a plurality of power supplies each configured to receive the main power from the main power connector and convert the main power to test power (the power supply system 1200 includes five fault-detection drivers 1202a-1202e, each including a power supply providing power to the DUTs in a corresponding device panel 306a-306e; [0083]; FIG. 12); and
a testing board attached to the power regulator board and including a plurality of device testing units, each device testing unit configured to receive the test power from at least one of the power supplies through test power connectors and apply test signals to a semiconductor device received in the device testing unit (heated strip socket 402 is configured to receive the example device strip 300a for heating and testing the devices 302 on device strip 300a; [0051]; Figs 4-8).
Further regarding claim 1, Rascon et al. do not teach a pair of test power connectors for each power supply of the plurality of power supplies.
Further regarding claim 1, Toshio teaches a pair of test power connectors for each power supply of a plurality of power supplies (a Vcc circuit changeover socket 204A as a first circuit changeover socket and a GND circuit changeover socket 205A as a second circuit changeover socket are arranged in a wiring connection area between the test terminals of numbers 1 to 7 at one side of each of the IC sockets and the resistors 203 corresponding to these terminals on this burn-in board 200; column 4, lines 39-51; Figs 1-4) for the purpose of connecting a first power source, at Vcc potential, and a second power source, at ground potential.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate a pair of test power connectors for each power supply of the plurality of power supplies, as taught by Toshio, into Rascon et al. for the purpose of connecting a first power source, at Vcc potential, and a second power source, at ground potential.
Claim(s) 2-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rascon et al. (US 2021/0255237 A1) as modified by Toshio (US 6,181,146 B1) as applied to claim 1 above, and further in view of Yamakita (JP 2016125886 A).
Regarding claim 2, Rascon et al. as modified by Toshio do not teach wherein the test power has a test voltage that is less than a main voltage of the main power.
Further regarding claim 2, Yamakita teaches a test power has a test voltage that is less than a main voltage of a main power (when applying 10 V from the device power supply 20 and applying a stress voltage of 2 V to the semiconductor device 3, one regulator circuit unit 5 is connected by DCDC conversion from 10 V to 2 V input voltage; [0060]; FIG. 4) for the purpose of driving more devices at a higher current capability.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the test power has a test voltage that is less than a main voltage of the main power, as taught by Yamakita, into Rascon et al. as modified by Toshio for the purpose of driving more devices at a higher current capability.
Regarding claim 3, Rascon et al. as modified by Toshio do not teach wherein the main voltage is approximately 12V and the test voltage is within a range of about 0.5V to 3.0V.
Further regarding claim 3, Yamakita teaches the main voltage is approximately 12V and the test voltage is within a range of about 0.5V to 3.0V (when applying 10 V from the device power supply 20 and applying a stress voltage of 2 V to the semiconductor device 3, one regulator circuit unit 5 is connected by DCDC conversion from 10 V to 2 V input voltage; [0060]; FIG. 4; although the input voltage is described as 10 V, the input voltage is not limited to 10 V, and if it is set to 10 V or more, it is possible to proportionally reduce the current which can be supplied; [0061]; 10 V being approximately 12 V) for the purpose of driving more devices at a higher current capability.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the main voltage is approximately 12V and the test voltage is within a range of about 0.5V to 3.0V, as taught by Yamakita, into Rascon et al. as modified by Toshio for the purpose of driving more devices at a higher current capability.
Regarding claim 4, Rascon et al. teach wherein the power regulator board and the device testing board are stacked over each other (the burn-in board 400 and the heated strip socket 402 is stacked over each other; Figs 4-8).
Regarding claim 5, Rascon et al. teach wherein each test power connector comprises a conductive stud extending from the power regulator board to the device testing board (metal contacts 701; Figs 7-8).
Regarding claim 6, Rascon et al. teach wherein the studs extend across a gap between the power regulator board and the device testing board (metal contacts 701; Figs 7-8).
Regarding claim 7, Rascon et al. teach wherein the power regulator board is stacked beneath the device testing board (the burn-in board 400 is stacked beneath the heated strip socket 402; Figs 4-8).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rascon et al. (US 2021/0255237 A1) as modified by Toshio (US 6,181,146 B1) and Yamakita (JP 2016125886 A) as applied to claim 4 above, and further in view of Suga et al. (US 2007/0057686 A1).
Regarding claim 8, Rascon et al. teach wherein the power regulator board includes a front edge, a back edge opposite the front edge and a pair of opposing side edges each extending from the front edge to the back edge (the four edges of the burn-in board 400; Figs 4A-4B).
Further regarding claim 8, Rascon et al. as modified by Toshio and Yamakita do not teach wherein the main power connector is located along the back edge of the power regulator board.
Further regarding claim 8, Suga et al. teach a main power connector is located along the back edge of a power regulator board (the back of each slot 110 is provided with a connector into which an edge connector 202 of a burn-in board 200 can be inserted; [0077]; Figs 1-4) for the purpose of making connection when the board is fully inserted into a slot of a chamber.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the main power connector is located along the back edge of the power regulator board, as taught by Suga et al., into Rascon et al. as modified by Toshio and Yamakita for the purpose of making connection when the board is fully inserted into a slot of a chamber.
Regarding claim 9, Yamakita teaches wherein the plurality of power supplies includes a row of the power supplies extending along the front edge, a row of the power supplies extending along the back edge, and a row of the power supplies extending along each of the side edges (regulator circuits 5; Figs 13-14).
Allowable Subject Matter
Claims 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12-23 would be allowable if rewritten or amended to overcome the objection(s) set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for indicating allowable subject matter of claim(s) 10-11 is the inclusion of “wherein the testing board includes: a front edge, a back edge opposite the front edge and a pair of opposing side edges each extending from the front edge to the back edge; and a testing stage connector, through which the test signals are communicated to the device testing units, located along the back edge of the testing board, which is approximately parallel to the back edge of the power regulator board”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 10-11 allowable over the prior art.
The primary reason for indicating allowable subject matter of claim(s) 12-23 is the inclusion of “a pre-regulator configured to convert bulk power having a bulk voltage to main power having a main voltage, which is less than the bulk voltage” and “a plurality of power supplies each configured to receive the main power from the main power connector and convert the main power to test power”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 12-23 allowable over the prior art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dangelo et al. (US 2006/0002161 A1) teach a burn-in and diagnostic testing system comprising bulk power supplies sourcing voltage regulator modules.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENDRICK X LIU whose telephone number is (571)270-3798. The examiner can normally be reached MWFSa 10am-8pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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29 May 2026
/KENDRICK X LIU/Examiner, Art Unit 2853
/DOUGLAS X RODRIGUEZ/Supervisory Patent Examiner, Art Unit 2853
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