DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, claim 7 recites “a common body contact region and a common electrically conducting via connected between the body contact region and the source electrode”. However, claim 1, from which claim 7 depends, recites a body contact region and claim 4, from which claim 7 depends, recites an electrically conducting via. As such, it is not clear whether the “a common body contact region” in claim 7 is the same or different structure as the “a body contact region” in claim 1 and the “a common electrically conducting via” in claim 7 is the same or different structure as the “an electrically conducting via” recited in claim 4. As such, the claim language is unclear. Appropriate correction is required to clarify the language.
Regarding claim 16, claim 16 recites “the insulating layer”. However, “an insulating layer” is not recited earlier in claim 16. Thus, “the insulating layer” lacks proper antecedent basis. Appropriate change is required to resolve the antecedent basis issue. For purposes of compact prosecution “the insulating layer” is interpreted by the Examiner to be “an insulating layer”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7 16 and 17 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yilmaz (US 2019/0273157) hereinafter “Yilmaz”.
Regarding claim 1, Figs. 1A and 3C of Yilmaz teaches a transistor device, comprising: a plurality of transistor cells; and a source electrode (Item 122), wherein each of the transistor cells comprises: a source region (Item 120) of a first doping type (n-type); a body region (Item 108) of a second doping type (p-type) complementary to the first doping type and adjoining the source region (Item 120); a gate electrode (Item 114B) adjacent to the body region (Item 108), dielectrically insulated from the body region (Item 108) by a gate dielectric (Item 116A), and arranged in a gate trench extending from a first surface of a semiconductor body into the semiconductor body; a body contact region (Item 112B) adjoining the body region (Item 108) and electrically connected to the source electrode (Item 122), wherein a distance (Item d1 or d2) between the body contact region (Item 112B) and the gate dielectric (Item 116A) is less than 300 nanometers (Fig. 3C where the distance between a gate trench and contact trench is 200 nm such that the distance between the gate dielectric and the body contact region is equal to or slightly less than 200 nm as the body contact region slightly bulges out from the contact trench).
Regarding claim 2, Figs. 1A and 3C of Yilmaz further teaches where the distance between the body contact region (Item 112B) and the gate dielectric is greater than 150 nanometers (Fig. 3C where the distance between a gate trench and contact trench is 200 nm such that the distance between the gate dielectric and the body contact region is equal to or slightly less than 200 nm as the body contact region slightly bulges out from the contact trench).
Regarding claim 3, Fig. 1A of Yilmaz further teaches an insulating layer (Item BPSG) arranged between the source electrode (Item 122) and the first surface of the semiconductor body.
Regarding claim 4, Fig. 1A of Yilmaz further teaches where the body contact region (Item 112B) is connected to the source electrode (Item 122) through an electrically conducting via (Item 106) extending from the source electrode (Item 122) through the insulating layer (Item BPSG).
Regarding claim 5, Figs. 1A and 3C of Yilmaz further teaches where a distance between the electrically conducting via (Item 106) and the gate dielectric (Item 116A) is less than 350 nanometers (Fig. 3C where the distance between the gate trench and contact trench is 200 nm).
Regarding claim 7, Fig. 1A of Yilmaz further teaches where source and body regions (Items 120 and 108, respectively) of two neighboring transistor cells are arranged in a mesa region between neighboring gate trenches, and where the two neighboring transistor cells comprises a common body contact region (Item 112B) and a common electrically conducting via (Item 106) connected between the body contact region (Item 112B) and the source electrode (Item 122).
Regarding claim 16, Figs. 1A and 3C of Yilmaz teaches a transistor device, comprising: a plurality of transistor cells; and a source electrode (Item 122), wherein each of the transistor cells comprises: a source region (Item 120) of a first doping type (n-type); a body region (Item 108) of a second doping type (p-type) complementary to the first doping type and adjoining the source region (Item 120); a gate electrode (Item 114B) adjacent to the body region (Item 108), dielectrically insulated from the body region (Item 108) by a gate dielectric (Item 116A), and arranged in a gate trench extending from a first surface of a semiconductor body into the semiconductor body; a body contact region (Item 112B) adjoining the body region (Item 108) and electrically connected to the source electrode (Item 122), wherein the body contact region (Item 112B) is connected to the source electrode (Item 122) through an electrically conducting via (Item 106) extending from the source electrode (Item 122) through an insulating layer (Item BPSG) and a portion of the semiconductor body (Item 108) to the body contact region (Item 112B), wherein a distance (Item d1 or d2) between the body contact region (Item 112B) and the gate dielectric (Item 116A) is less than 300 nanometers (Fig. 3C where the distance between a gate trench and contact trench is 200 nm such that the distance between the gate dielectric and the body contact region is equal to or slightly less than 200 nm as the body contact region slightly bulges out from the contact trench).
Regarding claim 17, Fig. 1A of Yilmaz further teaches where the distance between the electrically conducting via (Item 106) and the gate dielectric (Item 116A) is less than 300 nanometers (Fig. 3C where the distance between a gate trench and contact trench is 200 nm).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 8, 9, 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yilmaz (US 2019/0273157) hereinafter “Yilmaz” in view of Hirler et al. (US 2020/0388703) hereinafter “Hirler”.
Regarding claim 6, Yilmaz teaches all of the elements of the claimed invention as stated above.
Fig. 1A of Yilmaz further teaches where source regions (Item 120) and body regions (Item 108) of two neighboring transistor cells are arranged in a mesa region between neighboring gate trenches.
Yilmaz does not teach where each of the two neighboring transistor cells comprises a respective body contact region and a respective electrically conducting via.
Fig. 8 of Hirler teaches where source regions (Item 311 and 312) and body regions (Item 321) of two neighboring transistor cells are arranged in a mesa region between neighboring gate trenches, where each of the two neighboring transistor cells comprises a respective body contact region (Item 322) and a respective electrically conducting via (Item 421 and 423, respectively).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each of the two neighboring transistor cells comprise a respective body contact region and a respective electrically conducting via because this configuration avoids the unwanted activation of parasitic bipolar transistors (Hirler Paragraph 0036).
Regarding claim 8, the combination of Yilmaz and Hirler teaches all of the elements of the claimed invention as stated above.
Yilmaz does not teach a further body contact region arranged between the body contact regions of the neighboring transistor cells and connected to the source electrode through a further electrically conducting via.
Fig. 8 of Hirler teaches a further body contact region (Item 322 in between left and right Item 322 in the mesa) arranged between the body contact regions of the neighboring transistor cells and connected to the source electrode (Item S) through a further electrically conducting via (Item 422).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a further body contact region arranged between the body contact regions of the neighboring transistor cells and connected to the source electrode through a further electrically conducting via because this configuration avoids the unwanted activation of parasitic bipolar transistors (Hirler Paragraph 0036).
Regarding claim 9, the combination of Yilmaz and Hirler teaches all of the elements of the claimed invention as stated above.
Yilmaz does not teach wherein the further body contact region is spaced apart from the body contact regions of the neighboring transistor cells.
Fig. 8 of Hirler further teaches where the further body contact region (Item 322 in between left and right Item 322 in the mesa) is spaced apart from the body contact regions of the neighboring transistor cells.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the further body contact region is spaced apart from the body contact regions of the neighboring transistor cells because this configuration avoids the unwanted activation of parasitic bipolar transistors (Hirler Paragraph 0036).
Regarding claim 12, Yilmaz teaches all of the elements of the claimed invention as stated above except drift regions of the first doping type; compensation regions of the second doping type; a drain region of the first doping type; and a buffer region of the first doping type arranged between the drain region and the drift and compensation regions, wherein each of the drift regions adjoins the body region of at least one of the transistor cells, and wherein each of the compensation regions is connected to the source electrode and is adjacent to at least one of the drift regions.
Fig. 8 of Hirler teaches drift regions (Item 35) of the first doping type (n-type); compensation regions (Item 38) of the second doping type (p-type; Paargraph 0026); a drain region (Item 36) of the first doping type; and a buffer region (Item 111) of the first doping type arranged between the drain region (Item 36) and the drift (Item 35) and compensation regions (Item 38), wherein each of the drift regions (Item 35) adjoins the body region (Item 32) of at least one of the transistor cells, and wherein each of the compensation regions (Item 38) is connected to a source electrode (Item 41) and is adjacent to at least one of the drift regions (Item 35).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have drift regions of the first doping type; compensation regions of the second doping type; a drain region of the first doping type; and a buffer region of the first doping type arranged between the drain region and the drift and compensation regions, wherein each of the drift regions adjoins the body region of at least one of the transistor cells, and wherein each of the compensation regions is connected to the source electrode and is adjacent to at least one of the drift regions because this is known to form a robust semiconductor device having an increased breakdown voltage (Hirler Paragraph 0003).
Regarding claim 13, the combination of Yilmaz and Hirler teaches all of the elements of the claimed invention as stated above.
Yilmaz does not teach where each of the compensation regions adjoins the body region of at least one of the transistor cells.
Fig. 8 of Hirler further teaches where each of the compensation regions (Item 38) adjoins the body region (Item 32) of at least one of the transistor cells.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have each of the compensation regions adjoin the body region of at least one of the transistor cells because this is known to form a robust semiconductor device having an increased breakdown voltage (Hirler Paragraph 0003)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yilmaz (US 2019/0273157) hereinafter “Yilmaz” in view of Hirler et al. (US 2020/0388703) hereinafter “Hirler” and in further view of Lin et al. (US 2010/0117142) hereinafter “Lin”.
Regarding claim 10, the combination of Yilmaz and Hirler teaches all of the elements of the claimed invention as stated above.
Yilmaz does not teach wherein the further body contact region adjoins the body contact regions of the neighboring transistor cells.
Fig. 4(b) of Lin teaches where the further body contact region (Middle P+ in the mesa) adjoins the body contact regions of the neighboring transistor cells.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the further body contact region adjoin the body contact regions of the neighboring transistor cells because this configuration avoids a latch-up effect (Lin Paragraph 0024).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yilmaz (US 2019/0273157) hereinafter “Yilmaz” in view of Burke et al. (US 2018/0096849) hereinafter “Burke”.
Regarding claim 11, Yilmaz teaches all of the elements of the claimed invention as stated above.
Yilmaz does not explicitly teach where a doping concentration of the body contact region is at least 10 times a doping concentration of the body region.
Burke teaches a body region (Item 702) and body contact region (Item 809) where a doping concentration of the body contact region is at least 10 times a doping concentration of the body region (Paragraph 0044 where the doping concentration of the body region is at most 1x1018 and Paragraph 0048 where the doping concentration of the body contact region is at least 1x1019).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a doping concentration of the body contact region is at least 10 times a doping concentration of the body region because this is known to form good ohmic contact between the body region and the conductive via extending into the body region (Yilmaz Paragraph 0048).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yilmaz (US 2019/0273157) hereinafter “Yilmaz” in view of Hirler et al. (US 2020/0388703) hereinafter “Hirler” and in further view of Poelzl et al. (US 2020/0052066) hereinafter “Poelzl”.
Regarding claim 14, the combination of Yilmaz and Hirler teaches all of the elements of the claimed invention as stated above.
Yilmaz does not teach where a dimension of the buffer region in a vertical direction of the semiconductor body is less than 25% of a distance between the buffer region and the first surface.
Fig. 1 of Poelzl teaches where a dimension of a buffer region (Item 142) in a vertical direction of the semiconductor body (Item 102) is less than 25% of a distance (Paragraph 0047) between the buffer region (Item 142) and a first surface (Top surface of Item 124).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a dimension of the buffer region in a vertical direction of the semiconductor body is less than 25% of a distance between the buffer region and the first surface because this is known to limit out-diffusion of dopant atoms from the substrate into a drift zone (Poelzl Paragraph 0047).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yilmaz (US 2019/0273157) hereinafter “Yilmaz” in view of Hirler et al. (US 2020/0388703) hereinafter “Hirler” and Poelzl et al. (US 2020/0052066) hereinafter “Poelzl” and in further view of Fujino et al. (US 2024/0097023) hereinafter “Fujino”.
Regarding claim 15, the combination of Yilmaz, Hirler and Poelzl teaches all of the elements of the claimed invention as stated above except where the distance between the buffer region and the first surface is between 35 micrometers and 50 micrometers.
Fujino teaches where a thickness of a dirft layer (which is directly correlated to the distance between the buffer region and the first surface) is a result effective variable (Paragraph 0036 where the thickness of the drift layer is designed to be a thickness that satisfies predetermined withstand voltage conditions). In In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), the CCPA held that a particular parameter must first be recognized as a result-effective variable, i.e., a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. (MPEP 2144.05)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize the distance between the buffer region and the first surface such that the distance between the buffer region and the first surface is between 35 micrometers and 50 micrometers because "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP 2144.05).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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