Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: FIG. 4: 406. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 2 sets forth “arrangedin”. For purposes of compact prosecution, this is being interpreted as “arranged in”. Appropriate clarification is required.
Claim 8 sets forth “configured to access a one of the row of memory cells”. For purposes of compact prosecution, this is being interpreted as “configured to access one of the memory cells of the row of memory cells”. Appropriate clarification is required.
Claim 11 sets forth “the intermediate data from the first decoder;and”. This is interpreted as “the intermediate data from the first decoder; and”. Appropriate clarification is required.
Claims 12-20 are objected to as dependent upon claim 11.
Claim 12 sets forth “The method of claim 11, the memory bank comprises”. For purposes of compact prosecution, this is being interpreted as “The method of claim 11, wherein the memory bank comprises”. Appropriate clarification is required.
Claim 14 sets forth “The method of claim 11, wherein the decoding, by the first decoder, the address data, to provide intermediate data comprises decoding predetermined bits of the address data, the predetermined bits are less in number than a total number of bits of the address data.” This claim language is unclear. For purposes of compact prosecution, this is being interpreted as “The method of claim 11, wherein the decoding by the first decoder of the address data to provide intermediate data comprises: decoding predetermined bits of the address data, and wherein the predetermined bits are less in number than a total number of bits of the address data.” Appropriate clarification is required.
Claim 15 sets forth “addressdata”. For purposes of compact prosecution, this is being interpreted as “address data”. Appropriate clarification is required.
Claim 18 sets forth “furthercomprising”. For purposes of compact prosecution, this is being interpreted as “further comprising”. Appropriate clarification is required.
Claim 18 sets forth “addressdata”. For purposes of compact prosecution, this is being interpreted as “address data”. Appropriate clarification is required.
Claim 19 sets forth “furthercomprising”. For purposes of compact prosecution, this is being interpreted as “further comprising”. Appropriate clarification is required.
Claim 19 sets forth “addressdata”. For purposes of compact prosecution, this is being interpreted as “address data”. Appropriate clarification is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 sets forth “wherein memory cells addressable by a respective word line” in lines 9-10. It is unclear if these “memory cells addressable by a respective word line” are intended to refer to “a plurality of memory cells” and/or “the memory cells” referred to previously in the claim, or if they are referring to a separate group of one or more memory cells. Appropriate clarification is required.
Claims 2-10 are rejected as dependent upon claim 1.
Claim 9 sets forth “a column decoder configured to receive column address data and decode to provide column selection data to the bit lines”. This claim language is indefinite. It is unclear how to specifically make and/or use an invention including “and decode to provide column selection data to the bit lines”, specifically what is being decoded. Appropriate clarification is required.
Claim 15 sets forth “the method of claim 11, wherein decoding, by the first decoder, the address data, to provide intermediate data comprises: at multiple sub-decoders of the first decoder, decoding segmented bits of the address data.” This language is indefinite. For purposes of compact prosecution, this is being interpreted as “the method of claim 11, wherein the decoding, by the first decoder, of the address data, to provide intermediate data comprises: at multiple sub-decoders of the first decoder, decoding segmented bits of the address data”. Appropriate clarification is required.
Claim 16 is rejected as dependent upon claim 15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 7, 10-11, 13-14, 17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20230170010 A1 (Jain et al., hereinafter Jain).
Regarding claim 1, Jain teaches a memory (Jain, FIG. 1-7) comprising at least one memory bank (Jain, [0028]: “memory partition 102A-102D includes memory banks 110U and 110L”) comprising a set of memory arrays (“each memory cell array 110AR”) each comprising a plurality of memory cells; (Jain, [0028]: “Each memory bank 110U and 110L includes a memory cell array 110AR and a local input output (LIO) circuit 110BS.”) wherein the at least one memory bank comprises: multiple word lines (Jain, WL in FIG. 2A;) each connected to a corresponding row of the memory cells; (Jain, [0034]: “[0034]: “corresponding word lines WL”) a first decoder (Jain, pre-decoder 204 in FIG. 2A) configured to receive address data, (Jain, “address signals”) and decode the address data to provide intermediate data; (Jain, “global address decode circuit”) and a second decoder (Jain, post decoder 240a, 240b in fig. 2A; right side of memory bank 110L, 110U, [0091]) located in a central area of the memory bank between ones of the set of memory arrays, (Jain, arrays 210a, 210b in fig. 2A) and configured to receive the intermediate data from the first decoder, and decode the intermediate data to provide selection data to the word lines; (Jain, [0118-0136]) wherein memory cells addressable by a respective word line designated by the selection data are configured to be addressable by means of that selection data. (Jain, including [0055-0061]. Jain, [0055-0057]: “The address latch and pre-decoder circuit 204 is configured to generate a set of address signals LADR[0:10], a set of global pre-decoder signals PREDEC1_GLOBAL and a set of global pre-decoder signals PREDEC2_GLOBAL in response to a memory address signal ADR. In some embodiments, the memory address signal ADR and the set of address signals LADR[0:10] includes 11 bits (e.g., written as [0:10]). In some embodiments, the set of address signals LADR[0:10] is divided into a first set of address signals LADR[0:4], a second set of address signals LADR[5:7] and a third set of address signals LADR[8:10]. In some embodiments, the first set of address signals LADR[0:4] includes 5 bits, and the 5 bits are located at bit positions 0:4 in the set of address signals LADR[0:10]. In some embodiments, the second set of address signals LADR[5:7] includes 3 bits, and the 3 bits are located at bit positions 5:7 in the set of address signals LADR[0:10]. In some embodiments, the third set of address signals LADR[8:10] includes 3 bits, and the 3 bits are located at bit positions 8:10 in the set of address signals LADR[0:10]…”)
Regarding claim 3, Jain teaches the memory of claim 1, wherein each memory array comprises 8 rows each having 2048 memory cells. (Jain. [0038]: “Each memory cell array 110AR includes an array of memory devices 112 having N rows and M columns, where M and N are positive integers. The rows of cells in memory cell array 102 are arranged in a first direction X.”)
Regarding claim 4, Jain teaches the memory of claim 1, wherein the first decoder (Jain, pre-decoder 204 in FIG. 2A) is configured to decode predetermined bits of the address data, wherein the predetermined bits are less in number than a total number of bits of the address data. (Jain, [0055-0057]: “…In some embodiments, the first set of address signals LADR[0:4] includes 5 bits, and the 5 bits are located at bit positions 0:4 in the set of address signals LADR[0:10]. In some embodiments, the second set of address signals LADR[5:7] includes 3 bits, and the 3 bits are located at bit positions 5:7 in the set of address signals LADR[0:10]. In some embodiments, the third set of address signals LADR[8:10] includes 3 bits, and the 3 bits are located at bit positions 8:10 in the set of address signals LADR[0:10].”)
Regarding claim 7, Jain teaches the memory of claim 1, wherein the second decoder is configured to provide the selection data as a one-hot code decoded from the address data. (The instant specification provides that “The skilled person will appreciate that the term "one-hot code" refers to an indication of a single word line which is active, that is to say enabled or "hot", in order to allow memory cells in the row connected to that word line to be accessed or addressed for read and/or write operations.”; Jain, [0083-0084]: “The set of word line post-decoder circuits 240 a or 240 b is configured to receive the set of local pre-decoder signals PREDEC1_LOCAL, the set of local pre-decoder signals PREDEC2_LOCAL and one of the corresponding set of clock signals ICKD_TOP[0:3] or ICKD_BOT[0:3]. The set of word line post-decoder circuits 240 a or 240 b is configured to generate a set of word line signals WL′ in response to the set of local pre-decoder signals PREDEC1_LOCAL, the set of local pre-decoder signals PREDEC2_LOCAL and one of the corresponding set of clock signals ICKD_TOP[0:3] or ICKD_BOT[0:3]. The set of word line post-decoder circuits 240 a and 240 b is configured to output the set of word line signals WL′ on corresponding word lines WL. The set of word line post-decoder circuits 240 a and 240 b is further coupled to corresponding memory cell array 210 a or 210 b by the word lines WL. At least one of memory cell array 210 a or 210 b is configured to store a corresponding first set of data or a second set of data in response to at least the set of word line signals WL′.”)
Regarding claim 10, Jain teaches the memory of claim 1, wherein the first decoder is further configured to receive control data, (Jain, [0022]: “a global control circuit configured to generate a first set of global pre-decoder signals”) and decode the control data to control operation of the memory bank. (Jain, [0030]: “GIO circuit 100BL is a circuit configured to control access to one or more electrical paths, e.g., bit lines, to each memory device of the corresponding memory bank 110U or 110L of each memory partition 102A-102D, e.g., by generating one or more bit line signals.”; Jain, [0046]: “Memory circuit 200 includes memory partitions 102A-102D, a global control circuit 201 and GIO circuits 100BL.”)
Regarding claim 11, Jain teaches a method (Jain, FIG. 1-7) of accessing a memory comprising at least one memory bank, (Jain, [0028]: “memory partition 102A-102D includes memory banks 110U and 110L”) the method comprising: receiving, at a first decoder, (Jain, pre-decoder 204 in FIG. 2A) address data for accessing the memory; (Jain, “address signals”) wherein the at least one memory bank of the memory comprises a set of memory arrays (“each memory cell array 110AR”) each comprising a plurality of memory cells; (Jain, [0028]: “Each memory bank 110U and 110L includes a memory cell array 110AR and a local input output (LIO) circuit 110BS.”) decoding, by the first decoder, (Jain, pre-decoder 204 in FIG. 2A) the address data, to provide intermediate data; (Jain, “address signals”) receiving, by a second decoder located in a central area of the memory bank between ones of the set of memory arrays, (Jain, post decoder 240a, 240b in fig. 2A; right side of memory bank 110L, 110U, [0091]) the intermediate data from the first decoder; and decoding, by the second decoder, the intermediate data, to provide selection data to word lines each connected to a corresponding row of the memory cells; (Jain, [0118-0136]) and enabling at least one of read or write access to the row of the memory cells connected to the word line designated by the selection data. (Jain, [0302]: “In some embodiments, during the latch mode, a read/write operation of at least one of memory cell array 210 a or 210 b is performed, and the inverter 1004, PMOS transistors MP3 and MP4 and NMOS transistors MN4 and MN3 are configured to latch the address signal LADR[0] or inverted address signal ADRB[0].”)
Regarding claim 13, Jain teaches the method of claim 11, wherein each memory array comprises 8 rows each having 2048 memory cells. (Jain. [0038]: “Each memory cell array 110AR includes an array of memory devices 112 having N rows and M columns, where M and N are positive integers. The rows of cells in memory cell array 102 are arranged in a first direction X.”)
Regarding claim 14, Jain teaches the method of claim 11, wherein the decoding, by the first decoder, (Jain, pre-decoder 204 in FIG. 2A) the address data, to provide intermediate data comprises decoding predetermined bits of the address data, the predetermined bits are less in number than a total number of bits of the address data. (Jain, [0055-0057]: “…In some embodiments, the first set of address signals LADR[0:4] includes 5 bits, and the 5 bits are located at bit positions 0:4 in the set of address signals LADR[0:10]. In some embodiments, the second set of address signals LADR[5:7] includes 3 bits, and the 3 bits are located at bit positions 5:7 in the set of address signals LADR[0:10]. In some embodiments, the third set of address signals LADR[8:10] includes 3 bits, and the 3 bits are located at bit positions 8:10 in the set of address signals LADR[0:10].”)
Regarding claim 17, Jain teaches the method of claim 11, wherein the decoding, by the second decoder, the intermediate data, to provide selection data comprises providing the selection data as a one-hot code decoded from the address data. (The instant specification provides that “The skilled person will appreciate that the term "one-hot code" refers to an indication of a single word line which is active, that is to say enabled or "hot", in order to allow memory cells in the row connected to that word line to be accessed or addressed for read and/or write operations.”; Jain, [0083-0084]: “The set of word line post-decoder circuits 240 a or 240 b is configured to receive the set of local pre-decoder signals PREDEC1_LOCAL, the set of local pre-decoder signals PREDEC2_LOCAL and one of the corresponding set of clock signals ICKD_TOP[0:3] or ICKD_BOT[0:3]. The set of word line post-decoder circuits 240 a or 240 b is configured to generate a set of word line signals WL′ in response to the set of local pre-decoder signals PREDEC1_LOCAL, the set of local pre-decoder signals PREDEC2_LOCAL and one of the corresponding set of clock signals ICKD_TOP[0:3] or ICKD_BOT[0:3]. The set of word line post-decoder circuits 240 a and 240 b is configured to output the set of word line signals WL′ on corresponding word lines WL. The set of word line post-decoder circuits 240 a and 240 b is further coupled to corresponding memory cell array 210 a or 210 b by the word lines WL. At least one of memory cell array 210 a or 210 b is configured to store a corresponding first set of data or a second set of data in response to at least the set of word line signals WL′.”)
Regarding claim 20, Jain teaches the method of claim 11, further comprising: receiving, at the first decoder, control data; (Jain, [0022]: “a global control circuit configured to generate a first set of global pre-decoder signals”) decoding, by the first decoder, the control data, to control operation of the memory bank. (Jain, [0030]: “GIO circuit 100BL is a circuit configured to control access to one or more electrical paths, e.g., bit lines, to each memory device of the corresponding memory bank 110U or 110L of each memory partition 102A-102D, e.g., by generating one or more bit line signals.”; Jain, [0046]: “Memory circuit 200 includes memory partitions 102A-102D, a global control circuit 201 and GIO circuits 100BL.”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable in view of US 20230170010 A1 (Jain et al., hereinafter Jain).
Regarding claim 2, Jain teaches the memory of claim 1, and Jain provides for any reasonable arrangement of memory arrays and placement of decoders.
Claim 2 sets forth wherein the memory bank comprises eight memory arrays arrangedin an array of 2 columns by 4 rows, and wherein the first decoder is placed at an edge of the memory bank between 2 columns of memory arrays, and the second decoder is placed between the second and third rows of the 4-row memory arrays.
Although Jain does not specifically list the arrangement of memory arrays and decoders as set forth in claim 2, one of ordinary skill in the art would recognize that this arrangement of memory arrays and decoders would not achieve any new unexpected, functional, or synergistic result, and is merely a spatial modification of the teachings of Jain. Re Gustafson, 331 F.2d 905 (C.C.P.A. 1964): Established that claiming a "convenient and obvious location of elements in space" that does not yield an unexpected, functional, or synergistic result is unpatentable as obvious.
Regarding claim 12, Jain teaches the method of claim 11, and Jain provides for any reasonable arrangement of memory arrays and placement of decoders.
Claim 12 sets forth wherein the memory bank comprises eight memory arrays arranged in an array of 2 columns by 4 rows, and wherein the first decoder is placed at an edge of the memory bank between 2 columns of memory arrays, and the second decoder is placed between the second and third rows of the 4-row memory arrays.
Although Jain does not specifically list the arrangement of memory arrays and decoders as set forth in claim 12, one of ordinary skill in the art would recognize that this arrangement of memory arrays and decoders would not achieve any new unexpected, functional, or synergistic result, and is merely a spatial modification of the teachings of Jain. Re Gustafson, 331 F.2d 905 (C.C.P.A. 1964): Established that claiming a "convenient and obvious location of elements in space" that does not yield an unexpected, functional, or synergistic result is unpatentable as obvious.
Regarding claim 19, Jain teaches the method of claim 11, and Jain provides for any reasonable arrangement of decoders and enabling of read or write access.
Claim 19 sets forth furthercomprising:receiving, at a column decoder, column addressdata; decoding, by the column decoder, the column address data, to provide column selection data to bit lines each connected to a corresponding column of the memory cells; and enabling at least one of read or write access to the column of the memory cells connected to the bit line designated by the column selection data.
Although Jain does not specifically set forth a “column decoder”, one of ordinary skill in the art would recognize that additional decoders to receive additional data in order to further enable at least one of read or write access would not achieve any new unexpected, functional, or synergistic result, and is merely a spatial modification of the teachings of Jain. Re Gustafson, 331 F.2d 905 (C.C.P.A. 1964): Established that claiming a "convenient and obvious location of elements in space" that does not yield an unexpected, functional, or synergistic result is unpatentable as obvious.
Claim(s) 5-6 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Kazuyuki (JP 2007079398 A).
Regarding claim 5, Jain teaches the memory of claim 1, and does teach wherein there are a number of first decoders, but does not appear to explicitly teach wherein the first decoder comprises multiple sub-decoders each configured to decode segmented bits of the address data.
Kazuyuki cures the deficiencies of Jain. Kazuyuki teaches wherein the first decoder comprises multiple sub-decoders each configured to decode segmented bits of the address data. (Kazuyuki, [0056]: “The second circuit unit 5 includes a second decoder 51. The second decoder 51 has 40 sub-decoders Dec0 to Dec39. Each of these sub-decoders Dec0 to Dec39 is connected to a line group Loff, Lseg, and Lbank…Kazuyuki, [0042]: The segment decoder 432 decodes the intermediate 3-bit sub-data A <5: 3> = <A5, A4, A3> in the address data A <8: 0>, and the decoded sub-data A <5 : 3> is output as the segment data group C <7: 0>. The segment decoder 431 outputs the segment data group C <7: 0> in addition to the sub data A <5: 3>…”)
Kazuyuki and Jain both include subject matter directed to circuit devices including decoders and sub-decoders. It would have been obvious to one of ordinary skill in the art to modify the teachings of Jain with the sub-decoders configured to decode segmented data of Kazuyuki with the motivation of improving functionality of a memory device.
Regarding claim 6, Jain/Kazuyuki teaches the memory of claim 5, wherein the sub-decoder of the first decoder is selected from a 2-to-4 decoder and a 3-to-8 decoder. (One of ordinary skill in the art would recognize that the combination of Jain/Kazuyuki teaches any relevant small scale decoder, including 2-to-4 decoder and/or 3-to-8 decoder. Additionally, although Jain indicates a 3-to-8 decoder in several examples, implementing with the 2-to-4 decoder is not excluded by Jain/Kazuyuki and is well known in the art.)
Regarding claim 15, Jain teaches the method of claim 11, and does teach wherein there are a number of first decoders, but does not appear to explicitly teach wherein decoding, by the first decoder, the address data, to provide intermediate data comprises: at multiple sub-decoders of the first decoder, decoding segmented bits of the address data.
Kazuyuki cures the deficiencies of Jain. Kazuyuki teaches wherein decoding, by the first decoder, the address data, to provide intermediate data comprises: at multiple sub-decoders of the first decoder, decoding segmented bits of the address data. (Kazuyuki, [0056]: “The second circuit unit 5 includes a second decoder 51. The second decoder 51 has 40 sub-decoders Dec0 to Dec39. Each of these sub-decoders Dec0 to Dec39 is connected to a line group Loff, Lseg, and Lbank…Kazuyuki, [0042]: The segment decoder 432 decodes the intermediate 3-bit sub-data A <5: 3> = <A5, A4, A3> in the address data A <8: 0>, and the decoded sub-data A <5 : 3> is output as the segment data group C <7: 0>. The segment decoder 431 outputs the segment data group C <7: 0> in addition to the sub data A <5: 3>…”)
Kazuyuki and Jain both include subject matter directed to circuit devices including decoders and sub-decoders. It would have been obvious to one of ordinary skill in the art to modify the teachings of Jain with the sub-decoders configured to decode segmented data of Kazuyuki with the motivation of improving functionality of a memory device.
Regarding claim 16, Jain/Kazuyuki teaches the method of claim 15, wherein the sub-decoder of the first decoder is selected from a 2-to- 4 decoder and a 3-to-8 decoder. (One of ordinary skill in the art would recognize that the combination of Jain/Kazuyuki teaches any relevant small scale decoder, including 2-to-4 decoder and/or 3-to-8 decoder. Additionally, although Jain indicates a 3-to-8 decoder in several examples, implementing with the 2-to-4 decoder is not excluded by Jain/Kazuyuki and is well known in the art.)
Claim(s) 8 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of US 20160092293 A1 (Ishii, et al., hereinafter Ishii).
Regarding claim 8, Jain teaches the memory of claim 1, but does not appear to explicitly teach wherein each memory bank further comprises a column multiplexer configured to access a one of the row of memory cells designated by the selection data, in response to a column address data.
Ishii cures the deficiencies of Jain. Ishii teaches wherein each memory bank further comprises a column multiplexer (Ishii, “multiplexer 7”) configured to access a one of the row of memory cells designated by the selection data, in response to a column address data. (Ishii, [0152]: “[0152] The column decoder 18# includes a plurality of AND circuits AD2 and an inverter 1V2. The column decoder 18# generates a decode signal based on the column address data YA<1>, YA<0>.”)
Both Jain and Ishii are directed to memory devices and methods for accessing the memory. It would have been obvious to modify the teachings of Jain with the column multiplexer configured to access a row of the memory cells in response to data in order to improve functionality of the memory device.
Regarding claim 18, Jain teaches the method of claim 11, but does not appear to teach wherein the method is further comprising: receiving, at a column multiplexer, column address data; accessing a one of the row of memory cells designated by the selection data, in response to the column address data.
Ishii cures the deficiencies of Jain. Ishii teaches wherein the method is further comprising: receiving, at a column multiplexer, (Ishii, “multiplexer 7”) column address data; accessing a one of the row of memory cells designated by the selection data, in response to the column address data. (Ishii, [0152]: “[0152] The column decoder 18# includes a plurality of AND circuits AD2 and an inverter 1V2. The column decoder 18# generates a decode signal based on the column address data YA<1>, YA<0>.”)
Both Jain and Ishii are directed to memory devices and methods for accessing the memory. It would have been obvious to modify the teachings of Jain with the column multiplexer configured to access a row of the memory cells in response to data in order to improve functionality of the memory device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
Prosecution Insights