DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 15 – 34 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 19 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Additionally, the claimed subject matter is not described in the specification of any of the patent applications to which the instant application claims priority.
Specifically, the specification does not teach or describe the controller to determine a transition from data of the first link layer to data of the second link layer based on a workload of an application executed on the first die, as required by dependent claim 19. The specification describes transitioning from the first link layer to the second link layer, but does not teach that doing so is based on a workload of an application executed on the first die. The Examiner is unable to locate any discussion of application workload in the specification. Additionally, the specifications of the parent applications also fail to describe the above claim limitation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 15, 16, 20 – 29, 31 – 34 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Patent No. 9,921,768 (hereinafter Jen).
The applied reference has a common inventor and assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As per claim 15, Jen teaches an apparatus comprising: a first die (Jen; Figure 6 Item 610a) comprising a port (Jen; Figure 6 “IO”, Figure 8 Item 610) to couple the first die to a memory device (Jen; Figure 6 Item 605) over an interconnect, wherein the memory device comprises pooled memory (Jen; Col 8 Lines 19 – 38) for access by the die via the interconnect, wherein the port comprises circuitry to: implement a physical layer of the interconnect (Jen; Figure 8 Item 815); implement a first link layer of a first protocol (Jen; Figure 8 Item 810); implement a different second link layer of a different second protocol (Jen; Figure 8 Item 805); multiplex data of the first link layer and data of the second link layer on the same physical layer (Jen; Figure 9, Col 16 Lines 54 – 65), wherein, to multiplex the data, protocol identification data is to be sent from the first die to the memory device over the physical layer to identify whether data of the first link layer or the second layer is to be sent on the physical layer (Jen; Col 16 Line 54 – Col 17 Line 18); and send a flit of the first link layer over the physical layer to the memory device (Jen; Col 16 Line 54 – Col 18 Line 42).
As per claim 16, Jen also teaches wherein the interconnect comprises a die-to-die interconnect (Jen; Col 9 Lines 5 – 22).
As per claim 20, Jen also teaches wherein the circuitry is further to: send second protocol identification data over the physical layer to identify that data of the second protocol is to be sent following the flit (Jen; Figure 9, Jen; Col 17 Lines 31 – 47); and send second data over the interconnect to the memory device, wherein the second data comprises data of the second link layer (Jen; Figure 9, Jen; Col 17 Lines 31 – 47).
As per claim 21, Jen also teaches wherein the second protocol identification data is sent to indicate to the memory device that data on the interconnect is to switch from data of the first protocol to data of the second protocol (Jen; Col 17 Lines 31 – 47).
As per claim 22, Jen also teaches wherein the memory device is implemented on a second die (Jen; Figure 6 Item 605).
As per claim 23, Jen also teaches wherein the first protocol comprises a memory protocol (Jen; Figure 8 Item 810, Col 12 Lines 58 – 60, Col 16 Lines 16 – 20) and the second protocol comprises a general input/output protocol (Jen; Figure 8 Item 805, Col 16 Lines 16 – 20).
As per claim 24, Jen also teaches wherein the general I/O protocol comprises a Peripheral Component Interconnect Express (PCIe)-based protocol (Jen; Figure 8 Item 805, Col 16 Lines 16 – 20).
As per claim 25, Jen also teaches wherein the memory protocol comprises a cache-coherent memory protocol (Jen; Figure 8 Item 810, Col 10 Lines 31 – 65, Col 12 Lines 58 – 60, Col 16 Lines 16 – 20).
As per claim 26, Jen also teaches wherein the first die comprises a first address domain and the memory device comprises a different second address domain (Jen; Col 13 Lines 36 – 46).
As per claim 27, Jen also teaches address translation circuitry to translate between addresses of the first address domain and addresses of the second address domain (Jen; Col 13 Lines 36 – 46).
As per claim 28, Jen teaches an apparatus: first protocol logic (Jen; Figure 8 Item 810) to implement a first interconnect protocol; second protocol logic (Jen; Figure 8 Item 805) to implement a different second interconnect protocol; an interface (Jen; Figure 6 “IO”, Figure 8 Item 610) to couple to a memory device (Jen; Figure 6 Item 605) over an interconnect, wherein the memory device comprises pooled memory (Jen; Col 8 Lines 19 – 38) accessible over the interface, and the interface comprises circuitry to multiplex data of the first interconnect protocol and data of the second interconnect protocol over a common physical layer (Jen; Figure 8 Item 815, Figure 9, Col 16 Lines 54 – 65) of a link implemented on the interconnect, wherein protocol indicator data is sent on the link to identify a transition from data of the first interconnect protocol to flits comprising data of the second interconnect protocol (Jen; Col 16 Line 54 – Col 17 Line 18), and the link comprises a die-to-die link (Jen; Col 9 Lines 5 – 22).
As per claims 29 and 33, Jen also teaches wherein the first interconnect protocol comprises a Peripheral Component Interconnect Express (PCIe) protocol (Jen; Figure 8 Item 805, Col 16 Lines 16 – 20) and the second interconnect protocol comprises a cache coherent protocol (Jen; Figure 8 Item 810, Col 10 Lines 31 – 65, Col 12 Lines 58 – 60, Col 16 Lines 16 – 20).
As per claim 31, Jen teaches a system comprising: a first die comprising a memory device (Jen; Figure 6 Item 605); a second die (Jen; Figure 6 Item 610a) coupled to the first die by an interconnect, wherein the second die comprises a processor device (Jen; Figure 6 “CPU”) and a port (Jen; Figure 6 “IO”, Figure 8 Item 610) comprising circuitry to: implement a physical layer of the interconnect (Jen; Figure 8 Item 815); implement a first link layer of a first protocol (Jen; Figure 8 Item 810); implement a different second link layer of a different second protocol (Jen; Figure 8 Item 805); multiplex data of the first link layer and data of the second link layer on the same physical layer (Jen; Figure 9, Col 16 Lines 54 – 65), wherein, to multiplex the data, protocol identification data is to be sent from the first die to the memory device over the physical layer to identify whether data of the first link layer or the second layer is to be sent on the physical layer (Jen; Col 16 Line 54 – Col 17 Line 18); and send a flit of the first link layer over the physical layer to the memory device (Jen; Col 16 Line 54 – Col 18 Line 42).
As per claim 32, Jen also teaches address translation circuitry to translate addresses in a first address domain of the first die to addresses in a second address domain of the second die (Jen; Col 13 Lines 36 – 46).
As per claim 34, Jen also teaches wherein the memory device comprises a pooled memory to be shared by a plurality of host devices (Jen; Col 8 Lines 19 – 38).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 30 is/are rejected under 35 U.S.C. 103 as being obvious over US Patent No. 9,921,768 (hereinafter Jen) in view of US Patent No. 9,658,963 (hereinafter Morris).
The applied reference has a common inventor and/or assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
As per claims 17 and 30, Jen teaches the invention as described per claims 15 and 28 (see rejections of claims 15 and 28 above).
Jen does not explicitly teach wherein the flit comprises at least a portion of a memory request for the memory device.
However, Morris teaches a system in which a flit directed to a memory device includes at least a portion of a memory request (Morris; Col 25 Lines 12 – 35).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Jen to include the portion of memory request in the flit because doing so allows for transferring packet information over the link (Morris; Col 25 Lines 12 – 35).
Claim 18 is/are rejected under 35 U.S.C. 103 as being obvious over US Patent No. 9,921,768 (hereinafter Jen) in view of US Patent No. 9,658,963 (hereinafter Morris), and further in view of US Patent Application Publication No. 2016/01247872 (hereinafter Shrader).
The applied reference has a common inventor and/or assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
As per claim 18, Jen in combination with Morris teaches the invention as described per claim 17 (see rejection of claim 17 above).
Jen in combination with Morris does not explicitly teach wherein the first die further comprises a processor to execute instructions to determine that an address of the memory request maps to the pooled memory of the memory device, and the flit is sent to the memory device based on the address mapped to the pooled memory.
However, Shrader teaches internal routing logic which routes memory access requests to the appropriate memory based on the address of the memory request (Shrader; Paragraph [0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Jen in combination with Morris to include the address mapping because doing so allows for ensuring memory requests are transmitted to their intended destinations (Shrader; Paragraph [0029]).
Allowable Subject Matter
Claim 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination wherein the first die further comprises a controller to determine a transition from data of the first link layer to data of the second link layer based on a workload of an application executed on the first die, wherein the data is to be multiplexed based on the transition, as required by dependent claim 18, in combination with the other claimed limitations (emphasis added). The prior art of record teaches transitioning from data of a first link layer to data of a second link layer (Jen; Figure 9, Col 16 Lines 54 – 65), but does not teach doing so based on a workload of an application executed on the first die, as required by dependent claim 19.
Conclusion
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/RICHARD B FRANKLIN/ Examiner, Art Unit 2181