DETAILED ACTION
This action is in response to the Application filed on 09/23/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 09/23/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim(s) 3 and 17 is/are objected to because of the following informalities:
Claim 3, line 6 recites “the control signal is configured to generate the control signal”. It appears that it should be “the control circuit is configured to generate the control signal”.
Claim 17, line 6 recites “gird”. It appears that it should be “grid”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Pub. No. 2006/0006850; (hereinafter Inoue).
Regarding claim 1, Inoue [e.g. Fig. 1] discloses an apparatus, comprising: an integrated circuit including: a functional circuit block [e.g. Load (L)] coupled to a local power supply node [e.g. 2A]; and a local voltage regulator circuit [e.g. 5, 6] coupled to the functional circuit block via the local power supply node; and a bypass voltage regulator circuit [e.g. 3] coupled to the local power supply node and configured to provide a particular voltage level to the local power supply node [e.g. paragraph 0126 recites “the step-up chopper 3 maintains the voltage conversion ratio higher than 1 by switching of the chopper switch 3S.”]; and wherein: to provide the particular voltage level, the bypass voltage regulator circuit is configured to source a bypass electrical current to the local power supply node [e.g. paragraph 0124 recites “When the chopper switch 3S is in the ON state, a reverse-biased voltage is applied across the diode 3D, and then, a forward current Id flowing in the diode 3D falls to zero. On the other hand, a current I3 flowing through the inductor 3L rises and accordingly magnetic energy stored in the inductor 3L is increased, since the battery voltage Vi excites the inductor 3L”]; the local voltage regulator circuit is configured to maintain the particular voltage level [e.g. paragraph 0134 recites paragraph 138 recites “the output voltage Vo is maintained at a level lower than the battery voltage Vi by the non-operating voltage drop Von, when the bypass switch 5 is maintained in the ON state in the non-operating period of the step-up chopper 3”]; and to maintain the particular voltage level, the local voltage regulator circuit is configured to source a supply electrical current to the local power supply node in response to a determination that a voltage level at the local power supply node fails to satisfy a threshold voltage value [e.g. Vi; paragraph 137 recites “When the battery voltage Vi is higher than the output voltage Vo (Vi:>Vo), the bypass control section 6 maintains its output at the L level, thereby maintaining the bypass switch 5 in the ON state”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inoue in view of US Pub. No. 2007/0103136; (hereinafter Jain).
Regarding claim 2, Inoue fails to disclose wherein: a change in a load current drawn by the functional circuit block induces a drop in voltage level, causing the voltage level to fail to satisfy the threshold voltage value; the bypass voltage regulator circuit is unable to adjust the voltage level to compensate for the drop; and the local voltage regulator circuit is configured to source the supply current in response to detection of the drop in the voltage level.
Jain [e.g. Figs. 3 - 6] teaches wherein: a change in a load current [e.g. Fig. 5; dynamic mode] drawn by the functional circuit block [e.g. dynamic load 100] induces a drop in voltage level [e.g. Fig. 5; drop of Vo during dynamic mode], causing the voltage level to fail to satisfy the threshold voltage value [e.g. below 1.5V; see Fig. 6, 58c]; the bypass voltage regulator circuit is unable to adjust the voltage level to compensate for the drop; and the local voltage regulator circuit is configured to source the supply current in response to detection of the drop in the voltage level [e.g. paragraph 067 recites “turning Saux of the dynamic conversion on and off may comprise modulating (e.g., PWM) the gate of Saux during a load transient.” The auxiliary conversion circuit is used (see Fig. 5 Vgs_aux) to support the converter 10 when the load demand increases by the dynamic load creating a voltage drop at t2 as shown in Fig. 5].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Inoue by wherein: a change in a load current drawn by the functional circuit block induces a drop in voltage level, causing the voltage level to fail to satisfy the threshold voltage value; the bypass voltage regulator circuit is unable to adjust the voltage level to compensate for the drop; and the local voltage regulator circuit is configured to source the supply current in response to detection of the drop in the voltage level as taught by Jain in order of being able to provide a faster dynamic response.
Claims 3 – 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inoue in view of US Pub. No. 2021/0320590; (hereinafter NG).
Regarding claim 3, Inoue [e.g. Fig. 1] discloses wherein the bypass voltage regulator circuit includes: a control circuit [e.g. 6] configured to generate a control signal [e.g. output of 6]; a switching circuit [e.g. 5] coupled to the control circuit and coupled to an input power supply node [e.g. 1A]; the switching circuit is configured to generate the bypass electrical current based on a supply voltage level of the input power supply node [e.g. 1A] and the control signal indicating the voltage difference [e.g. paragraph 0137 recites “The bypass control section 6 performs the on-off control over the bypass switch 5, based on the difference from the battery voltage Vi and the output voltage Vo, as follows. When the battery voltage Vi is higher than the output voltage Vo (Vi>Vo), the bypass control section 6 maintains its output at the L level, thereby maintaining the bypass switch 5 in the ON state. When the battery voltage Vi is lower than the output voltage Vo (Vi<Vo), the bypass control section 6 maintains its output at the H level, thereby maintaining the bypass switch 5 in the OFF state” ].
Inoue fails to disclose a resistor coupled between a first node and a second node; and wherein: the control signal is configured to generate the control signal based on a voltage difference between a first voltage level of the first node and a second voltage level of the second node.
NG teaches a resistor [e.g. 40] coupled between a first node [e.g. output of 102] and a second node [e.g. VOUT]; and wherein: the control circuit [e.g. 32, 36, 28] is configured to generate the control signal [e.g. SW1] based on a voltage difference between a first voltage level of the first node and a second voltage level of the second node [e.g. at inverting and non-inverting of comparator 30].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Inoue by a resistor coupled between a first node and a second node; and wherein: the control signal is configured to generate the control signal based on a voltage difference between a first voltage level of the first node and a second voltage level of the second node as taught by NG in order of being able to provide stability.
Regarding claim 4, Inoue [e.g. Fig. 1] discloses wherein the switching circuit is one of a boost converter [e.g. 3 is a chopper (boost) converter] or a buck converter.
Claims 5 - 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inoue in view of US Pub. No. 2013/0176011; (hereinafter Muhammad).
Regarding claim 5, Inoue fails to disclose wherein the local voltage regulator circuit includes a low-dropout regulator circuit, and wherein, to maintain the particular voltage level, the low-drop regulator circuit is configured to adjust a conductance between a primary power supply node and the local power supply node.
Muhammad [e.g. Fig. 1] teaches wherein the local voltage regulator circuit includes a low-dropout regulator circuit [e.g. 115 - 116], and wherein, to maintain the particular voltage level, the low-drop regulator circuit is configured to adjust a conductance between a primary power supply node and the local power supply node [e.g. 115 ON; paragraph 029 recites “The bypass module 116 can be turned to a low-dropout voltage regulator (LDO) by connected external elements outside of the integrated circuit 101 while using the power transistor 115. For lower output voltages, the bypass module 116 is turned off. For higher output voltages, the power transistor 115 bypasses the step-down logic 107 and the switch 108,109 when it is desired to supply current directly from the battery input 102”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Inoue by wherein the local voltage regulator circuit includes a low-dropout regulator circuit, and wherein, to maintain the particular voltage level, the low-drop regulator circuit is configured to adjust a conductance between a primary power supply node and the local power supply node as taught by Muhammad in order of being able to provide for loads requiring higher voltage.
Regarding claim 6, Inoue discloses a power switch circuit [e.g. 5] configured to prevent injection of the bypass electrical current onto the local power supply node [e.g. when switch 5 is OFF] based on a control signal [e.g. output of 6] received at the power switch circuit [e.g. gate terminal of 5].
Inoue fails to disclose the low-dropout regulator circuit.
Muhammad [e.g. Fig. 1] teaches the low-dropout regulator circuit [e.g. paragraph 029 recites “The bypass module 116 can be turned to a low-dropout voltage regulator (LDO) by connected external elements outside of the integrated circuit 101 while using the power transistor 115].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Inoue by the low-dropout regulator circuit as taught by Muhammad in order of being able to provide for loads requiring higher voltage.
Claims 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inoue in view of US Pub. No. 2022/0302827; (hereinafter Tarroboiro).
Regarding claim 7, Inoue fails to disclose wherein the local voltage regulator circuit includes a switched-capacitor circuit, and wherein, to maintain the particular voltage level, the switched-capacitor circuit is configured to: charge a capacitor of the switched-capacitor circuit using a primary supply voltage; and discharge the capacitor into the local power supply node.
Tarroboiro [e.g. Fig. 2] teaches wherein the local voltage regulator circuit includes a switched-capacitor circuit [e.g. 211] , and wherein, to maintain the particular voltage level [e.g. Vout], the switched-capacitor circuit is configured to: charge a capacitor [e.g. C1] of the switched-capacitor circuit using a primary supply voltage [e.g. Input voltage supply at 203]; and discharge the capacitor into the local power supply node [e.g. paragraph 040].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Inoue by wherein the local voltage regulator circuit includes a switched-capacitor circuit, and wherein, to maintain the particular voltage level, the switched-capacitor circuit is configured to: charge a capacitor of the switched-capacitor circuit using a primary supply voltage; and discharge the capacitor into the local power supply node as taught by Tarroboiro in order of being able to provide a step-up output voltage or a step-down output voltage, paragraph 05.
Claims 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inoue in view of US Pub. No. 2011/0057724; (hereinafter Pabon).
Regarding claim 8, Pabon [e.g. Fig. 3] discloses an apparatus, comprising: an integrated circuit that includes: a first regulator circuit [e.g. 312] coupled to a power converter circuit [e.g. 310] via a first auxiliary power supply node [e.g. node directly connecting 310, 312 and 350]; a first circuit block [e.g. load at Pout] coupled to the first regulator circuit via a first local power supply node [e.g. node directly connecting 350 and output of 312]; and wherein: the first regulator circuit is configured to generate a particular voltage level on the first local power supply node [e.g. paragraph 040 recites “the DC/DC power converter 312 converts the voltage level of the input power P.sub.IN to a DC signal having a second voltage level, for a second level of power applications, for example, lower power applications. The second voltage level may be configured to provide any voltage within a range of tunable voltages that is different from the range providing the first voltage level. The DC power having the second voltage level is provided to an output port to supply power POUT to a connecting low power device”].
Pabon, Fig. 3 fails to disclose to generate a particular voltage level on the first local power supply node in response to a fall in a voltage level of the first local power supply node, the fall in the voltage level attributable to a fluctuation in an electrical current demand associated with the first circuit block.
Pabon, Fig. 4 teaches to generate a particular voltage level [e.g. 410a] on the first local power supply node [e.g. 410a] in response to a fall in a voltage level of the first local power supply node [e.g. paragraph 047 recites “after a digital reference is specified, if the output voltage is too low, a controlling element (such as the DC/DC converter 408 or the sense circuitry 412) may be instructed to increase the voltage to adjust the output”], the fall in the voltage level attributable to a fluctuation in an electrical current demand associated with the first circuit block [e.g. load connected to 442A].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Pabon, Fig. 3 by to generate a particular voltage level on the first local power supply node in response to a fall in a voltage level of the first local power supply node, the fall in the voltage level attributable to a fluctuation in an electrical current demand associated with the first circuit block as taught by Pabon, Fig. 4 in order of being able to adjust the output voltage, paragraph 047.
Regarding claim 16, Pabon [e.g. Fig. 3] discloses wherein the first regulator circuit includes: a transconductance device [e.g. power MOSFET in DC/DC converter 312; see paragraph 043] coupled between the first auxiliary power supply node e.g. node directly connecting 310, 312 and 350] and the first local power supply node [e.g. node directly connecting 350 and output of 312]; and a control circuit [e.g. 314] configured to generate a control signal [e.g. control signal from 314 to 312] to operate the transconductance device, wherein the control signal is based on a voltage level of the first local power supply node [e.g. see output node being input to controller 314].
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claims 17 – 20 are allowed.
Claims 9 – 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 9 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the integrated circuit further comprises: a second regulator circuit coupled to the power converter circuit via a second auxiliary power supply node; a second circuit block coupled to the second regulator circuit via a second local power supply node; and a selection circuit coupled to the first local power supply node and to the second local power supply node; and wherein: the selection circuit is configured to generate a feedback signal based on a lowest voltage level of one of the first local power supply node or the second local power supply node; and the power converter circuit is configured to adjust a magnitude of an electrical current output by the power converter circuit based on the feedback signal”.
The primary reason for the indication of the allowability of claim 17 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “selecting, by the selection circuit, a minimum voltage level of the respective voltage levels of the plurality of points in the power supply gird; and adjusting, by a regulator circuit of the integrated circuit, an operation of a power converter circuit that is external to the integrated circuit, wherein the power converted circuit is coupled to the power supply grid using the minimum voltage level.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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