76DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-10 and 17-18 is/are rejected under 35 U.S.C. 102[a2] as being anticipated by Desai [US 2019/0303777].
As claims 1 and 18, Desai [US 2019/0303777] discloses a semiconductor device [Fig 1], comprising: a first semiconductor die [Fig 1, Ref 14, 16] including a morph-link circuit [Fig 1, Ref 14] and a first interface circuit [Fig 20, Ref 20], wherein the morph-link circuit is configured to: receive streaming data formatted in a first format according to a first protocol [Fig 1, Ref 14 for receiving ethernet frame which is stream data formatted with first format according ethernet protocol, Par. 0058], the streaming data comprising a plurality of data bits in the first format and a plurality of control bits in the first format [Par. 0058 discloses ethernet frame includes data bits and control bits]; convert the streaming data to a second format according to a second protocol [Fig 1, Ref 14 converts the data bit and control bits of the ethernet frame into bus format according bus protocol, Par. 0012], including separating the plurality of control bits from the plurality of data bits [Par. 0132 discloses bus protocol separating control and data bits]; and transmit the streaming data in the second format to the first interface circuit [Fig 1, Ref 14 for transmitting data and control bits to Ref 16 using bus protocol], wherein the morph-link circuit, configured to transmit the streaming data, is further configured to transmit the plurality of data bits in the second format via a first communication channel to the first interface circuit, and to transmit control information corresponding to the plurality of control bits via a second communication channel to the first interface circuit [Fig 1, Ref 14 for transmitting data and control bits to Ref 16 using bus protocol wherein the N data bits via channel and M control bits via another channel, Par. 0132], wherein the first interface circuit is configured to cause: transmitting the plurality of data bits in the second format to a second interface circuit disposed outside the first semiconductor die according to the second protocol [Fig 1, Ref 16 send N and M bits via 12 using bus protocol, Par. 0132]; and transmitting, separately from the plurality of data bits in the second format, the control information in the second format to the second interface circuit according to the second protocol [Fig 1, Ref 12 discloses Ref 16 send N and M bits via 12 using bus protocol, Par. 0132], wherein the second protocol is different from the first protocol [Fig 1, ethernet protocol is not same as bus protocol], and wherein the second communication channel is separate and different from the first communication channel [Fig 1, N and M are different channels, Par. 0132].
As claim 2, Desai [US 2019/0303777] discloses transmitting the plurality of data bits in the second format to the second interface circuit comprises transmitting the plurality of data bits in the second format over a plurality of data lines in a parallelized manner without framing overhead according to the second protocol [Fig 1, Ref 12, N data bits on N lanes using bus protocol, Par. 0132].
As claim 3, Desai [US 2019/0303777] discloses transmitting the control information in the second format to the second interface circuit comprises transmitting the control information in the second format to the second interface circuit via a sideband communication channel, and wherein the sideband communication channel is separate and different from one or more channels for transmitting the plurality of data bits in the second format to the second interface circuit [Fig 1, Ref 12, M control bits on N lanes using bus protocol on sideband channel, Par. 0132].
As claim 4, Desai [US 2019/0303777] discloses transmitting the control information in the second format to the second interface circuit comprises transmitting at least a subset of the plurality of control bits [Par. 0070 discloses 512 bits is transmitted in 4 beats].
As claim 7, Desai [US 2019/0303777] discloses the streaming data formatted according to the first protocol comprises the plurality of data bits in the first format interleaved with the plurality of control bits in the first format [Par. 0058 discloses ethernet frame format wherein control and data bits are interleaved into frame structure].
As claim 8, Desai [US 2019/0303777] discloses a second semiconductor die that includes the second interface circuit and a second morph-link circuit [Fig 1, Ref 18 and 14].
As claim 9, Desai [US 2019/0303777] discloses the second morph-link circuit is configured to convert the streaming data from the second format to the first format using the control information [Fig 1, Ref 14 converts second format into ethernet frame format, Par. 0058].
As claim 10, Desai [US 2019/0303777] discloses the second morph-link circuit configured to convert the streaming data from the second format to the first format is further configured to generate one or more control bits [Par. 0058 discloses ethernet frame includes header].
As claim 17, Desai [US 2019/0303777] discloses the morph-link circuit configured to convert the streaming data to the second format is further configured to convert the streaming data in the first format comprising a plurality of parallel bit streams into the streaming data in the second format comprising one or more byte streams [Par. 0132 8 bits is byte and 64 bits is 8 byte so converting first format 1 byte into 1 byte of second format by Ref 14 of Fig 1].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Desai [US 2019/0303777] in view of Blankenship [US 2016/0283112].
As claim 5, Desai [US 2019/0303777] fails to disclose what Blankenship [US 2016/0283112] discloses transmitting the control information in the second format to the second interface circuit comprises transmitting checksum data for the streaming data [Par. 044 and 0051 discloses CRC for data and header].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to apply a method and system comprising generating CRC for data in order to determine if data is correct or not as disclosed by Blankenship into the teaching of Desai. The motivation would have been to prevent data loss.
As claim 6, Desai [US 2019/0303777] fails to disclose fails to disclose what Blankenship [US 2016/0283112] discloses generate the control information by performing a cyclic redundancy check (CRC) of the plurality of data bits [Par. 0044 and 0051].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to apply a method and system comprising generating CRC for data in order to determine if data is correct or not as disclosed by Blankenship into the teaching of Desai. The motivation would have been to prevent data loss.
Allowable Subject Matter
Claims 11-16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As claim 11, the prior arts fail to disclose the second morph-link circuit is configured to: compute a CRC for the streaming data in the second format over a fixed-length frame; compare the CRC to a source CRC in the control information; and identify a boundary in the plurality of data bits in the second format in response to the CRC matching the source CRC, and wherein the second morph-link circuit is configured to repeat computing a CRC, comparing a CRC and identifying a boundary for some frames but not for other frames.
As claim 12, the prior arts fail to disclose the morph-link circuit is configured to receive the streaming data in the first format at a first data rate; the first interface circuit is configured to cause transmitting the plurality of data bits in the second format at a second data rate, the second data rate being greater than the first data rate by a rate difference; and the morph-link circuit is configured to compensate for the rate difference by: transmitting dummy bits to the first interface circuit; and transmitting a valid signal to the first interface circuit via a separate channel, the valid signal indicating which bits are dummy bits.
As claim 13, the prior arts fail to disclose the morph-link circuit is configured to receive the streaming data in the first format at a variable data rate; the first interface circuit is configured to cause transmitting the plurality of data bits in the second format at a second data rate; and the morph-link circuit is configured to: transmit a variable number of dummy bits to the first interface circuit, the variable number of dummy bits corresponding to a rate difference between the variable data rate and the second data rate; and transmit a valid signal to the first interface circuit, the valid signal indicating which bits are dummy bits.
As claim 14, the prior arts fail to disclose the morph-link circuit comprises a buffer circuit configured to compensate for clock differences between a first clock signal for being utilized to provide the streaming data in the first format to the morph-link circuit and a second clock signal for being utilized by the first interface circuit for transmitting the plurality of data bits in the second format.
As claim 15, the prior arts fail to disclose the morph-link circuit is configured to receive the streaming data in the first format at a first data rate, and wherein the first interface circuit is configured to cause transmitting the plurality of data bits in the second format at the first data rate.
As claim 16, the prior arts fail to disclose the morph-link circuit is configured to operate in accordance with a first clock signal, the first interface circuit is configured to operate in accordance with a second clock signal, and a rate of the first clock signal is less than a rate of the second clock signal.
Claim 19 allowed.
As claim 19, the prior arts fail to disclose a semiconductor device, comprising: a first semiconductor die including a morph-link circuit and a first interface circuit, wherein the morph-link circuit is configured to: receive streaming data formatted in a first format according to a first protocol, the streaming data comprising a plurality of data bits in the first format and a plurality of control bits in the first format; convert the streaming data to a second format according to a second protocol, including separating the plurality of control bits from the plurality of data bits; and transmit the streaming data in the second format to the first interface circuit, wherein the morph-link circuit, configured to transmit the streaming data, is further configured to transmit the plurality of data bits in the second format via a first communication channel to the first interface circuit, and to transmit control information in the second format corresponding to the plurality of control bits via a second communication channel to the first interface circuit, wherein the first interface circuit is configured to cause: transmitting the plurality of data bits in the second format to a second interface circuit disposed outside the first semiconductor die according to the second protocol; and transmitting, separately from the plurality of data bits in the second format, the control information in the second format to the second interface circuit according to the second protocol, wherein the second protocol is different from the first protocol, wherein the second communication channel is separate and different from the first communication channel, wherein the first format comprises a bit stream format, the second format comprises a byte stream format, the streaming data in the first format comprises a plurality of parallel bit streams, and the plurality of data bits in the second format comprise a byte stream, wherein the morph-link circuit is configured to transmit a validity indicator to the first interface circuit, the validity indicator being separate from the plurality of data bits in the second format and the control information in the second format, wherein the first interface circuit is configured to cause transmitting, separately from the plurality of data bits in the second format and the control information in the second format, the validity indicator indicating whether the byte stream is valid, wherein a clock rate of the morph-link circuit is less than a clock rate of the first interface circuit, and wherein the morph-link circuit is configured to: add one or more dummy bits to the plurality of data bits in the second format; transmit the plurality of data bits in the second format including the one or more dummy bits to the first interface circuit; and transmit a valid signal to the first interface circuit, the valid signal indicating whether bits are dummy bits.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Colmant [US 2002/0196778] discloses a method and system for transmitting data and control bits via different path.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN HIEU D NGUYEN whose telephone number is (571)272-3159. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Edan Orgad can be reached at 571-272-7884. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN HIEU D NGUYEN/Primary Examiner, Art Unit 2414
Prosecution Insights