DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received
09/23/2024 for application number 18/893,743. The Office hereby acknowledges receipt of the
following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and
Claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claims 9-15 are interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
In Claim 9, such limitation is “processing logic configured to: determine when at least a first cluster of processing cores has entered a cluster clock gating state; and in response to determining that the first cluster has entered the cluster clock gating state, reduce a clock frequency used by the processing cores of the first cluster from a first clock frequency to a second clock frequency, the second clock frequency being less than the first clock frequency.”
Claims 10, 11, 12, 14, and 15 depend on Claim 9, but do not provide additional structural support for the “processing logic” of Claim 9.
In Claim 13, such limitations are:
“core power state machines being configured to perform power management for a respective processing core of said plurality of processing cores and to output a respective notification signal indicating when the respective processing core is in an idle, low power, state”
“a cluster state machine configured to perform power management for the first cluster”
“cluster power state machine is configured to determine when the first cluster has entered the cluster clock gating state by detecting when an aggregate of the notification signals has been received by the cluster power state machine indicating that all of the processing cores are in the idle, low power, state”
“cluster power state machine being configured to output an interrupt signal when the aggregate of the notification signals is received by the cluster power state machine”
“dynamic voltage and frequency scaling (DVFS) state machine configured to receive an output signal from the firmware processor in response to the firmware processor receiving the interrupt signal”
“DVFS state machine being configured to, based at least in part on the output signal received from the firmware processor, generate an output signal that causes circuitry of the cluster to select the second clock frequency and second supply voltage for use by the processing cores.”
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Regarding the term “processing logic,” paragraph 27 of the specification defines logic as digital circuits, such as digital gate structures, that are combined and configured in a particular manner to achieve one or more functions. Paragraph 66 of the specification also states that the inventive principles and concepts can also be implemented in software being executed by a processor or in a combination of software and hardware and/or firmware. As such, in light of the specification, the structure of the processing logic of Claims 9-12, 14, and 15 is interpreted as being implemented as digital circuits, of which is implemented in at least some form of software, hardware, firmware, or any combination of the three.
Regarding the terms “core power state machines,” “cluster state machine,” “cluster power state machine,” “dynamic voltage and frequency scaling (DVFS) state machine,” and “DVFS state machine,” paragraph 66 of the specification defines state machines as being implemented in hardware. Paragraph 66 also states that inventive concepts (in this case, such as state machines) can also be implemented in software being executed by a processor or in a combination of software and hardware and/or firmware. As such, in light of the specification, the structure of a “state machine” (which encompasses terms such as “core power state machines,” “cluster state machine,” “cluster power state machine,” “dynamic voltage and frequency scaling (DVFS) state machine,” and “DVFS state machine”) is interpreted as being implemented in hardware, software being executed by a processor or in a combination of software and hardware and/or firmware.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5, 6, and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 5, lines 7-8 recite, “…wherein the core power state machines send an aggregated notification to the cluster power state machine…” (emphasis added). There is insufficient antecedent basis for this limitation in the claim, as there is no mention of a core power state machine anywhere in the claim preceding the limitation. For purposes of examination, “core power state machines” is interpreted to mean “core state machines.”
Lines 7-9 recite, “…wherein the core power state machines send an aggregated notification to the cluster power state machine…” (emphasis added). There is insufficient antecedent basis for this limitation in the claim, as there is no mention of a cluster power state machine anywhere in the claim preceding the limitation. For purposes of examination, “cluster power state machine” is interpreted to mean “cluster state machine.”
Regarding Claim 6, the dependent claim inherits the deficiencies of its respective parent claim and is rejected accordingly.
Regarding Claim 13, line 8 recites, “wherein the cluster power state machine is configured to…” (emphasis added). There is insufficient antecedent basis for this limitation in the claim, as there is no mention of a cluster power state machine anywhere in the claim preceding the limitation. For purposes of examination, “cluster power state machine” is interpreted to mean “cluster state machine.” Lines 10-13 also recite “cluster power state machine” and, for the purposes of examination, will also be interpreted as “cluster state machine.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over UMEZAWA (US 2011/0302339 A1) in view of DITTY et al. (US 2019/0258251 A1).
Regarding Claim 1, UMEZAWA discloses:
A method for reducing power leakage in a system-on-a-chip (SoC) [a method, FIG. 8], the method comprising:
in response to determining that a processor has entered a clock gating state, reducing a clock frequency used by the processor from a first clock frequency to a second clock frequency [clock control unit 15 periodically cuts off a clock pulse from the clock signal CLK supplied from the PLL 40 by periodically negating the enable signal EN (i.e. entering a clock gating state), which reduces the frequency of the clock signal CLK and the operating frequency of logic unit 13 (i.e. reducing a clock frequency used by a processor from a first clock frequency to a second clock frequency in response to determining that a processor has entered a clock gating state), p. 40; logic unit 13 is a type of processing unit, p. 25],
the second clock frequency being less than the first clock frequency [the clock control unit of the input port reduces the operating frequency (i.e. clock frequency) in the clock domain 17 to 1/4 of the frequency of the clock signal CLK supplied from the PLL 40, p. 42].
UMEZAWA does not explicitly disclose determining when at least a first cluster of processing cores has entered a cluster clock gating state.
However, in the analogous art of clock gating, DITTY teaches determining when at least a first cluster of processing cores has entered a cluster clock gating state [core clusters (cores are CPU cores, p. 194) are independently clock-gated (i.e. entering a cluster clock gating state) when all cores are clock-gated, p. 195].
It would have been obvious to one of ordinary skill in the art, having the teachings of UMEZAWA and DITTY before him before the effective filling date of the claimed invention, to incorporate the method of determining when a cluster of processing cores has entered a clock gating state as taught by DITTY into the method as disclosed by UMEZAWA in order to incorporate a capability for aggressive power management [DITTY p. 195].
Regarding Claim 9, UMEZAWA discloses a power management system [data transfer apparatus, FIG. 1] for reducing power leakage in a system-on-a-chip (SoC), the system comprising: processing logic [logic unit 13, FIG. 1].
The remainder of Claim 9 recites limitations similar to those of Claim 1, and is rejected accordingly.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over UMEZAWA and DITTY as applied to Claims 1 and 9 above, and in further view of PAL
(US 2017/0038814 A1).
Regarding Claim 2, UMEZAWA and DITTY teach the method of Claim 1 as applied above.
UMEZAWA and DITTY do not explicitly teach determining when the first cluster of processing cores has exited the cluster clock gating state; and in response to determining that the first cluster has exited the cluster clock gating state, increasing the clock frequency used by the processing cores of the first cluster from the second clock frequency to the first clock frequency.
However, in the analogous art of clock gating, PAL teaches determining when a first cluster of processing cores has exited a clock gating state [internal clock paths in the one or more processors are un-gated (i.e. exiting a clock gating state), p. 112; (processors are processor cores, p. 25; i.e. cluster of processing cores)];
and in response to determining that the first cluster has exited the clock gating state, increasing the clock frequency used by the processing cores of the first cluster from the second clock frequency to the first clock frequency [after activation of the one or more processors, frequency of the clock signal is increased from the second clock frequency back to the first clock frequency approximately equal to the frequency of the input clock signal, p. 113; (processors are activated by un-gating internal clock paths, p. 112);the second clock frequency is lower than the frequency of the input clock signal, p. 111].
It would have been obvious to one of ordinary skill in the art, having the teachings of UMEZAWA, DITTY, and PAL before him before the effective filling date of the claimed invention, to incorporate the method of increasing a clock frequency in response to exiting a clock gating state as taught by PAL into the method as taught by UMEZAWA and DITTY in order to wake a processor from an idle mode used to conserve power when the processor is needed [PAL p. 4].
Regarding Claim 10, UMEZAWA and DITTY teach the system of Claim 9 as applied above.
The remainder of Claim 10 recites limitations similar to those of Claim 2, and is rejected accordingly.
Claims 3, 4, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over UMEZAWA and DITTY as applied to Claims 1 and 9 above, and in further view of RANGARAJAN et al. (US 2019/0065359 A1).
Regarding Claim 3, UMEZAWA and DITTY teach the method of Claim 1 as applied above.
UMEZAWA and DITTY do not explicitly teach in response to determining that the first cluster has entered the cluster clock gating state, reducing a supply voltage used by the processing cores of the first cluster from a first supply voltage to a second supply voltage, the second supply voltage being less than the first supply voltage.
However, in the analogous art of power saving, RANGARAJAN teaches in response to determining that the first cluster has entered the cluster clock gating state, reducing a supply voltage used from a first supply voltage to a second supply voltage, the second supply voltage being less than the first supply voltage [when clock signal Clk is gated (indicating that CPU core 115 is idle; CPU core 115 is a cluster of CPU cores, p. 13; i.e. a first cluster entering a cluster clock gating state), the trigger device 215 triggers (instructs) the controller 140 to switch the cache memory 120 from supply voltage VDD_APC (i.e. a first supply voltage) to the lower supply voltage VDD_MX (i.e. a second supply voltage), p. 28].
It would have been obvious to one of ordinary skill in the art, having the teachings of UMEZAWA, DITTY, and RANGARAJAN before him before the effective filling date of the claimed invention, to incorporate the method of reducing a supply voltage in response to clock gating as taught by RANGARAJAN into the method as taught by UMEZAWA and DITTY in order to reduce leakage power [RANGARAJAN p. 28].
Regarding Claim 4, UMEZAWA, DITTY, and RANGARAJAN teach the method of Claim 3 as applied above.
RANGARAJAN further teaches in response to determining that the first cluster has exited the cluster clock gating state, increasing the supply voltage used from the second supply voltage to the first supply voltage [when clock signal Clk is reenabled (i.e. exiting a clock gating state), trigger device 215 instructs controller 140 to switch the cache memory 120 from supply voltage VDD_MX (i.e. second supply voltage) back to supply voltage VDD_APC (i.e. first supply voltage), p. 29].
Regarding Claim 11, UMEZAWA and DITTY teach the system of Claim 9 as applied above.
The remainder of Claim 11 recites limitations similar to those of Claim 3, and is rejected accordingly.
Regarding Claim 12, UMEZAWA, DITTY, and RANGARAJAN teach the system of Claim 11 as applied above.
The remainder of Claim 12 recites limitations similar to those of Claim 4, and is rejected accordingly.
Claims 5, 6, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over UMEZAWA, DITTY, and RANGARAJAN as applied to Claims 3 and 11 above, and in further view of KOCEV (US 2012/0102344 A1) and PAWAR et al. (US 2024/0004454 A1).
Regarding Claim 5, UMEZAWA, DITTY, and RANGARAJAN teach the method of Claim 3 as applied above.
DITTY further teaches:
a plurality of processing cores [CCPLEX includes eight CPU cores (201), FIG. 8, p. 194],
and a plurality of respective core state machines, each core state machine performing power management for the respective processing core [cores support simplified power state entry sequences in software with work offloaded to microcode (i.e. core state machine performing power management for their respective processing core), p. 195].
UMEZAWA, DITTY, and RANGARAJAN do not explicitly teach a cluster state machine that performs power management for the first cluster; a firmware processor running firmware; and a dynamic voltage and frequency scaling (DVFS) state machine, and wherein the core power state machines send an aggregated notification to the cluster power state machine to notify the cluster power state machine when the processing cores are all in an idle, low power, state, and wherein the step of determining when the first cluster has entered the cluster clock gating state includes detecting that the aggregated notification has been received by the cluster power state machine.
However, in the analogous art of clock gating, KOCEV teaches a cluster state machine that performs power management for the first cluster [core I/F manager 215 (i.e. cluster state machine) asserts the PG5 signal to power-gate core interfaces 21 (i.e. performs power management; core interfaces 21 are coupled to corresponding processor cores 11, p. 37), p. 51];
wherein the core power state machines send an aggregated notification to the cluster power state machine to notify the cluster power state machine when the processing cores are all in an idle, low power, state [processor cores 11 (i.e. core power state machines) send signals to core I/F power manager 215 (i.e. cluster state machine) to indicate idleness (core inactivity is idleness, p. 50), p. 49; core I/F manager 215 determines that all of core interfaces 21 are clock-gated based on the signals sent by the processor cores, p. 51 (i.e. aggregated notification; p. 52 of the specification of the instant application indicates that the term “aggregated notification” means that a “notification is sent from each of the core PSMs … such that the cluster PSM … receives all of the notifications.”; core I/F manager 215 clock-gates processors that are idle, p. 50].
and detecting that the aggregated notification has been received by the cluster power state machine [Core I/F power manager 215 receives various signals from each of processor cores 11 (i.e. an aggregated notification has been received by the cluster power state machine), p. 49; p. 52 of the specification of the instant application indicates that the term “aggregated notification” means that a “notification is sent from each of the core PSMs … such that the cluster PSM … receives all of the notifications.”].
It would have been obvious to one of ordinary skill in the art, having the teachings of UMEZAWA, DITTY, RANGARAJAN, and KOCEV before him before the effective filling date of the claimed invention, to incorporate the cluster state machine and method of sending an aggregated notification as taught by KOCEV into the method as taught by UMEZAWA, DITTY, and RANGARAJAN in order to optimize power consumption [KOCEV p. 22].
UMEZAWA, DITTY, RANGARAJAN, and KOCEV do not explicitly teach a firmware processor running firmware; and a dynamic voltage and frequency scaling (DVFS) state machine.
However, in the analogous art of power saving techniques, PAWAR teaches:
a firmware processor running firmware [processing engine 120A and BIOS 160, FIG. 1];
and a dynamic voltage and frequency scaling (DVFS) state machine [power control circuit 130, FIG. 1].
It would have been obvious to one of ordinary skill in the art, having the teachings of UMEZAWA, DITTY, RANGARAJAN, KOCEV, and PAWAR before him before the effective filling date of the claimed invention, to incorporate the firmware processor and DVFS state machine as taught by PAVAR into the method as taught by UMEZAWA, DITTY, RANGARAJAN, and KOCEV in order to provide improved energy efficiency and conservation [PAWAR p. 2].
Regarding Claim 6, UMEZAWA, DITTY, RANGARAJAN, KOCEV, and PAWAR teach the method of Claim 5 as applied above.
KOCEV further teaches with the cluster power state machine, sending a signal from the cluster power state machine [core I/F power manager 215 (i.e. cluster state machine) asserts the CGCoreArb signal to cause core arbitration unit 22 to be clock gated, p. 51; CGCoreArb signal is received by NBFE power manager 220, FIG. 3, p. 54].
PAWAR further teaches in the firmware processor, receiving an interrupt signal, entering a power (P) state associated with a second clock frequency and a second supply voltage and outputting a signal to the DVFS state machine [mode control circuit 140 of processing engine 120 may receive an SMI interrupt (i.e. an interrupt signal) and sends a SMM save notification to the power control circuit 130 (i.e. outputting a signal to the DVFS state machine), p. 24; after receiving the save notification, the power control circuit 130 transitions the processor (processing engine 120 is part of processor 110, FIG. 1) to a low power state, p. 25; a power state indicates a voltage level and clock frequency (i.e. power (P) state associated with the second clock frequency and the second supply voltage), p. 13];
and in the DVFS state machine, receiving the signal output from the firmware processor and outputting a signal that causes circuitry of the first cluster to select the second clock frequency and second supply voltage for use by the processing cores [after receiving the save notification from processing engine 120, power control circuit 130 transitions the processor (processing engine 120 is part of processor 110, Fig. 1) to a low power state (i.e. selecting the second clock frequency and second supply voltage for use through a command (outputting a signal)), p. 25];
Regarding Claim 13, UMEZAWA, DITTY, and RAGARAJAN teach the system of Claim 11 as applied above.
The remainder of Claim 13 recites limitations similar to those of Claims 5 and 6 and is rejected accordingly.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over UMEZAWA and DITTY as applied to Claims 1 and 9 above, and in further view of KOCEV.
Regarding Claim 7, UMEZAWA and DITTY teach the method of Claim 1 as applied above.
UMEZAWA and DITTY do not explicitly teach determining whether all of the processing cores are in an idle, low power, state and whether at least one of the processing cores is in a core clock gating state, wherein in response to determining that all of the processing cores are in an idle, low power, state and that at least one of the processing cores is in a core clock gating state, a determination is made that the first cluster has entered the cluster clock gating state.
However, in the analogous art of clock gating, KOCEV teaches determining whether all of the processing cores are in an idle, low power, state and whether at least one of the processing cores is in a core clock gating state [core I/F power manager 215 determines if all core interfaces 21 (core interfaces 21 are coupled to a corresponding one of processor cores 11, p. 37) are clock-gated (core interfaces 21 are clock-gated when idle, p. 50; i.e. all of the processing cores are in an idle, low power state), p. 51],
wherein in response to determining that all of the processing cores are in an idle, low power, state and that at least one of the processing cores is in a core clock gating state, a determination is made that the first cluster has entered the cluster clock gating state [when core I/F manager 215 determines that all of core interfaces 21 are clock-gated, it may assert the CGCoreArb signal (i.e. a determination is made that the cluster has entered the cluster clock gating state), p. 51].
It would have been obvious to one of ordinary skill in the art, having the teachings of UMEZAWA, DITTY, and KOCEV before him before the effective filling date of the claimed invention, to incorporate the method of determining a clock gating state after determining cores are idle, low power and clock gated as taught by KOCEV into the method as taught by UMEZAWA and DITTY in order to control power consumption of a unit in a highly dynamic and efficient manner [KOCEV p. 22].
Regarding Claim 14, UMEZAWA and DITTY teach the system of Claim 9 as applied above.
The remainder of Claim 14 recites limitations similar to those of Claim 7, and is rejected accordingly.
Claims 8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over UMEZAWA and DITTY as applied to Claims 1 and 9 above, and in further view of HE et al. (US 2018/0284869 A1) and KOCEV.
Regarding Claim 8, UMEZAWA and DITTY teach the method of Claim 1 as applied above.
UMEZAWA and DITTY do not explicitly teach determining whether all of the processing cores are in a collapsed, low power, state and whether software aggregation is being performed at a processing core level and not at a cluster level, wherein in response to determining that all of the processing cores are in a collapsed, low power, state and that software aggregation is being performed at a processing core level and not at a cluster level, a determination is made that the first cluster has entered the cluster clock gating state.
However, in the analogous art of power saving, HE teaches determining whether all of the processing cores are in a collapsed, low power, state and whether software aggregation is being performed at a processing core level and not at a cluster level, a determination is made that the first cluster has entered the cluster clock gating state [scheduler powers off cluster if all of the processing cores in the cluster are off (i.e. processing cores are in a collapsed, low power, state); unused cores are powered off (i.e. software aggregation being performed at a processing core level and not at a cluster level), p. 44].
It would have been obvious to one of ordinary skill in the art, having the teachings of UMEZAWA, DITTY, and HE before him before the effective filling date of the claimed invention, to incorporate the method of determining a collapsed low power state and software aggregation as taught by HE into the method as taught by UMEZAWA and DITTY in order to minimize power usage [HE p. 23].
UMEZAWA, DITTY, and HE do not explicitly teach wherein in response to determining that all of the processing cores are in a collapsed, low power, state, a determination is made that the first cluster has entered the cluster clock gating state.
However, in the analogous art of power saving, KOCEV teaches wherein in response to determining that all of the processing cores are in a low power, state, a determination is made that the first cluster has entered the cluster clock gating state [when core I/F manager 215 determines that all of core interfaces 21 are clock-gated, it may assert the CGCoreArb signal (i.e. a determination is made that the cluster has entered the cluster clock gating state), p. 51; core interfaces 21 are clock-gated when idle (i.e. a low power, state), p. 50].
It would have been obvious to one of ordinary skill in the art, having the teachings of UMEZAWA, DITTY, HE, and KOCEV before him before the effective filling date of the claimed invention, to incorporate the method of determining a clock gating state after determining cores are idle, low power and clock gated as taught by KOCEV into the method as taught by UMEZAWA, DITTY, and HE in order to control power consumption of a unit in a highly dynamic and efficient manner [KOCEV p. 22].
Regarding Claim 15, UMEZAWA and DITTY teach the system of Claim 9 as applied above.
The remainder of Claim 15 recites limitations similar to those of Claim 8, and is rejected accordingly.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over DITTY in view of UMEZAWA.
Regarding Claim 16, DITTY discloses a computer program for controlling a power management system in a system-on-a-chip (SoC) to perform power management, the computer program being embodied on a non-transitory computer readable medium and comprising computer instructions for execution by one or more processors [GPU memory 2008 constitutes non-transitory memory that stores instructions (i.e. a computer program) performed by GPU 2006, p. 297];
determining when at least a first cluster of processing cores has entered a cluster clock gating state [core clusters (cores are CPU cores, p. 194) are independently clock-gated (i.e. entering a cluster clock gating state) when all cores are clock-gated, p. 195].
DITTY does not explicitly disclose in response to determining that the first cluster has entered the cluster clock gating state, reducing a clock frequency used by the processing cores of the first cluster from a first clock frequency to a second clock frequency, the second clock frequency being less than the first clock frequency.
However, in the analogous art of power management, UMEZAWA teaches in response to determining that a processor has entered a clock gating state, reducing a clock frequency used by the processor from a first clock frequency to a second clock frequency [clock control unit 15 periodically cuts off a clock pulse from the clock signal CLK supplied from the PLL 40 by periodically negating the enable signal EN (i.e. entering a clock gating state), which reduces the frequency of the clock signal CLK and the operating frequency of logic unit 13 (i.e. reducing a clock frequency used by a processor from a first clock frequency to a second clock frequency in response to determining that a processor has entered a clock gating state), p. 40; logic unit 13 is a type of processing unit, p. 25],
the second clock frequency being less than the first clock frequency [the clock control unit of the input port reduces the operating frequency (i.e. clock frequency) in the clock domain 17 to 1/4 of the frequency of the clock signal CLK supplied from the PLL 40, p. 42].
It would have been obvious to one of ordinary skill in the art, having the teachings of DITTY and UMEZAWA before him before the effective filling date of the claimed invention, to incorporate reducing a clock frequency in response to a clock gating state as taught by UMEZAWA into the computer program as disclosed by DITTY in order to save power [UMEZAWA p. 4].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over DITTY and UMEZWA as applied to Claim 16 above, and in further view of PAL.
Regarding Claim 17, DITTY and UMEZAWA teach the computer program of Claim 16 as applied above.
The remainder of Claim 17 recites limitations similar to those of Claim 2, and is rejected accordingly.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over DITTY and UMEZAWA as applied to Claim 16 above, and in further view of RANGARAJAN.
Regarding Claim 18, DITTY and UMEZAWA teach the computer program of Claim 16 as applied above.
The remainder of Claim 18 recites limitations similar to those of Claim 3, and is rejected accordingly.
Regarding Claim 19, DITTY, UMEZAWA, and RAGARAJAN teach the computer program of Claim 18 as applied above.
The remainder of Claim 19 recites limitations similar to those of Claim 4, and is rejected accordingly.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over DITTY and UMEZAWA as applied to Claim 16 above, and in further view of KOCEV.
Regarding Claim 20, DITTY and UMEZAWA teach the computer program of Claim 16 as applied above.
KOCEV teaches determining that the first cluster of processing cores has entered the cluster clock gating state by determining (1) that all of the processing cores are in an idle, low power, state and at least one of the processing cores is in a core clock gating state or (2) that all of the processing cores are in a collapsed, low power, state and that software aggregation is being performed at a processing core level and not at a cluster level [when core I/F manager 215 determines that all of core interfaces 21 are clock-gated, it may assert the CGCoreArb signal (i.e. a determination is made that the cluster has entered the cluster clock gating state), p. 51].
It would have been obvious to one of ordinary skill in the art, having the teachings of DITTY, UMEZAWA, and KOCEV before him before the effective filling date of the claimed invention, to incorporate the method of determining a clock gating state after determining cores are idle, low power and clock gated as taught by KOCEV into the method as taught by DITTY and UMEZAWA in order to control power consumption of a unit in a highly dynamic and efficient manner [KOCEV p. 22].
CONCLUSION
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/J.L.R./ Examiner, Art Unit 2175
/ANDREW J JUNG/ Supervisory Patent Examiner, Art Unit 2175
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