DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-14) in the reply filed on 7/29/2026 is acknowledged.
Claims 15-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected subject matter.
Claim Objections
Claim 9 objected to because of the following informalities: Claim 9 states, “see metal layer”, this should state “seed metal layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 & 11-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gozu et al. (US PG. Pub. 2017/0359891).
Regarding claim 1 – Gozu teaches a printed circuit board (fig. 1A, 1 [paragraph 0025] Gozu states, “a wiring substrate 1”), comprising: a first insulating layer (10 [paragraph 0025] Gozu states, “an insulating layer 10”); and a plurality of first metal patterns (20 [paragraph 0025] Gozu states, “a wiring layer 20”) disposed on the first insulating layer (10), wherein the first insulating layer (10) includes at least one recessed portion (10y [paragraph 0030] Gozu states, “depressions 10y”), the at least one recessed portion (10y) is disposed between the plurality of first metal patterns (20), and each of the plurality of first metal patterns (20) includes a first seed metal layer (21 [paragraph 0047] Gozu states, “metal film 21 include, for example, titanium”; titanium is the material used in the instant application and appears to meet the limitation “a first seed metal layer”) disposed on the first insulating layer (10), a second seed metal layer (22 [paragraph 0037] Gozu states, “metal film 33 is a so-called seed layer”) disposed on the first seed metal layer (21), and a metal pattern layer (23 [paragraph 0037] Gozu states, “metal film 23”) disposed on the second seed metal layer (22).
Regarding claim 2 – Gozu teaches the printed circuit board according to claim 1, wherein the first seed metal layer (fig. 1A, 21) includes titanium (Ti) ([paragraph 0047] Gozu states, “metal film 21 include, for example, titanium”), the second seed metal layer (22) includes copper (Cu) ([paragraph 0038] Gozu states, “Suitable materials for the metal film 22 and the metal film 23 include, for example, copper”), and the metal pattern layer (23) includes copper (Cu) (discussed in quoted paragraph 0038 above).
Regarding claim 3 – Gozu teaches the printed circuit board according to claim 1, wherein the plurality of first metal patterns (fig. 1A, 20) are disposed on a first surface (10a-1) of the first insulating layer (10), and the metal pattern layer (23) is thicker ([paragraph 0048] Gozu states, “The thickness of the metal film 23 may be, for example, approximately 1 μm to approximately 6 μm”) than each of the first (21 [paragraph 0047] Gozu states, “The thickness of the metal film 21 may be, for example, approximately 20 nm to approximately 100 nm”) and second seed metal layers (22 [paragraph 0047] Gozu states, “The thickness of the metal film 22 may be, for example, approximately 100 nm to approximately 500 nm”).
Regarding claim 4 – Gozu teaches the printed circuit board according to claim 3, wherein the first insulating layer (fig. 1A, 10) includes a step portion (10a-3) between the first surface (10a-1) of the first insulating layer (10) in a first region in which the plurality of first metal patterns (20) are disposed and the first surface (10a-2) of the first insulating layer (10) in a second region in which the at least one recessed portion is disposed (claimed step portion and first and second regions shown in figure 1A).
Regarding claim 5 – Gozu teaches the printed circuit board according to claim 3, wherein the first surface (figs. 1A-1B, 10a-2) of the first insulating layer (10) in a region in which the at least one recessed portion (10y) is disposed has a surface roughness ([paragraph 0054] Gozu states, “The surface roughness Ra of the bottom surface 10a-2 and the inner wall surfaces 10a-3 of the depression 10y may be, for example, approximately 50 nm to approximately 100 nm”) higher than that of the first surface (10a-1) of the first insulating layer (10) in a region in which the plurality of first metal patterns (20) are disposed ([paragraph 0066] Gozu states, “The upper end face 10a-1 of the projection 10x contacting the metal film 21 is a smooth surface having a smaller roughness than the bottom surface 10a-2”).
Regarding claim 11 – Gozu teaches the printed circuit board according to claim 3, further comprising: a second insulating layer (fig. 1A, 30 [paragraph 0040] Gozu states, “The insulating layer 30 is formed on the insulating layer 10 to cover the wiring layer 20 and fill in the depression 10y”) disposed on the first surface (10a-2 & 10a-1) of the first insulating layer (110) and covering at least a portion of each of the plurality of first metal patterns (20); and a plurality of third metal patterns (40 [paragraph 0041] Gozu states, “wiring layer 40”) disposed on a third surface (upper surface) of the second insulating layer (30).
Regarding claim 12 – Gozu teaches the printed circuit board according to claim 1, wherein the at least one recessed portion (figs. 1A-1B, 10y) has a fourth surface (bottom surface of recess including surface 10a-2) and a fifth surface (side wall 10a-3) that are substantially angled with each other (see approximately 90 degree angle between the two surfaces and appears to meet the limitation as described in the instant application in paragraph 0042).
Regarding claim 13 – Gozu teaches the printed circuit board according to claim 12, wherein the at least one recessed portion (Gozu; figs. 1A-1B, 10y) has a substantially constant depth (the depth D1 [see D1 description in paragraph 0033] appears constant in figure 1A).
Regarding claim 14 – Gozu teaches the printed circuit board according to claim 1, wherein the plurality of first metal patterns (fig. 1A, 20) includes a plurality of microcircuit patterns having an L (Line)/S (Space) that is 5 μm/5 μm or less ([paragraph 0034] Gozu states, “The line/space of the wiring layer 20 may be, for example, approximately 2 μm/2 μm to approximately 5 μm/5 μm”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gozu et al. in view of Sakamoto et al. (US PG. Pub. 2016/0066423).
Regarding claim 6 – Gozu teaches the printed circuit board according to claim 3 but fails to teach wherein the at least one recessed portion penetrates through a portion of the first insulating layer in a thickness direction from the first surface of the first insulating layer between the plurality of first metal patterns.
Sakamoto teaches a printed circuit board (fig. 1, 1A [paragraph 0027] Sakamoto states, “a printed wiring board (1A)”) having at least one recessed portion (see recessed portion with via 38 therein) and wherein the at least one recessed portion penetrates through a portion of the first insulating layer (26 [paragraph 0033] Sakamoto states, “insulating layer 26”) in a thickness direction from the first surface of the first insulating layer (26) between the plurality of first metal patterns (32 [paragraph 0038] Sakamoto states, “conductor patterns 32”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having the first insulating layer and recessed portions and adjacent metal patterns thereon as taught by Gozu with the recessed portion penetrating through a portion of the first insulating layer between the first metal patterns as taught by Sakamoto because these through hole via connections will allow for higher circuit density/space efficiency, mechanical strength and high current capacity within a multilayer PCBs.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gozu et al. in view of Kagohashi (US PG. Pub. 2023/0319986).
Regarding claim 7 – Gozu teaches the printed circuit board according to claim 3, but fails to teach further comprising: a plurality of second metal patterns disposed on a second surface of the first insulating layer; at least one via pattern filling at least one via hole penetrating a first region of the first insulating layer between the first surface and the second surface of the first insulating layer, wherein the first region of the first insulating layer is between at least some portions of each of the plurality of first and second metal patterns, wherein the at least one via pattern includes: the first seed metal layer disposed on a wall surface of the via hole and at least a portion of the plurality of second metal patterns, the second seed metal layer disposed on the first seed metal layer, and the metal pattern layer disposed on the second seed metal layer and filling at least a portion of the via hole.
Kagohashi teaches a printed circuit board (fig. 1, 2 [paragraph 0017] Kagohashi states, “printed wiring board 2”) comprising: a plurality of second metal patterns (10 [paragraph 0019] Kagohashi states, “The first conductor layer 10 includes a signal wiring 12 and a pad 14”) disposed on a second surface (bottom surface) of the first insulating layer (20 [paragraph 0020] Kagohashi states, “insulating layer 20”); at least one via pattern (40 [paragraph 0023] Kagohashi states, “via conductor 40”) filling at least one via hole (26 [paragraph 0023] Kagohashi states, “the opening 26”) penetrating a first region (see region having via hole 26 therein) of the first insulating layer (20) between the first surface (top surface) and the second surface (bottom surface) of the first insulating layer (20), wherein the first region of the first insulating layer (20) is between at least some portions of each of the plurality of first (30 [paragraph 0022] Kagohashi states, “The second conductor layer 30 includes a first signal wiring 32, a second signal wiring 34, and a land 36”) and second (10) metal patterns, wherein the at least one via pattern (40) includes: the first seed metal layer (31a [paragraph 0050] Kagohashi states, “each of the first layers (11a, 31a) of the seed layers (10a, 30a) is formed of any one metal of aluminum, titanium”) disposed on a wall surface (27 [paragraph 0023] Kagohashi states, “inner wall surface 27”) of the via hole (40) and at least a portion of the plurality of second metal patterns (10), the second seed metal layer (31b [paragraph 0022] Kagohashi states, “The second layer (31b) is formed of copper”) disposed on the first seed metal layer (31a), and the metal pattern layer (30b [paragraph 0044] Kagohashi states, “The electrolytic plating layer (30b) is formed of copper”) disposed on the second seed metal layer (31b) and filling at least a portion of the via hole (claimed structure shown in figures 1 and 2).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having the first metal patterns disposed on the first insulating layer as taught by Gozu with the inclusion of a plurality of second metal patterns on a second surface of the first insulating layer and a via pattern having the first and second seed layers and the metal pattern layer therein to connected to the second metal patterns as taught by Kagohashi states, “The via conductor 40 connects the first conductor layer 10 and the second conductor layer 30. In FIG. 1, the via conductor connects the pad 14 and the land 36… even when the via conductor is formed of the sputtered seed layer (30a) and the electrolytic plating layer (30b), a printed wiring board 2 with high connection reliability can be provided” [paragraph 0023 & 0047]. These through hole via connections will allow for higher circuit density/space efficiency, mechanical strength and high current capacity within a multilayer PCBs
Regarding claim 8 - Gozu in view of Kagohashi teach the printed circuit board according to claim 7, wherein a first portion (Kagohashi; fig. 1, upper portion of second metal patterns 10) of the plurality of second metal patterns (10) directly contacts the first seed metal layer (31a).
Regarding claim 9 - Gozu in view of Kagohashi teach the printed circuit board according to claim 8, wherein the first portion (Kagohashi; fig. 1, upper portion of second metal patterns 10) overlaps the first seed metal layer (31a), the second seed metal layer (31b), and the metal pattern layer (30b), in order (claimed structure shown in figures 1 and 2 of Kagohashi).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gozu et al. in view of Kagohashi et al. as applied to claim 7 above, and further in view of Furutani (US PG. Pub. 2024/0008176).
Regarding claim 10 – Gozu in view of Kagohashi teach the printed circuit board according to claim 7 but fails to explicitly teach wherein a second portion of the plurality of second metal patterns overlaps adjacent first metal patterns among the plurality of first metal patterns.
Furutani teaches a printed circuit board (fig. 1, 1) wherein a second portion (wirings 12 shown below wirings FW1 and FW2) of the plurality of second metal patterns (12) overlaps ([paragraph 0034] Furutani states, “a conductor layer 12 on a one-layer lower side each have a plane layer (12PL) at a position overlapping the first wirings (FW1) in a plan view”) adjacent first metal patterns (FW1 & FW2 [paragraph 0034] Furutani states, “first wirings (FW1)…second wirings (FW2)”) among the plurality of first metal patterns (FW1 & FW2).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having the first metal patterns and the second metal patterns connected by a via as taught by Gozu in view of Kagohashi with the second metal patterns also overlapping adjacent first metal patterns as taught by Furutani because Furutani states regarding this overlapping feature, “the conductor layers 12 adjacent to the upper side and lower side of the first wirings (FW1) have plane layers (12PL) that overlap the first wirings (FW1) in a plan view. It is thought that relatively good signal transmission can be realized also by the first wirings (FW1)” [paragraph 0046].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mizutani (US Patent 10804210) discloses wiring board.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
Prosecution Insights