DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16 have been considered but are moot because of the new ground of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The new limitations added to claim 7 are not supported by the original disclosure and constitute new matter, namely, “n random access addresses received consecutively, where n is an integer greater than 1, a dummy clk indicating a number of dummy clock cycles, where the number is a number greater than or equal to 0; and output data read respectively according to the n random access addresses which are output consecutively in the order of the received access addresses, where the following read transmission does not comprise any command value.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4, 6, 14, is/are rejected under 35 U.S.C. 103 as being unpatentable over Zitlaw (US 2007/0245071) and JP 2009508283 (hereinafter JP283; Relying on the most relevant portions of the attached English Machine Translation).
Regarding claim 1, Zitlaw discloses a method for reading a NOR memory [¶0007: NOR memory], comprising: consecutively receiving at least two random access addresses in a random read mode [Claim 18: generating serial memory addresses and receiving random access memory addresses]; and consecutively outputting data read according to the received access addresses [Claim 1, 18: selecting random memory address in accessing the data register for outputting the accessed data, data multiplexer output randomly accessed data in response to the input address].
JP283 discloses the NOR memory having an access interface using a SPI protocol, the access interface comprising at least one data/address multiplexing line [See Drawing Description].
It would have been obvious to one of ordinary skill in the art to have a NOR memory having an access interface using a SPI protocol, the access interface comprising at least one data/address multiplexing line in order to provide precharge method for a flash memory having serial input/output interface (Background Section).
Regarding claim 2, Zitlaw discloses the method according to claim 1, wherein, the random read mode is initiated by a predetermined command value [Claim 1: the data multiplexer adapted to output randomly accessed data in response to input address and state of select signal].
Regarding claim 4, ZItlaw discloses the method according to claim 1, wherein the random read mode is initiated by value of a designated register in the NOR memory [Claim 18: accessing the register with the selected address such that when the externally provided random access memory address is the selected address].
Regarding claim 6, Zitlaw discloses the method according to claim 2, wherein the random read mode is a continuous read mode which includes at least two continuous read transmissions, wherein each read transmission comprises at least two random access addresses received consecutively and data outputted consecutively [Claim 1, 18]; wherein the data is read according to the corresponding received access addresses [Claim 1, 18].
Regarding claim 14, ZItlaw discloses the method according to claim 1, wherein the random read mode is a continuous read mode which includes at least two continuous read transmissions, wherein each read transmission includes at least two random access addresses received consecutively and data outputted consecutively; wherein the data is read according to the corresponding received access addresses [Claim 1, 18].
Claim(s) 3, 5, 7-8, 12-13, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zitlaw (UA 2007/0245071); JP283; and JP 3540777 (hereinafter JP071, relying on the most relevant portion of the PE2E machine generated English translation).
Regarding claim 3, Zitlaw discloses the method according to claim 1, but does not explicitly disclose wherein, the random read mode comprises: a predetermined command value indicating the random read mode initiated, n random access addresses received consecutively, where n is an integer greater than 1, dummy clk indicating a number of dummy clock cycles, where the number is a number greater than or equal to 0, output data read respectively in response to the n random access addresses, which are output consecutively in the order of the received access addresses.
JP777, however, discloses wherein, , the random read mode comprises: a predetermined command value indicating the random read mode initiated, n random access addresses received consecutively, where n is an integer greater than 1, dummy clk indicating a number of dummy clock cycles, where the number is a number greater than or equal to 0, output data read respectively in response to the n random access addresses, which are output consecutively in the order of the received access addresses [FIG. 1-22, Description Section].
It would have been obvious to one of ordinary skill in the art to have the random read mode transmission being represented by a combination of cmd, address, data, dummy clock cycle and other relater parameters in order to provide a nonvolatile semiconductor memory device capable of performing smooth high-speed reading by minimizing a waste time generated when switching word lines (Summary of Invention).
Regarding claim 5, JP777 discloses the method according to claim 4, wherein, the random read mode comprises n random access addresses received consecutively, where n is an integer greater than 1, dummy clk indicating a predetermined number of dummy clock cycles, where the predetermined number is a number greater than or equal to 0, output data represent data read respectively according to the n random access addresses, which are output consecutively in the order of the access addresses received [FIG. 1-22, Description Section].
Regarding claim 7, JP777 discloses the method according to claim 6, wherein, the first read transmission comprises a predetermined command value indicating the random read mode is initiated, n random access addresses received consecutively, where n is an integer greater than 1, dummy clk indicating a predetermined number of dummy clock cycles, where the predetermined number is a number greater than or equal to 0, output data read respectively according to the n random access addresses, which are output consecutively in the order of the received access addresses, wherein the following read transmission comprises n random access addresses received consecutively, where n is an integer greater than 1, a dummy clk indicating a number of dummy clock cycles, where the number is a number greater than or equal to 0; and output data read respectively according to the n random access addresses which are output consecutively in the order of the received access addresses, where the following read transmission does not comprise any command value [FIG. 1-22, Description Section].
Regarding claim 8, JP777 discloses the method according to claim 3, wherein, the number of n or the number of dummy clock cycles is predetermined, or determined according to the command value or a value of a designated register, that is set in advance, in the NOR memory [FIG. 1-22, Description Section].
Regarding claim 12, JP777 discloses the method according to claim 3, wherein the length of time for reading data according to the access address address_1 is less than the length of time for transmitting the n random access addresses, and the length of time for the dummy clk is 0 [FIG. 1-22, Description Section].
Regarding claim 13, JP777 discloses the method according to claim 1, wherein, the random read mode comprises: a parameter indicating the random read mode is initiated, n random access addresses received consecutively, where n is an integer greater than 1, a dummy clk indicating a number of dummy clock cycles, where the number is a number greater than or equal to 0, output data read respectively according to the n random access addresses, which are output consecutively in the order of the received access addresses [FIG. 1-22, Description Section].
Regarding claim 15, JP777 discloses the method according to claim 1, wherein the random read mode is a continuous read mode which includes at least two continuous read transmissions, wherein the first read transmission comprises: a parameter indicating the random read mode is initiated, n random access addresses received consecutively, where n is an integer greater than 1, a dummy clk indicating a number of dummy clock cycles, where the number is a number greater than or equal to 0 [FIG. 1-22, Description Section]; and output data read respectively according to the n random access addresses, which are output consecutively in the order of the received access addresses [FIG. 1-22, Description Section]; wherein the second read transmission comprises: n random access addresses received consecutively, where n is an integer greater than 1, a dummy clk indicating a number of dummy clock cycles, where the number is a number greater than or equal to 0 [FIG. 1-22, Description Section]; and output data read respectively according to the n random access addresses, which are output consecutively in the order of the received access addresses [FIG. 1-22, Description Section].
Claim(s) 9, 10, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zitlaw (UA 2007/0245071), JP283 and Springberg et al. (US 2020/0133563).
Regarding claim 9, Zitlaw discloses the method according to claim 1, but does not explicitly wherein, the read operation performed in response to receiving the at least one of access addresses is a burst read operation, the burst length for each access address or a default burst length is predetermined, or determined by a value of a designated register, that is set in advance, in the NOR memory.
Springberg et al., however, discloses wherein, the read operation performed in response to receiving the at least one of access addresses is a burst read operation, the burst length for each access address or a default burst length is predetermined, or determined by a value of a designated register, that is set in advance, in the NOR memory [¶0013, 0051].
Springberg, however, discloses wherein, the read operation performed in response to receiving the at least one of access addresses is a burst read operation, the burst length for each access address or a default burst length is predetermined, or determined by a value of a designated register, that is set in advance, in the NOR memory in order to provide data to be stored at the memory sub-system and request data to be retrieved from the memory sub-system (¶0012).
Regarding claim 10, Springberg discloses the method according to claim 1, wherein, at least two of the received access addresses include at least two access addresses belonging to different dies, and each of the access addresses includes at least one bit of information indicating the die the access address belongs to [FIG. 6].
Regarding claim 16, the rationale in the rejection of claim 1 is herein incorporated. ZItlaw further discloses a NOR memory comprising: an access interface for communicating information with the outside of the NOR memory [FIG. 7, 1]; and a control module configured to control a read operation to the NOR memory arrays according to information received from the access interface, so as to implement the method according to claim 1.
Springberg further discloses one or more NOR memory arrays fabricated on one or more dies [FIG. 7, ¶0007: memory array];
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zitlaw (UA 2007/0245071), JP283, and TW 201506952 (hereinafter TW952, relying on the most relevant portions of the PE2E English machine translation).
Regarding claim 11, Zitlaw discloses the method according to claim 1, but does not explicitly disclose wherein, the NOR memory has an access interface using a SPI protocol; and/or the NOR memory has a single-port, dual-port, four-port or eight-port access interface; and/or the NOR memory adopts SDR timing to receive the access addresses and output the read data.
TW952, however, discloses wherein, the NOR memory has an access interface using a SPI protocol [Abstract, Description: SPI interface protocol, NOR flash memory]; and/or the NOR memory has a single-port, dual-port, four-port or eight-port access interface [Abstract, Description: SPI interface protocol, NOR flash memory]; and/or the NOR memory adopts SDR timing to receive the access addresses and output the read data [Abstract, Description: SPI interface protocol, NOR flash memory].
It would have been obvious to one of ordinary skill in the art to have the NOR memory has an access interface using a SPI protocol; and/or the NOR memory has a single-port, dual-port, four-port or eight-port access interface; and/or the NOR memory adopts SDR timing to receive the access addresses and output the read data in order to allow NOR flash memory to be code-shadowed into random access memory (RAM) (Description).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Navon (US10719445) disclose NOR memory, random read mode.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARDOCHEE CHERY whose telephone number is (571)272-4246. The examiner can normally be reached from 900-500.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at (571)270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Respectfully Submitted,
USPTO
Dated: May 1, 2026 By: /MARDOCHEE CHERY/
Primary Examiner
Art Unit 2133
Email:Mardochee.Chery@uspto.gov Telephone: 571-272-4246
Facsimile: 571-273-4246
Prosecution Insights