CTFR 18/894,152 CTFR 79440 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 2. Claim s 1-4, 7-8, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Freking et al. (Pub. No. US20130346665) in view of Fuxa et al. (Pub. No. US20170046075) As per claim 1, Freking discloses an interface (fig.1, PCIe interface 125) to adjust a storage setup based on at least one of speed and capacity (paragraph 46, increase the lane width and transmit data faster) , the interface comprises: a controller (fig.2, bus controller 215 and 220) to manage downstream peripheral component interconnect express (PCle) lane configurations (paragraph 49, lines 2-3, he system 400 is configured such that bus controller 215 and 220 transfer data between MAC and PHY interfaces 120, 125 using a 2.times.16 lane configuration) a splitter (fig.4, the system 405) to split a PCle lane into multiple configurations based on a configuration of the controller (paragraph 50, the system 405 perform lane fusing where the configuration logic instructs both bus controllers 215, 220 to use one or more hardware modules to implement a lane configuration with wider PCIe links.) Freking discloses all the limitations as the above but does not explicitly disclose the adapter to adjust of speed and capacity, the adapter comprises convert a first PCIe lane configuration including a first number of storages devices that are connected to a first number of the storage devices that are connected to a second number of PCIe lanes to adjust the storage setup based on at least one of speed and capacity, wherein the first number of storage devices is different from the second number of the storage devices and the first number of the PCIe lanes is different from the second number of the PCIe lanes. However, Fuxa discloses this. (paragraph 23, manage and reduce total power used by the storage controller 204 by adjusting or reducing the utilized number of PCIe lanes 214, and/or by adjusting or lowering negotiated PCIe generation (speed) through the lanes 214 and the storage controller. The server 100 may alter PCIe settings to reduce the number of active lanes from the interconnect 102 to the I/O device 104 to provide bandwidth below capability but that satisfies demand as further cited in paragraph 16.) It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Fuxa with the teaching of Freking so as to add more storage so as to yield the predicatable result so as to control efficiently, thus enhance the system performance. As per claim 2, Freking discloses wherein the first PCIe lane configuration is a configuration of one storage device to four PCIe U.2 lanes (1x4) and the adapter converts the first PCle lane configuration to the second PCle lane configuration. (paragraph 21, lines 1-2, PCIe devices may be configured to operate in a plurality of different PCIe link widths (i.e., times.1, times.2, times.4, times.8, times.16, times.32, etc.) by transmitting data serially along the different lanes.) As per claim 3, Fuxa discloses wherein the second PCle lane configuration includes two separate PCle lanes, each with a configuration of two storage devices to two PCle lanes. (paragraph 32, the storage controller 204 having 8 Gen-3 PCIe lanes on the front end (to interconnect lanes 214) and 2 direct attached drives 210 in a RAID-1 configuration on the backend capable of 275 MB/sec each.) As per claim 4, Fuxa discloses wherein the second PCle lane configuration includes four separate PCle U.2 lanes, each with a configuration of four storage devices to one PCle U.2 lane (4x1). (paragraph 32, the storage controller 204 having 8 Gen-3 PCIe lanes on the front end (to interconnect lanes 214) and 2 direct attached drives 210 in a RAID-1 configuration on the backend capable of 275 MB/sec each.) As per claim 7, Freking discloses the interface further comprising a memory programmed to configure the PCle lane according to a desired setup. (paragraph 76, lines 6-7, when a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. The different lane configurations share the same lanes (and wires) of the bus as the other lane configurations.) As per claim 8, Fuxa discloses the interface further comprising a power delivery controller to deliver power to the controller. (paragraph 50, lines 10-12, the storage controller 204 could be set to give the slowest speed and the minimum or no lanes to give the lowest power settings or consumption of the storage controller 204.) As per claim 10, Fuxa discloses wherein the controller manages up to four PCIe lane configurations downstream. (paragraph 50, lines 10-12, the storage controller 204 could be set to give the slowest speed and the minimum or no lanes to give the lowest power settings or consumption of the storage controller 204.) 07-21-aia AIA 3. Claim s 5-6, 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Freking et al. (Pub. No. US20130346665) in view of Fuxa et al. (Pub. No. US20170046075) and further in view of Reinke et al. (Pub. No. US20120033370) As per claims 11 and 17, Freking an adapter (fig.1, PCIe interface 125) to adjust a storage setup based on at least one of speed and capacity (paragraph 6, change from a first lane configuration to a second lane configuration and paragraph 46, increase the lane width and transmit data faster.) , the adapter comprises: a set of slots to insert storage devices (paragraph 8, lines 17-18, he external bus couples to both the first and second computing devices.) Freking discloses all the limitations as the above but does not explicitly disclose the adapter to adjust of speed and capacity, the adapter comprises convert a first PCIe lane configuration including a first number of storages devices that are connected to a first number of the storage devices that are connected to a second number of PCIe lanes to adjust the storage setup based on at least one of speed and capacity, wherein the first number of storage devices is different from the second number of the storage devices and the first number of the PCIe lanes is different from the second number of the PCIe lanes. However, Fuxa discloses this. (paragraph 23, manage and reduce total power used by the storage controller 204 by adjusting or reducing the utilized number of PCIe lanes 214, and/or by adjusting or lowering negotiated PCIe generation (speed) through the lanes 214 and the storage controller. The server 100 may alter PCIe settings to reduce the number of active lanes from the interconnect 102 to the I/O device 104 to provide bandwidth below capability but that satisfies demand as further cited in paragraph 16.) It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Fuxa with the teaching of Freking so as to add more storage so as to yield the predicatable result so as to control efficiently, thus enhance the system performance. Freking in view Fuxa disclose all the limitation as the above but do not explicitly disclose an upstream connection to a PCle male connector and downstream connections to PCle female connectors. However, Reinke discloses this. (paragraph 24, a female connector 25 that forms part of each interface port 24 on the interface cards 14 of FIGS. 2A and 2B, and FIG. 2D represents one end of the cable 18 and a male connector 32 affixed thereto for connecting to the female connector 25 of the interface card 14.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the male and female connector as shown in Reinke with the teaching of Freking in view Fuxa so as it would have performed the same function as to protection, secure connection, and assembly standardization, mechanisms ensure that components are installed correctly and securely. As per claims 5, 14, and 18, Reinke discloses wherein the adapter connects to a PCIe male connector as an upstream connection . (paragraph 24, a female connector 25 that forms part of each interface port 24 on the interface cards 14 of FIGS. 2A and 2B, and FIG. 2D represents one end of the cable 18 and a male connector 32 affixed thereto for connecting to the female connector 25 of the interface card 14.) As per claims 6, 15 and 19, Reinke discloses wherein downstream connections on the adapter are PCle female connectors. (paragraph 24, a female connector 25 that forms part of each interface port 24 on the interface cards 14 of FIGS. 2A and 2B, and FIG. 2D represents one end of the cable 18 and a male connector 32 affixed thereto for connecting to the female connector 25 of the interface card 14.) As per claim 12, Fuxa discloses wherein the first PCIe lane configuration is a configuration of one storage device to four PCIe U.2 lanes (1x4) and the adapter converts the first PCle lane configuration to the second PCle lane configuration including two separate PCIe lanes, each with a configuration to the second PCIe lane configuration including two separate PCIe lanes, each with a configuration of two storage devices to two PCIe lanes. (paragraph 32, the storage controller 204 having 8 Gen-3 PCIe lanes on the front end (to interconnect lanes 214) and 2 direct attached drives 210 in a RAID-1 configuration on the backend capable of 275 MB/sec each.) As per claim 13, Fuxa discloses wherein the first PCIe lane configuration is a configuration of one storage device to four PCIe U.2 lanes (1x4) and the adapter converts the first PCle lane configuration to the second PCle lane configuration including four separate PCIe lanes, each with a configuration to the second PCIe lane configuration including four separate PCIe lanes, each with a configuration of four storage devices to two PCIe lanes. (paragraph 32, the storage controller 204 having 8 Gen-3 PCIe lanes on the front end (to interconnect lanes 214) and 2 direct attached drives 210 in a RAID-1 configuration on the backend capable of 275 MB/sec each.) As per claim 16, Freking discloses wherein the first PCIe lane configuration is a configuration of one storage device to four PCIe U.2 lanes (1x4) and the adapter converts the first PCle lane configuration to the second PCle lane configuration. (paragraph 21, lines 1-2, PCIe devices may be configured to operate in a plurality of different PCIe link widths (i.e., times.1, times.2, times.4, times.8, times.16, times.32, etc.) by transmitting data serially along the different lanes.) As per claim 20, Freking discloses wherein a first PCIe lane configuration including a one storage device to four PCle U.2 lanes (1x4) configuration is provided by a controller and is used for the one storage device to four PCle lanes (1x4) connector. (paragraph 21, lines 1-2, PCIe devices may be configured to operate in a plurality of different PCIe link widths (i.e., times.1, times.2, times.4, times.8, times.16, times.32, etc.) by transmitting data serially along the different lanes.) 07-21-aia AIA 4. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Freking et al. (Pub. No. US20130346665) in view of Fuxa et al. (Pub. No. US20170046075) and further in view of Subramanian et al. (Pub. No. US20240330210) As per claim 9, Freking in view of Skirmonti discloses all the limitations as the above but do not explicitly disclose the interface further comprising a type C connector to connect the interface to a host. However, Subramanian discloses this. (paragraph 17, lines 1-6, display data is sent over a Type C connector either as tunneled traffic or native traffic which is separate from the PCIe link and doesn't require PCIe bandwidth.) It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Subramanian with the teaching of Freking in view of Fuxa so as to provide system with faster data transfer speeds, higher power delivery for charging, and the ability to carry various data protocols to make system more efficient, thus enhance the system performance . Response to Amendment 5. Applicant's amendment filed on 2/2/2026 have been fully considered but are moot in view of the new ground(s) of rejection. 07-96 AIA 6. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Livne [Pub. No. US20230056330] discloses Other PCIe link widths may be used, and the 16 (or other number of) lanes may be split to communicate with multiple PCIe endpoint devices . Conclusion 07-39 AIA 7. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Contact Information 8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV]. The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K. T. H./ Examiner, Art Unit 2184 /HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184 Application/Control Number: 18/894,152 Page 2 Art Unit: 2184 Application/Control Number: 18/894,152 Page 3 Art Unit: 2184 Application/Control Number: 18/894,152 Page 4 Art Unit: 2184 Application/Control Number: 18/894,152 Page 5 Art Unit: 2184 Application/Control Number: 18/894,152 Page 6 Art Unit: 2184 Application/Control Number: 18/894,152 Page 7 Art Unit: 2184 Application/Control Number: 18/894,152 Page 8 Art Unit: 2184 Application/Control Number: 18/894,152 Page 9 Art Unit: 2184 Application/Control Number: 18/894,152 Page 10 Art Unit: 2184
Prosecution Insights