DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING OXIDE SEMICONDUCTOR LYAER ON PLANARIZED METAL OXIDE LAYER AND METHOD FOR MANUFACTURING THE SAME
Claim Objections
Claims 8 and 13 are objected to because of the following informalities:
Regarding claim 8, “the following formula.” should be changed to, as a suggestion, “the following formula:”.
Regarding claim 13, “a field effect mobility” should be changed to “the field effect mobility µ”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, the limitation “wherein a relationship between an arithmetic mean roughness Ra (nm) of a surface of the metal oxide layer and a field effect mobility μ (cm2/Vs) is expressed by the following formula. μ = −10.033Ra + 48.23 (Where the arithmetic mean roughness Ra ≤ 0.80 nm)” would render the claim indefinite since it is unclear to one skilled in the art why the given mathematical formula equates the terms with mismatched units: the field effect mobility on the left side is expressed in (cm2/Vs) (i.e., “μ”) and the arithmetic mean roughness Ra on the right side is expressed in (nm) with additional number (i.e., “−10.033Ra + 48.23”). Furthermore, assuming Ra = 0.80nm as the maximum value as an example (“Ra ≤ 0.80 nm”), isn’t the right side of the formula -10.033(0.8 x 10-9) + 48.23 = about 48.23 with Ra = 0.8 x 10-9m since “-10.033(0.8 x 10-9)” is relatively small number compared to “48.23”? How do the units affect the formula? Claims 9-13, which depend from claim 1, are also rejected by virtue of their dependencies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 8, and 10-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hizuka et al. (JP 2013157359 A with English Translation; hereinafter “Hizuka”).
Regarding claim 1, Hizuka teaches a method for manufacturing a semiconductor device, the method comprising steps of: forming a first metal oxide layer containing aluminium as a main component (a base insulating layer formed of aluminum oxide, not shown) above an insulating surface (a substrate 400 having an upper surface and formed of glass) (pages 3-4); performing a planarization process on a surface of the first metal oxide layer (a planarization process on the base insulating layer such that the base insulating layer has an average surface roughness Ra 0.3nm or less) (pages 8); forming an oxide semiconductor layer (an oxide semiconductor film 403) on the insulating surface on which the planarization process is performed (Fig. 1 and pages 4--8); forming a gate insulating layer (a gate insulating layer 402) above the oxide semiconductor layer (Fig. 2 and pages 11-12); and forming a gate electrode (a gate electrode layer 401) facing the oxide semiconductor layer above the gate insulating layer (Fig. 2 and page 12).
Regarding claim 2, Hizuka teaches wherein the planarization process makes an arithmetic mean roughness Ra of a surface of the first metal oxide layer less than 0.80 nm (page 8).
Regarding claim 8, referring to Fig. 2, Hizuka teaches a semiconductor device comprising: a metal oxide layer containing aluminium as a main component (a base insulating layer formed of aluminum oxide, not shown) above an insulating surface (a substrate 400 having an upper surface and formed of glass) (pages 3-4); an oxide semiconductor layer (an oxide semiconductor film 403) on the metal oxide layer (pages 4--8); a gate electrode (a gate electrode layer 401) facing the oxide semiconductor layer (page 12); and a gate insulating layer (a gate insulating layer 402) between the oxide semiconductor layer and the gate electrode (pages 11-12); wherein a relationship between an arithmetic mean roughness Ra (nm) of a surface of the metal oxide layer and a field effect mobility μ (cm2/Vs) is expressed by the following formula. μ = −10.033Ra + 48.23 (Where the arithmetic mean roughness Ra ≤ 0.80 nm) (See the rejection of claim 8 under 35 U.S.C. 112(b) as discussed above. For the given formula in claim 1, the given units are considered as not affecting the formular calculation. As such, with the base insulating layer having an average surface roughness Ra 0.3nm, μ = −10.033Ra + 48.23 = −10.033(0.3) + 48.23 = 45.2) (pages 8).
Regarding claim 10, Hizuka teaches wherein the metal oxide layer has a barrier property against oxygen and hydrogen (the base insulating layer formed of aluminum oxide would have the barrier property against oxygen and hydrogen with the material choice being identical to that of the invention and having the identical material property) (pages 3-4).
Regarding claim 11, Hizuka teaches wherein the oxide semiconductor layer contains two or more metals including indium, and a ratio of indium in the two or more metals is 50% or more (for example, the oxide semiconductor film is formed of InGaZn based oxide having In:Ga:Zn with 3:2:1 atomic ratios) (pages 4-5).
Regarding claim 12, Hizuka teaches wherein the oxide semiconductor layer is a crystalline oxide semiconductor layer (for example, the oxide semiconductor film is in a single crystal state) (page 5).
Regarding claim 13, Hizuka teaches wherein a field effect mobility is greater than 40 cm2/Vs (see the rejection of claim 8 above having μ = 45.2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hizuka.
Regarding claims 3-5, Hizuka teaches the planarization process on the first metal oxide layer by a dry etching or the like (page 8). However, Hizuka does not further teach that the planarization process removes at least 5 nm or more from the surface of the first metal oxide layer (claim 3), the planarization process is performed by wet etching using tetramethylammonium hydroxide, potassium hydroxide, or a mixed acid containing phosphoric acid, nitric acid, and acetic acid (claim 4), and the planarization process is performed by a plasma process using an inert gas or halogen gas (claim 5). Nevertheless, it would have been obvious to one of ordinary skill in the art to remove the desired amount of the first metal oxide layer including 5 nm or more (for claim 3), with readily available planarization processes such as a wet etching process with readily available wet etchant (for claim 4) or a plasma process using an inert gas (for claim 5) as readily available planarization processes/conditions for obtaining the desired target surface planarity.
Regarding claims 6 and 9, while Hizuka does not teach a thickness of the first metal oxide layer after the planarization process is 1 nm or more and 20 nm or less, it would have been obvious to one of ordinary skill in the art to adjust the thickness of the first metal oxide layer, including the claimed thickness of 1 nm or more and 20 nm or less, by a routine experimentation for obtaining the optimal and workable thickness range for the first metal oxide layer.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hizuka as applied to claim 1 above, and further in view of Koezuka et al. (US 2020/0052100 A1; hereinafter “Koezuka”).
Regarding claim 7, Hizuka does not further teach forming a second metal oxide layer on the gate insulating layer after forming the gate insulating layer; performing an annealing process with the second metal oxide layer formed on the gate insulating layer; and removing the second metal oxide layer after the annealing process. Koezuka teaches a method for manufacturing a semiconductor device, comprising: forming a second metal oxide layer (a metal oxide layer 114) on a gate insulating layer (a gate insulating layer 110) after forming the gate insulating layer (Fig. 5C and paragraphs 218-229); performing an annealing process with the second metal oxide layer formed on the gate insulating layer (performing a heat treatment after forming the metal oxide layer 114) (paragraph 229); and removing the second metal oxide layer after the annealing process in order to improve the reliability of the transistor (Fig. 5D and paragraphs 229-232). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Hizuka with that of Koezuka in order to improve the reliability of the transistor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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