DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 5/13/26 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues that the combination of Hizu in view of Kobayashi fails to teach “that (1) a first wiring that supplies the first control signal to the pixel circuit is provided on the first circuit layer, the first wiring being connected to the control signal generation circuit in the peripheral region, and (2) a second wiring that supplies the second control signal to the signal processing circuit is provided on the second circuit layer, the second wiring being connected with the control signal generation circuit.” However, the Examiner respectfully disagrees with this conclusion.
As explained in the rejection of claim 1, Hizu discloses a control signal generation circuit that generates a first control signal to control an operation of the pixel circuit (figure 19 exhibits control circuit 210 which supplies a signal to control the pixel circuit as disclosed at paragraph 59) and Kobayashi discloses a control unit that generates a second control signal to control an operation of the signal processing circuit (figure 4 teaches that control unit 620 provides signals for controlling a processing portion 60 as disclosed at paragraph 40). Thus, Hizu in view of Kobayashi disclose the first and second control signals and that said signals are provided from a signal generation unit to the pixel circuit and the signal processing unit, respectively.
Kobayashi further discloses first wiring (paragraph 41 teaches that each substrate has a wiring layer for transmitting signals, it is apparent that signals from the control circuit 620 would be transmitting using said wiring) and second wiring (Kobayashi discloses providing wiring in a wiring layer of the lower substrate as disclosed at paragraph 41). Kobayashi further discloses that the wiring is for transferring signals (paragraph 39 “reduction of the chip area may also improve circuit integration and contribute to an increase in speed by shortening the wiring pattern for transferring signals” [emphasis added]).
Therefore, when modifying Hizu in view of the teachings of Kobayashi, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention that when providing a signal to a component on the first layer (the pixel circuit) to use the first wiring layer since Kobayashi teaches that the wiring pattern is for transferring signals and to use the second wiring layer when providing a signal to a component on the second layer (the signal processing unit) since Kobayashi teaches that the wiring pattern is for transferring signals.
In view of the foregoing, the examiner maintains that the combination of Hizu in view of Kobayashi discloses “that (1) a first wiring that supplies the first control signal to the pixel circuit is provided on the first circuit layer, the first wiring being connected to the control signal generation circuit in the peripheral region, and (2) a second wiring that supplies the second control signal to the signal processing circuit is provided on the second circuit layer, the second wiring being connected with the control signal generation circuit.” Therefore, claim 1 stands rejected in view of Applicant’s amendments as further detailed below.
Specification
The substitute specification filed 5/13/2026 has been entered.
Drawings
The drawings were received on 5/13/2026. These drawings are acceptable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6-8, 13-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hizu (United States Patent Application Publication 2023/0300494) in view of Kobayashi (United States Patent Application Publication 2022/0247964).
Regarding claim 1, Hizu discloses a photoelectric conversion apparatus comprising: a pixel including (1) an avalanche photodiode (figure 19 exhibits a pixel having avalanche photodiode 331 as disclosed at paragraph 66), (2) a pixel circuit that performs processing using a signal output from the avalanche photodiode (figure 19 exhibits quenching and detection circuit 310 and selection transistors 321-324 as disclosed at paragraph 66), and (3) a signal processing circuit that performs processing using a signal output from the pixel circuit (figure 19 exhibits counter 340 as disclosed at paragraph 66); and a control signal generation circuit that generates (1) a first control signal to control an operation of the pixel circuit (figure 19 exhibits control circuit 210 which supplies a signal to control the pixel circuit as disclosed at paragraph 59), wherein a second circuit layer where the signal processing circuit and the control signal generation circuit are arranged (figure 19 exhibits a logic substrate 202 in which the counter and control circuit 210 are arranged as disclosed at paragraphs 160 and 166), a first circuit layer where the pixel circuit is arranged (figure 19 exhibits intermediate substrate 203 in which the pixel circuit is arranged as disclosed at paragraph 166), and a photodiode layer where the avalanche photodiode is arranged (figure 19 exhibits light-receiving substrate 201 in which the photodiodes are arranged as disclosed at paragraph 159) are laminated together in this order (paragraph 159 teaches that the substrates are stacked in that order), wherein an output terminal of the avalanche photodiode is connected to the pixel circuit (figure 19 exhibits the output of photodiode 331 connected to selection transistor 321 of the pixel circuit), wherein the pixel is provided plurally, whereby there are a plurality of pixels, and is arranged in a pixel region (paragraph 58 teaches that an array of pixels is provided). However Hizu fails to disclose (2) a second control signal to control an operation of the signal processing circuit, wherein the control signal generation circuit is arranged in a peripheral region provided around the pixel region, wherein a first wiring that supplies the first control signal to the pixel circuit is provided on the first circuit layer, the first wiring being connected to the control signal generation circuit in the peripheral region, and wherein a second wiring that supplies the second control signal to the signal processing circuit is provided on the second circuit layer, the second wiring being connected with the control signal generation circuit.
Kobayashi is a similar or analogous system to the claimed invention as evidenced Kobayashi teaches an imaging device wherein the motivation of providing an increase in speed by shortening the wiring pattern for transferring signals would have prompted a predictable variation of Hizu by applying Kobayashi’s known principal of providing a second control signal to control an operation of the signal processing circuit (figure 4 teaches that control unit 620 provides signals for controlling a processing portion 60 as disclosed at paragraph 40), the control signal generation circuit is arranged in a peripheral region provided around the pixel region (figure 4 shows control circuit 620 arranged in a peripheral area outside of pixel region 5), and first wiring that supplies the first control signal to the pixel circuit is provided on the first circuit layer, the first wiring being connected to the control signal generation circuit in the peripheral region (paragraph 41 teaches that each substrate has a wiring layer for transmitting signals, it is apparent that signals from the control circuit 620 would be transmitting using said wiring), and a second wiring that supplies the second control signal to the signal processing circuit is provided on the second circuit layer, the second wiring being connected with the control signal generation circuit (Kobayashi discloses providing wiring in a wiring layer of the lower substrate as disclosed at paragraph 41).
In view of the motivations such as providing an increase in speed by shortening the wiring pattern for transferring signals one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Hizu.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 4, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 1, in addition, Kobayashi discloses wherein, in the pixel region, the first wiring is provided on the first circuit layer (Kobayashi discloses providing wiring in a wiring layer of the middle substrate as disclosed at paragraph 41).
Regarding claim 6, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 1, in addition, Hizu discloses wherein an element arranged on the first circuit layer is an element having higher pressure resistance than an element arranged on the second circuit layer (figure 19 exhibits wherein the pixel circuit includes a quenching circuit as disclosed at paragraph 66 and counter 340 which counts the signal output from the quenching/detection circuit 310 as disclosed at paragraph 71, the quenching circuit has a higher pressure resistance than the counter).
Regarding claim 7, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 1, in addition, Hizu discloses wherein the pixel circuit includes a control circuit for the avalanche photodiode (figure 19 exhibits wherein the pixel circuit includes a quenching circuit as disclosed at paragraph 66), and the signal processing circuit includes a count circuit that performs count processing for the signal output from the pixel circuit (figure 19 exhibits counter 340 which counts the signal output from the quenching/detection circuit 310 as disclosed at paragraph 71).
Regarding claim 8, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 7, wherein the pixel circuit includes (1) a quenching element that performs a quenching operation for the avalanche photodiode (figure 19 exhibits a quenching circuit as disclosed at paragraph 66). However figure 19 of Hizu fails to disclose (2) a waveform shaping circuit that performs waveform shaping processing for the signal output from the avalanche photodiode.
Hizu in the embodiment of figure 13 is a similar or analogous system to the claimed invention as evidenced Hizu in the embodiment of figure 13 teaches an imaging device wherein the motivation of reducing counting errors would have prompted a predictable variation of Hizu by applying Hizu in the embodiment of figure 13’s known principal of providing a waveform shaping circuit that performs waveform shaping processing for the signal output from the avalanche photodiode (figure 13 exhibits a pulse-shaping circuit 371 as disclosed at paragraph 128)..
In view of the motivations such as reducing counting errors one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Hizu.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 13, Hizu in view of Kobayashi discloses a photoelectric conversion system comprising: the photoelectric conversion apparatus according to claim 1 (see claim 1); and a signal processing unit that generates an image using a signal output from the photoelectric conversion apparatus (figure 3 of Hizu exhibits signal processing unit 230 as disclosed at paragraph 60).
Regarding claim 14, Hizu in view of Kobayashi discloses a moving body comprising: the photoelectric conversion apparatus according to claim 1 (see claim 1), in addition, Hizu discloses control unit that controls movement of the moving body using a signal output from the photoelectric conversion apparatus (figure 22 exhibits microcomputer 12051 which controls a vehicle based on an output from the image sensor as disclosed at paragraph 189).
Regarding claim 15, Hizu in view of Kobayashi discloses equipment comprising: the photoelectric conversion apparatus according to claim 1 (see claim 1), in addition, Hizu discloses at least any of: (1) an optical apparatus corresponding to the photoelectric conversion apparatus (figure 1 exhibits optical unit 110 as disclosed at paragraph 53); (2) a control apparatus that controls the photoelectric conversion apparatus (figure 1 exhibits control unit 130 as disclosed at paragraph 55); (3) a processing apparatus that processes a signal output from the photoelectric conversion apparatus (figure 22 exhibits outside-vehicle information detecting unit 12030 as disclosed at paragraph 186); (4) a display apparatus that displays information obtained by the photoelectric conversion apparatus (figure 22 exhibits display 12062 as disclosed at paragraph 200); (5) a storage apparatus that stores information obtained by the photoelectric conversion apparatus (figure 1 exhibits recording unit 120 as disclosed at paragraph 54); and (6) a mechanical apparatus that operates on a basis of information obtained by the photoelectric conversion apparatus (paragraph 189 discloses controlling vehicle functions based on image data).
Regarding claim 18, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 1, in addition, Kobayashi discloses wherein in the peripheral region, a part of the first wiring is arranged in the second circuit layer (paragraph 41 teaches that each substrate has a wiring layer for transmitting signals, figure 4 shows that the first through third layers are stacked directly on top of each other, it is apparent that in order for a signal to transmit from the lowest layer 3 to the top layer 1 that the signal will also pass through the wiring layer in the second substrate 2; this portion of the wiring layer of the second substrate 2 which passes the signal from the third substrate 3 to the first substrate 1 is interpreted as part of the first wiring since it transmits a signal to the components on the first substrate 1).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Hizu in view of Kobayashi and further in view of Arita (United States Patent Application Publication 2016/0211299).
Regarding claim 2, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 1, however, Hizu fails to disclose wherein, in the pixel region, buffers are arranged on the first wiring at a fixed pitch according to a pixel unit.
Arita is a similar or analogous system to the claimed invention as evidenced Arita teaches an imaging device wherein the motivation of limiting deviation in the supply timing of the selection signal would have prompted a predictable variation of Hizu by applying Arita's known principal of providing buffers arranged at a fixed pitch according to a pixel unit (figure 7A exhibits a plurality of buffers 130 arranged at a fixed pixel according to the height of a unit pixel as disclosed at paragraph 43).
In view of the motivations such as limiting deviation in the supply timing of the selection signal one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Hizu.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 3, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 1, however, Hizu fails to disclose wherein the plurality of pixels include (1) at least one pixel where a buffer is not provided on the first wiring and (2) at least one pixel where a buffer is provided on the first wiring (figure 4 shows that a buffer is not provided for a first pixel in a row and is provided for a second pixel in a row).
Arita is a similar or analogous system to the claimed invention as evidenced Arita teaches an imaging device wherein the motivation of limiting deviation in the supply timing of the selection signal would have prompted a predictable variation of Hizu by applying Arita’s known principal of providing at least one pixel where a buffer is not provided on the first wiring and at least one pixel where a buffer is provided on the first wiring (figure 4 shows that a buffer is not provided for a first pixel in a row and is provided for a second pixel in a row).
In view of the motivations such as limiting deviation in the supply timing of the selection signal one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Hizu.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hizu in view of Kobayashi and further in view of Masumi et al. (United States Patent Application Publication 2025/0097599), hereinafter referenced as Masumi.
Regarding claim 9, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 8, however, Hizu fails to disclose wherein the quenching element is controlled by the first control signal to switch between (1) a high-resistance state and (2) a low-resistance state where a resistance value is lower than a resistance value of the high-resistance state.
Hizu teaches a quench element that is a resistor (figure 19 shows resistor 311). Masumi teaches that the quench element can be a resistor or a MOS transistor (paragraph 44). A MOS transistor switches between a high-resistance state when a voltage is not applied to the gate and a low-resistance state when a voltage is applied to the gate. Because both the resistor and MOS transistor function as quenching elements, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to substitute the MOS transistor taught by Masumi for the resistor taught by Hizu to achieve the predictable result of performing a quenching function and stopping the avalanche breakdown process by stopping the rapid flow of current in the photodiode.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hizu in view of Kobayashi and further in view of Wang et al. (United States Patent Application Publication 2024/0314468), hereinafter referenced as Wang.
Regarding claim 10, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 7, however, Hizu fails to disclose wherein the count circuit comprises (1) a flip-flop that performs the count processing and (2) a memory that retains a count value obtained through the count processing.
Hizu teaches a counter of unknown structure. Wang teaches a counter comprising flip-flops and memory (figure 11 exhibits a counter 10 comprising counter units 100 which each include a flip-flop 110 and memory 120 as disclosed at paragraph 149). Because both Hizu and Wang teach counters, it would have been obvious to a person having ordinary skill in the art to substitute the counters which have flip-flop that performs the count processing and a memory that retains a count value obtained through the count processing, as taught by Wang, for the counter disclosed by Hizu to achieve the predictable result of counting and retaining a value.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hizu in view of Kobayashi in view of Wang and further in view of Kanehara et al. (United States Patent Application Publication 2020/016983), hereinafter referenced as Kanehara.
Regarding claim 11, Hizu in view of Kobayashi and further in view of Wang discloses the photoelectric conversion apparatus according to claim 10, wherein, on the first wiring, there are arranged (1) a first buffer that outputs the first control signal to a plurality of groups each including at least two pixels among the plurality of pixels and (2) a second buffer that outputs the first control signal to the respective pixels included in the plurality of groups.
Kanehara is a similar or analogous system to the claimed invention as evidenced Kanehara teaches an imaging device wherein the motivation of minimizing the offset in timing of when pixels are controlled would have prompted a predictable variation of Hizu by applying Kanehara’s known principal of providing a first buffer that outputs the first control signal to a plurality of groups each including at least two pixels among the plurality of pixels (figure 15 exhibits a first buffer 80p as disclosed at paragraph 182) and a second buffer that outputs the first control signal to the respective pixels included in the plurality of groups are arranged (figure 15 exhibits buffers 26 which output the signal to the pixels in the groups as disclosed at paragraph 192).
In view of the motivations such as minimizing the offset in timing of when pixels are controlled one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Hizu.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 12, Hizu in view of Kobayashi in view of Wang and further in view of Kanehara discloses the photoelectric conversion apparatus according to claim 11, in addition, Kanehara discloses wherein the first buffer comprises a logic circuit that inverts the first control signal that is to be input (paragraph 160 teaches that the buffers are inverters).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hizu in view of Kobayashi and further in view of Kanehara.
Regarding claim 16, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 1, however, Hizu fails to disclose wherein a buffer provided for the first wiring is arranged in the peripheral region.
Kanehara is a similar or analogous system to the claimed invention as evidenced Kanehara teaches an imaging device wherein the motivation of minimizing the offset in timing of when pixels are controlled would have prompted a predictable variation of Hizu by applying Kanehara’s known principal of providing a buffer provided for the first wiring arranged in the peripheral region (figure 15 exhibits a first buffer 80p arranged in a peripheral region as disclosed at paragraphs 192 and 161).
In view of the motivations such as minimizing the offset in timing of when pixels are controlled one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Hizu.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hizu in view of Kobayashi in view of Kanehara and further in view of Totsuka (United States Patent Application Publication 2014/0168491).
Regarding claim 17, Hizu in view of Kobayashi discloses the photoelectric conversion apparatus according to claim 1, however, Hizu fails to disclose wherein buffers provided for the first wiring are arranged in the first circuit layer and the second circuit layer.
Kanehara is a similar or analogous system to the claimed invention as evidenced Kanehara teaches an imaging device wherein the motivation of minimizing the offset in timing of when pixels are controlled would have prompted a predictable variation of Hizu by applying Kanehara’s known principal of providing a buffer provided for the first wiring arranged in the peripheral region (figure 15 exhibits a first buffer 80p arranged in a peripheral region as disclosed at paragraphs 192 and 161). When applying this known technique to Hizu in view of Kobayashi in which the control signal generation circuit is located in the second circuit layer, it is apparent that the buffers 80p disclosed by Kanehara would also be disclosed in the second circuit layer.
In view of the motivations such as minimizing the offset in timing of when pixels are controlled one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Hizu.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Hizu in view of Kobayashi in view of Kanehara fails to disclose buffers arranged in the first circuit layer.
Totsuka is a similar or analogous system to the claimed invention as evidenced Totsuka teaches an image sensor wherein the motivation of ensuring that drive signals reach the pixels at the far end of the array with a proper voltage would have prompted a predictable variation of Hizu by applying Totsuka’s known principal of buffers arranged in the first circuit layer (figures 2 and 3 show buffers 30 arranged in the layer in which the pixel circuit is located as disclosed at paragraph 23). When applying this known technique to Hizu in view of Kobayashi it would have been obvious to arrange the buffers taught by Totsuka on the first circuit layer in order to properly drive the pixel transistors located on the first circuit layer.
In view of the motivations such as ensuring that drive signals reach the pixels at the far end of the array with a proper voltage one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Hizu.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON A FLOHRE whose telephone number is (571)270-7238. The examiner can normally be reached Mon-Fri 8:00-3:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at 571-272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JASON A. FLOHRE
Patent Examiner
Art Unit 2637
/JASON A FLOHRE/ Patent Examiner, Art Unit 2637
Prosecution Insights