DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The specification, the abstract and the drawings are all acceptable.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-3, 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over USPN 10,686,393 to Wang, and in view of USPN 9,391,603 to Fujimura.
As to claim 1, Wang teaches a semiconductor device that makes at least one-half bridge drivable including an upper transistor and a lower transistor(fig. 5 wherein the frequency inverter includes three half bridges having upper transistors Q1, Q2, Q3 and lower transistors Q4, Q5, Q6), the semiconductor device comprising: an upper control input terminal configured to allow input of an upper control input signal for controlling driving of the upper transistor; a lower control input terminal configured to allow input of a lower control input signal for controlling driving of the lower transistor; a power supply terminal configured to allow input of a power supply voltage and a control logic unit(fig. 5 wherein the microprocessor MCU provides upper control input signals for controlling driving of the upper transistors Q1, Q2, Q3 and lower control input signals for controlling driving of the lower transistors Q4, Q5, Q6 and a power supply terminal “AC input” and “rectifier” configured to allow input of a power supply voltage).
Wang does not teach a reference power supply circuit configured to receive supply of the power supply voltage and to allow generation of a reference power supply voltage to be supplied to the control logic unit; and a switch circuit including switches provided for the upper control input signal and the lower control input signal respectively and switched between on and off in response to logic levels of the upper control input signal and the lower control input signal respectively, wherein the reference power supply circuit is configured to be activated on the basis of a combination of the logic levels of the upper control input signal and the lower control input signal.
Fujimura teaches a reference power supply circuit configured to receive supply of the power supply voltage and to allow generation of a reference power supply voltage to be supplied to the control logic unit and a switch circuit including switches provided for the upper control input signal and the lower control input signal respectively and switched between on and off in response to logic levels of the upper control input signal and the lower control input signal respectively, wherein the reference power supply circuit is configured to be activated on the basis of a combination of the logic levels of the upper control input signal and the lower control input signal(col. 4: lines 63 – col. 5: lines 10 & col. 6: lines 30-62 wherein apparatus and method are taught for reference power supply switching and controls to the control logic unit and switch circuit).
Thus, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to implement the teachings of Fujimura into Wang since Wang suggests a motor control system and Fujimura suggests the beneficial
use of power supply switching and controls for a motor control system in the analogous art of motor control technology.
The motivation for this comes from the fact that Fujimura teaches the power supply switching and controls for a motor control system which can be used to improve the motor control system disclosed by Wang.
As to claim 2, Wang in view of Fujimura teaches the semiconductor device according to claim 1, wherein the reference power supply circuit is configured to be activated if each of the upper control input signal and the lower control input signal is at a high level(Fujimura col. 7: lines 61- col. 8: lines 7).
As to claim 3, Wang in view of Fujimura teaches the semiconductor device according to claim 2, wherein all of the switches are composed of N-channel MOSFETs and are connected in series between the reference power supply circuit and a ground potential(Fujimura col. 7: lines 10-53).
As to claim 6, Wang in view of Fujimura teaches the semiconductor device according to claim 1, wherein the at least one-half bridge includes half bridges of a U-phase, a V-phase, and a W-phase connected to a three-phase brushless DC motor, the upper control input signal includes a U-phase upper control input signal, a V-phase upper control input signal, and a W-phase upper control input signal, the lower control input signal includes a U-phase lower control input signal, a V-phase lower control input signal, and a W-phase lower control input signal, and the switches include a U-phase upper switch allowing input of the U-phase upper control input signal, a V-phase upper switch allowing input of the V-phase upper control input signal, a W-phase upper switch allowing input of the W-phase upper control input signal, a U-phase lower switch allowing input of the U-phase lower control input signal, a V-phase lower switch allowing input of the V-phase lower control input signal, and a W-phase lower switch allowing input of the W-phase lower control input signal(Wang fig. 5 wherein the three half bridges of the three phases are connected to the three phase motor and have control input signals from the “MCU” to control the switches Q1 to Q6).
As to claim 7, Wang in view of Fujimura teaches the semiconductor device according to claim 6, wherein the U-phase upper switch, the V-phase upper switch, the W-phase upper switch, the U-phase lower switch, the V-phase lower switch, and the W-phase lower switch are all composed of N-channel MOSFETs and are connected in series between the reference power supply circuit and a ground potential (Fujimura figs. 1 & 4 & Wang fig. 5).
As to claim 8, Wang in view of Fujimura teaches A motor system comprising: the semiconductor device according to claim 6, the half bridges of the U-phase, the V-phase, and the W-phase drivable by the semiconductor device; and the three-phase brushless DC motor connected to the half bridges of the U-phase, the V-phase, and the W-phase(Wang fig. 5).
As to claim 9, Wang in view of Fujimura teaches a motor system (Wang fig. 5 & col. 5: lines 29-47 teaches a motor system which can be used to all kinds of devices including but not limiting to a vehicle).
Allowable Subject Matter
5. Claims 4-5 are objected to as being dependent upon the rejected base claim 1, but could be allowable if rewritten in independent form including all of the limitations of the base claims and any intervening claims for the following reasons: No prior art of record discloses the features as claimed in the noted claims.
6. The following is a statement of reasons for the indication of allowable subject matter. The non-obvious features are:
In comparison with the closest prior art as cited in this Office action and any previous Office actions, no prior art of record discloses the following features as claimed in the following claim limitations:
As per claim 4: A second end connected to the switch circuit; a PMOS transistor having a gate connected to a first node to which the first diode and the first resistor are connected, and a source connected to the application terminal of the power supply voltage; a second resistor having a first end connected to a drain of the PMOS transistor; a second diode having a cathode connected to a second end of the second resistor, and an anode connected to an application terminal of a ground potential; an NMOS transistor having a gate connected to a second node to which the second resistor and the second diode are connected; a third resistor connected between the application terminal of the power supply voltage and a drain of the NMOS transistor; a bandgap reference connected to a source of the NMOS transistor; and an LDO configured to be activated on the basis of a reference voltage output from the bandgap reference and to generate the reference power supply voltage from the power supply voltage.
As per claim 5: The switch circuit includes a latching switch connected in parallel with a configuration where the switches are connected in series and the control logic unit is configured to maintain the latching switch in an on state on the basis of detection by the detection unit.
Conclusion
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
USPN 11,038,448 to Tsai discloses a motor control system.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID S LUO whose telephone number is (571)270-5251. The examiner can normally be reached 8AM-5PM.
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/DAVID LUO/Primary Examiner, Art Unit 2837
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