Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 13 and 18
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yokoyama et al. (US 20170352399).
Regarding independent claim 1, Yokoyama discloses a memory circuit (Figs. 6-8), comprising:
a memory array comprising a plurality of memory cells (MARY; Fig. 6 and [0052]-[0053] describes memory array);
a low-through latch (LL) coupled to a pin and a control line, wherein the control line carries a clock signal (Fig. 6 and [0053] describes latch circuits 1_0 to 1_n−1 connected to pin A[n] and clock signal ICLK); and
a high-through latch (HL) coupled to the LL, the control line, and the memory array (Fig. 6 and [0053] describes latch circuits 2_0 to 2_n−1 connected to pin LL, inverted clock signal ICLKB and memory array),
wherein the HL is configured to propagate signals when the clock signal is high and stop propagation of the signals when the clock signal is low, and wherein the LL is configured to propagate signals when the clock signal is low and stop propagation of the signals when the clock signal is high (Fig. 6 shows first set of latches are controlled by ICLK and second set of latches are controlled by ICLKB. That satisfies the scenario described here).
Regarding claim 2, Yokoyama discloses all the elements of claim 1 as above and further a clock generator coupled to a clock pin and configured to generate a first clock signal and a second clock signal, wherein the clock signal of the control line corresponds to one of the first clock signal or the second clock signal (Fig. 6 shows signal CLK being connected to ICLK control signal for first set of latches or to ICLKB control signal for second set of latches).
Regarding claim 3, Yokoyama discloses all the elements of claim 1 as above and further the LL and the HL are a first LL and a first HL, respectively, wherein the first LL and the first HL form a first flip-flop interposed between a first address pin and the memory array, and wherein the first address pin is configured for a write operation (Fig. 6 and [0060] describes latch circuits 1_0 to 1_n−1 and the latch circuits 2_0 to 2_n−1 and operates as a flip-flops. The control unit CTRL further includes the read/write control circuit RWCTL).
Regarding claim 9, Yokoyama discloses all the elements of claim 1 as above and further each of the plurality of memory cells is a static random access memory (SRAM) cell configured to perform a read-and-write operation in one clock cycle (Fig. 2 and [0037] describes SRAM memory cell).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama et al. (US 20170352399).
Regarding claim 4, Yokoyama discloses all the elements of claim 3 as above and further a second flip-flop comprising a second LL electrically connected to a second HL, wherein the second flip-flop is coupled to a data pin (Fig. 8 shows n number of first latches connected to n number of second latches); and
a third flip-flop comprising a third LL electrically connected to a third HL, wherein the third flip-flop is coupled to a Bit Write Enable Bit (BWEB) pin (Fig. 8, [0032] and [0062] describes WEN denotes a write enable signal. Output signals are supplied from the front-stage latch circuits 3_1 into which the write enable signal WEN is input to the read/write control circuit RWCTL and the internal access control signals WENQ is output from the rear-stage latch circuits 4_1).
Regarding claim 5, Yokoyama discloses all the elements of claim 4 as above and further a word line (WL) decoder interposed between and coupled to the HL and the memory array (Fig. 6 and [0054] describes word line drive circuit WD); and
a write circuit coupled to the first HL, the second HL, and the third HL, and configured to output a signal to the memory array (Fig. 8 and [0060] describes read/write control circuit RWCTL).
Regarding claim 6, Yokoyama discloses all the elements of claim 3 as above and further a fourth LL electrically coupled to a second address pin, wherein the second address pin is configured for a read operation array (Fig. 8 and [0062] describes front-stage latch circuit 3_2 into which the chip enable signal CEN is input).
Regarding claim 7, Yokoyama discloses all the elements of claim 6 as above and further a read circuit coupled to the fourth LL and the memory array, where the read circuit is configured to receive a signal from the memory array ([0030]-[0032] describes read/write control circuit RWCTL. The read/write control circuit RWCTL generates a decode start-up signal TDEC, an internal write enable signal WE and a sense amplifier enable signal SE in accordance with various control signals (WEN, CLK, CEN) sent from control terminals of the memory macro MEMU. WEN denotes a write enable signal used to distinguish a read command from a write command).
Regarding claim 10, Yokoyama discloses all the elements of claim 1 as above and further a shadow latch comprising a scan flip-flop, wherein the LL and the HL are part of the scan flip-flop (Fig. 11 and [0076] describes scan flip-flop chain in a test mode and thereby circuit sharing is promoted. The memory macro MEMU further includes a scan-in terminal SI, a scan-out terminal SO, and a data-side scan flip-flop chain ScanFF which inputs test data into the data-input-output unit 10 in the test mode).
Regarding claim 11, Yokoyama discloses all the elements of claim 1 as above and further the LL and the HL are a first LL and a first HL, respectively, and wherein the memory circuit further comprises: a read circuit coupled to the memory array; a write circuit coupled to the memory array; a second LL coupled to a common pin, the control line carrying the clock signal, and the read circuit; and a second HL coupled to the second LL, the control line, and the write circuit, wherein a signal from the common pin is separated via a first output from the second LL and a second output from the second HL (Figs, 1, 4, 6 and 8 shows various features).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama et al. (US 20170352399) in view of Weber (US 9941867).
Regarding claim 8, Yokoyama discloses all the elements of claim 1 as above and through Weber further each of the LL and the HL comprises two tri-state buffers and an inverter (Fig. 2 and (20) describes latch 205 being formed using two tri-state buffers (210 and 215) and an inverter 220).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Weber to Yokoyama in order to operate in a different operating modes as taught by Weber (SUMMARY (6)-(7)).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama et al. (US 20170352399) in view of Lin et al. (US 20080034192).
Regarding claim 12, Yokoyama discloses all the elements of claim 1 as above and through Lin further a multiplexer comprising: a first input port coupled to the LL, a second input port coupled to the HL, a control port coupled to a selector pin configured to select an operation mode of the memory circuit, and an output port coupled to the memory array, wherein the multiplexer is configured to output signals from one of the LL or the HL according to a signal from the selector pin, and wherein the operation mode comprises a write- then-read operation and a read-then-write operation (Figs. 1-4 and corresponding sections of the specifications shows input ports of mux being connected with latches and output port to the memory array for read/write operation in any sequence. Control input is connected to mode selection signal).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Lin to Yokoyama in order to provide improved context switch mechanism and DFT (design-for-testability) capability as taught by Lin ([0010]).
Claims 13-17 recite same limitations of device claims 1-12 and henceforth rejected by same way with Yokoyama, Weber and Lin as above.
Claims 18-20 recite same limitations of device claims 1-12 but drafted in method format and henceforth rejected by same way with Yokoyama, Weber and Lin as above.
Response to Arguments
Applicants’ arguments filed on 7/14/2026 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (pg.: 8 of Remarks stated “The claims define a specific sequential signal flow: the LL receives a signal from a pin, and when the clock transitions, the HL receives that signal from the LL and propagates it onward to a memory array for functional operations such as reading or writing. The HL serves as the final stage in a signal path that terminates at the memory array. The HL is the conduit through which address (or other) signals reach the array for operative use”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In terms of broadest reasonable interpretation, HL is electrically coupled with memory array.
Yokoyama in Fig. 6 and [0055] describes that comparator COMP may be implemented or formed as the internal circuit of the memory macro MEMU.
Yokoyama in Fig. 14 and [0086] describes that the front-stage circuits 1_0 to 1_n−1 and the rear-stage latch circuits 2_0 to 2_n−1 are combined together and operate as the flip-flop and an output signal from the flip-flop is output to the comparator COMP as the signal AQ[n].
Rejections are maintained for above reasons.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 8/21/2026
