DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 3-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pal et al. (USPN 11,249,530).
With respect to claim 1, Pal et al. discloses, in Figs. 5 and 7, a reference voltage generator (Fig. 5, details of 450 disclosed in Fig. 7, generating the reference voltage VDD to which the voltage at 425 is referenced to. Thus, Fig. 5 is “reference voltage generator”) comprising:
a header circuit (420-1 to 420-N) configured to pass current from a power supply (current from VIN to VDD) to a time-to-digital converter (current from VDD is passed to the time-to-digital converter of 730 with 450 of Fig. 7, since 730 is powered by VDD), an amount of the current to pass determined by a thermometer code (en[0] to en[N-1]. Note the above code is a thermometer code since it is updated one at a time according to the comparison of 510, i.e., en[0] to en[N-1] increases/decrease one bit at time according to the comparison and is thus a thermometer code, see Col. 7 lines 15-27); and
logic (510 and 520) to update the thermometer code based on a comparison (510 compares the outputs of 450 and 550) between an output of the time-to-digital converter (output of 450/Fig. 7 to 510) and a digital code representing a reference voltage level (output of 550 “Reference Signal”).
With respect to claim 3, the reference voltage generator of claim 1, wherein the logic to update the thermometer code is configured to tolerate metastability (the circuit tolerates metastability due to the synchronous clocking of 510 and 520 by CLKctrl and the circuitry of Fig. 7).
With respect to claim 4, the reference voltage generator of claim 1, further configured to: apply the current to a delay chain of the time-to-digital converter (VDD/current supplied to 730 of the TDC of Fig. 7).
With respect to claim 5, the reference voltage generator of claim 1, further configured to:
generate an output reference voltage level (VDD); and
the time-to-digital converter configured to generate a sample of the output reference voltage level from the current (VDD sampled by 730, i.e., the delay is dependent upon VDD and the output of Fig. 7 produces a sample of the reference voltage level) and a clock signal (CLK applied to 650 and 450 of Fig. 7).
With respect to claim 6, the reference voltage generator of claim 5, wherein the logic to generate the thermometer code comprises:
logic to compare the sample of the output reference voltage level to the digital code representing the reference voltage level (510 comparing the output of 450 and the output of 550).
With respect to claim 7, the reference voltage generator of claim 6, further comprising:
logic to select one of an increment to the thermometer code or a decrement to the thermometer code based on comparison of the sample of the output reference voltage level to the digital code representing the reference voltage level (520 increment/decrementing en[0] to en[N-1]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pal et al. (USPN 11,249,530) in view of Mahajan et al. (USPN 10,175,655)
With respect to claim 2, Pal et al. discloses, the reference voltage generator of claim 1, further comprising:
an arrangement of pass transistors (420-1 to 420-N) configured to set a linear relationship between the thermometer code and the reference voltage level (the amount of activated/deactivated pass transistors of 420-1 to 420-N is linearly controlled one-by-one under the control of the comparison of the output of 450 and 550 such that the thermometer code is linearly controlled responsive to the comparison, see Col. 7 lines 12-27).
Pal et al. fails to disclose the specifics of how the pass transistors are constructed/configured. Thus, Pal et al. fails to disclose that the pass transistors are “progressively stronger”. However, it is old and well-known to binary weight pass transistors of a header switch device. This is further evidenced in Fig. 2 (see 105 MP221 to MP22n) and Col. 5 lines 54-59 of Mahajan et al.
It would have been obvious to construct the transistors 420-1 to 420-N such that they are binary weighted and thus “progressively stronger” as the amount of transistors increase as shown by Mahajan et al., since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so for the purpose of being able to set a desired output current relationship according to the amount of enabled transistors. Furthermore, such binary weighting/progressively stronger transistors is/are old and well-known as shown by Mahajan et al.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pal et al. (USPN 11,249,530) in view of Feng et al. (USPN 11,507,122).
Pal et al. discloses a voltage regulator (Fig. 5). Pal et al. fails to disclose “a low-pass filter configured at a node between the header circuit and the time-to-digital converter.” However, it is old and well-known to place a filtering capacitor (i.e., low-pass filter) between the output of a voltage regulator (i.e., VDD of Pal et al.) and ground. Such a filtering capacitor would be connected between the header of Pall et al. and the time-to-digital converter, since the VDD/output node 425 of Pal et al. is between the header and time-to-digital converter of Fig. 7.
Feng et al. evidences, in Fig. 1, that it is known to place a filtering capacitor (C) between the output terminal (Vout) and ground. Such a filtering capacitor operates as a low-pass filter and will, among other things, filter out high frequency noise/signals at the output terminal Vout.
It would have been obvious to add a filtering capacitor, such a C of Feng et al., between the output of Pal et al. (i.e., VDD) and ground for the purpose of having a filter circuit (i.e., low pass filter) that, among other things, filters out high frequency noise/signals at the output terminal of Pal et al.
Allowable Subject Matter
Claims 9-22 are allowed.
Response to Arguments
Applicant's arguments filed 7/13/2026 have been fully considered but they are not persuasive.
The argument that “Pal teaches a circuit to regulate a supply voltage VDD to a load, not a reference voltage generator” is not persuasive. Examiner agrees that Pal et al. produces a regulated voltage VDD, the voltage VDD being a reference voltage due to the broadest reasonable interpretation of “reference voltage”. As is known “VDD” is commonly referred to in the art as a “reference voltage” since it is the voltage at which other voltages are referenced to. This is further evidenced in Lin et al. (USPAPN 2020/0044639), see paragraph 0017 and Fig. 2, and Wu (USPN 11,736,099), see Col. 14 lines 20-28 and Fig. 11A, as can be seen the upper rail voltage of VDD is known in the art to be a “reference voltage”. Therefore, a circuit that generates/regulates a VDD is a “reference voltage generator” due to the broadest reasonable interpretation of “reference voltage”.
The argument that the “enable vector is not a thermometer code” is not persuasive. As can be seen in Col. 7 lines 33-53 the enable vector operates as a thermal code. For instance, a magnitude of the difference between the timing margin and the reference signal is determined (see Col. 7 lines 34-37). Furthermore, Pal operates to turn on or off of an amount (amount equal to “k”) transistors according to the magnitude (i.e. “k”) of the difference between the timing margin and reference terminal. Thus, the amount of transistors that are enabled/disable are thermometer coded to k. Therefore the enable vector is thermometer coded. For instance, say that there are four transistor 420-1 to 420-4, and K is equal to the magnitude of the difference of the timing margin and reference signal, then according to Col. 7 lines 33-53 en[0]-en[3] would be generated similar to the table below:
K
en[0]
en[1]
en[2]
en[3]
-2
0
0
0
0
(i.e., timing margin is less than reference signal by 2 )
-1
1
0
0
0
(i.e., timing margin is less than reference signal by 1 )
0
1
1
0
0
(i.e., timing margin is equal to reference signal )
1
1
1
1
0
(i.e., timing margin is greater than reference signal by 1 )
2
1
1
1
1
(i.e., timing margin is equal to reference signal by 2 )
Thus, the enable vector is thermometer coded with respect to K. This is similar to the “thermal code” as shown in TABLE 1 of Col. 7 Yu et al. (USPN 11,405,045) and Col. 5 lines 7-15 of Miao et al. (USPN 10,680,856). Further evidencing that the operation of Pal is thermometer coded.
The argument that “there is no feedback mechanisms updating a thermometer code based on a comparison between an output of the time- to-digital converter and a digital code representing a reference voltage level” is not persuasive. The feedback mechanism is provided by the timing circuit 450 as disclosed in Figs. 6 and 7. For instance 650 generates a clock/timing signal (610) that is dependent upon the VDD level as provided to 650 (see also 730 of Fig. 7). Furthermore, TDC 450 generates the timing margin based on the VDD dependent delay which is compared to the digital reference voltage level (555) generated by 550 of Fig. 5. The above operation provides for such a feedback mechanism. This is further evidenced in Col. 6 line 28 to Col. 7 line 53. Thus, Applicant’s arguments are not persuasive.
The argument that “[t]he Claims compare the TDC output to a digital code representing a reference voltage level whereas Pal compares the TDC-generated timing margin signal to a reference timing value stored in a register” and the “digital code in Pal is a timing-margin target, not a representation of a reference voltage level” is not persuasive. This is because the timing margin is a representation of the reference voltage level of VDD since the timing margin is proportional to the level of the reference voltage VDD. This is because the level of VDD is adjusted with respect to the timing margin value and the timing margin value is compared to the reference voltage level 555 to the proper level of VDD, see Col. 6 lines 43-65. Furthermore, the circuit of Fig. 7 detects voltage droops of VDD and the timing margin being dependent upon VDD such that VDD is regulated (i.e., adjusted according to changes in the load demand/current), see Col. 5 lines 13-29, Col. 10 line 63 to Col. 11 line 9 and Col. 12 line 63 to Col. 13 line 31. Therefore, the circuit adjusts VDD according to the timing margin and reference signal 555 such that VDD is regulated to a desired value according to a change in load current demand.
The argument that the “header switch adjustments resulting from the comparison don't target a voltage that is used as a reference”, since they “target a voltage that satisfies a timing margin” and therefore “Pal cannot reasonably be characterized as teaching ‘a comparison between an output of the time-to- digital converter and a digital code representing a reference voltage level’” is not persuasive for the reasons discussed above. Since 510 of Fig. 5 compares the output voltage of the TDC of 450 with the reference signal code of 555 such that the level of reference voltage VDD is regulated. This Pal discloses the claimed limitations.
A thermometer code is not merely a value that changes by one element per iteration. Rather, it is a particular encoding. A thermometer code is a specific coding format characterized by contiguous asserted bits and a monotonically moving boundary between asserted and de-asserted bits. This is fundamentally different from a binary or Gray code counter, one-hot, Johnson code etc. that changes one bit per step but is not thermometer encoded. Simply changing "one switch at a time" does not make Pal's enable code into a thermometer code.
The following arguments are not persuasive:
“There is no teaching at all in Pal that maintaining a contiguous enable pattern with a monotonically moving transition boundary is important. Thus thermometer coding is not an inevitable or even likely consequence of Pal's disclosure. Under anticipation, inherency requires that the missing feature be necessarily present, not merely one possible implementation that can be imagined.”
As discussed above en[0] to en[N-1] are thermometer coded with respect to the magnitude of k. The enable pattern monotonically increases/decreases with the value of k. Therefore, the above arguments are not persuasive.
The following arguments are not persuasive: “Pal also does not disclose the claimed supply circuit or feedback loop. The claims recite a header circuit configured to pass current from a power supply to a time-to-digital converter, wherein an amount of the current passed is determined by the thermometer code. Pal teaches using a timing circuit to increase or decrease the number of enabled header switches supplying a load circuit 460 by one step at a time. The Pal header circuit does not pass current from a power supply to a time-to-digital converter wherein an amount of the current passed is determined by a thermometer code. In Pal the header switches regulate the supply voltage delivered to the protected circuit, such as a processor or logic block. The timing circuit merely observes the timing behavior of that circuit and produces a digital timing margin signal. The TDC is upstream of the header switches and does not receive or consume current supplied by the header switches”.
The output of the TDC within 450 controls 452 such that the header switches pass current from VDD to the TDC within 450 since VDD controls 650 of the TDC of Figs. 6 and 7 within 450. Wherein 650 controls the timing margin responsive to the change in VDD and thus the amount of headers/current supplied responsive to VDD. Furthermore, VDD is dependent on the amount of current required by the load and the amount of current provided by the header switches as evidenced in Col. 5 lines 13-29
The following arguments are not persuasive: “In sum, Pal merely describes switch controller 520 enabling or disabling header switches 420-1 through 420-N to regulate the supply provided to the protected circuit in response to a timing-margin comparison. Although timing circuit 450 performs time-to-digital conversion, the reference does not disclose that the header switches supply current to the time-to-digital converter itself, nor that the amount of current supplied to the time-to-digital converter is determined by the enable vector. Rather, timing circuit 450 is part of the feedback path that measures circuit timing, while the header switches regulate the supply delivered to the monitored logic. Accordingly, even if the enable vector EN were assumed, arguendo, to constitute a thermometer code (which is does not), Pal fails to disclose the claimed relationship in which the thermometer code determines an amount of current passed by a header circuit to a time-to-digital converter.”
This is because the code generated by 435 of Fig. 5 is responsive to both the current generated by 420-1 to 420-N and the current consumed by the load 460. The circuitry of 450 as disclosed in Figs. 6-7 detects the current consumption of the load and the amount of current supplied by the headers by determining the timing margin which is indicative of both the load current consumed and the amount of current provided to VDD by the header switches for the reasons discussed above. Thus Pal operates as claimed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
