DETAILED ACTION
Re Application No. 18/894592, this action responds to the amended claims dated 01/06/2026.
At this point, claims 1-5 and 7-19 have been amended. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Examiner notes Applicant’s amended claims dated 01/06/2026. In view of the amendments, Examiner’s prior rejections under 35 USC § 112(b) have been rendered moot and are accordingly withdrawn, except as follows:
The claims are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, as follows:
Claim 7, language “the RAID controller is configured to transmit a second output command and the second address to the second plane after transmitting the first output command and the first address to the first plane” (lines 1-3). This limitation appears to directly conflict with claim 5, as claim 5, as claim 5 appears to require the address/output commands to be transmitted in the order of the read/address commands (lines 4-6), while claim 7 requires it to be the reverse, as claim 7 requires the second output/address to be transmitted after the first output/address (lines 1-3), but parent claim 6, which depends on claim 5, requires the second read/address to be transmitted before the first read/address (lines 2-3);
Claims 15 and 16, language “transmit a [first/second] output command and the [first/second] address to the [first/second] normal plane for the [first/second] normal plane to output the [first/second] sub-stripe data” (e.g. claim 15, lines 2-3). This limitation is indefinite, as parent claim 13 already discloses reading the first and second sub-stripe data (lines 6-7), while parent claim 14 discloses transmitting first and second read commands with first and second addresses (lines 2-3). Accordingly, it is unclear how an “output command” differs from a read command, as a read command implicitly includes a request to return (output) the data from the requested location. Accordingly, Examiner interprets the read commands to be both read commands and output commands.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Klein et al (US 2022/0027233 A1) in view of Piszczek et al (US 9639457 B1).
Re claim 1, Klein discloses the following:
a redundant array of inexpensive disk (RAID) system comprising (¶ 4). The memory array is implemented as a RAID 5 (RAID);
a plurality of nonvolatile memory devices including a plurality of planes for storing data chunk and parity data the data chunk including a plurality of sub-stripe data, the plurality of sub-stripe data including first sub-stripe data and second sub-stripe data; and (¶ 22 and 34). The storage system includes a plurality of NAND flash (nonvolatile memory devices), each of which includes one or more dies, each of which includes one or more planes (¶ 34); however, it is noted that “a plurality of nonvolatile memory devices including a plurality of planes” does not actually require multiple planes per device; in fact, Applicant’s own example in the specification and drawings merely discloses a single plane for each device (Fig. 3). Furthermore, the limitation “for storing a data chunk and parity data” is intended use, and is not given patentable weight. Nonetheless, Klein discloses that the planes of the NAND devices are used for storing parity and data. Data in a stripe includes respective data on each data disk (first sub-stripe and second sub-stripe data) (¶ 22);
a RAID controller configured to access at least one of the plurality of nonvolatile memory devices in a plane independent read (PIR) mode (Fig. 1, controller 110; ¶ 77-79). It is noted that Applicant has not claimed any details about the “plane independent read mode”; and the specification merely states that “in a plane independent read (PIR) mode, the RAID controller may perform an access operation for each of a plurality of planes PL1 to PLN independently or in parallel” (¶ 54). Accordingly, Examiner interprets “plane independent read mode” to merely be reading data across a plurality of disks (and accordingly, the planes in the disks corresponding to said data), either independently or in parallel. During a data recovery operation (PIR mode), data is sequentially read from each device (and a corresponding plane therein);
wherein the RAID controller is configured to transmit, to the at least one of the plurality of nonvolatile memory devices, a first read command and a first address, the first address corresponding to a first plane of the plurality of planes, transmit, to the at least one of the plurality of nonvolatile memory devices, a second read command and a second address, the second address corresponding to a second plane of the plurality of planes (¶ 77-79 and 82-83). As part of a data recovery operation, the RAID controller transmits reads to each of the storage devices (including first and second ones) and reads them into the drive buffer (at least one of the nonvolatile memory devices) (¶ 77-79). The memory read requests (commands) use respective addresses to access the data, wherein the addresses can be logical block addresses corresponding to blocks (¶ 82-83). The blocks and pages corresponding to those LBAs also correspond to planes (¶ 34). Since each flash device contains its own respective one or more planes, data which is striped across different devices is striped across a plurality of planes;
[…] an XOR enable command, the XOR enable command being configured to activate XOR computation on the at least one of the plurality of nonvolatile memory devices (¶ 77-79). The recovery request enables (activates) parity to be recalculated using XOR; accordingly, it is an XOR enable command;
receive the first sub-stripe data from the first plane, and receive the second sub-stripe data from the second plane (¶ 34 and 77-79 and 82). The respective storage devices (and their respective planes) (¶ 34) each send the requested read data corresponding to the requested addresses to the RAID controller (¶ 77-79 and 82);
transmit an input command and a third address to at least one of the plurality of nonvolatile memory devices, the third address corresponding to a third plane of the plurality of planes (¶ 39, 77-79, 82, 86 and 95). The RAID controller sends a command to store (input) the requested data into the drive buffer (at least one of the non-volatile memory devices) (¶ 39, 77-79 and 82). The recovered XOR data is written to the trans-XOR portion of the drive buffer, and ultimately to one of the NAND disks in the RAID array, wherein the recovered XOR data is associated with the address that the recovered data is to be stored (third address corresponding to a third plane) (¶ 86 and 95).
Klein discloses serial parity (XOR) calculations across memory devices; while it also discloses that the calculations may be distributed, it does not go into extensive detail about how this works. Accordingly, Examiner has provided Piszczek.
Piszczek discloses that the RAID controller is configured to: […] transmit, to the at least one of the nonvolatile memory devices, an XOR enable command, the XOR enable command being configured to activate XOR computation on the at least one of the plurality of nonvolatile memory devices (col. 6, lines 6-9). The distributed data storage controller which is designated to calculate parity (RAID controller) applies (transmits) an XOR logic function to the FPGA of the storage (at least one of the nonvolatile memory devices), which activates XOR computation.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the RAID parity calculation of Klein to handle them on memory devices, rather than a host, as in Piszczek, because Piszczek suggests that distributing XOR (parity) calculation across storage devices would allow the system to efficiently scale as the amount of storage increases, eliminating the need for costly hardware for a centralized RAID engine (col. 1, lines 28-33).
Re claim 2, Klein and Piszczek disclose the system of claim 1; Klein further discloses to transmit a program command and the third address to the at least one of the plurality of nonvolatile memory devices (¶ 39, 77-79, 82, 86 and 95). See claim 1 above.
Piszczek further discloses the following:
wherein the RAID controller is configured to: transmit the first sub-stripe data to the third plane, transmit the second sub-stripe data to the third plane (Figs. 3 and 6A-6D and associated text). XOR calculation is distributed across the storage devices; each storage device receives two pieces of data, either original data or a previously calculated partial parity (first and second sub-stripe data) which are received at the FPGA of the respective storage device (third plane), and from which parity is calculated;
transmit a program command […] to the at least one of the nonvolatile memory devices (claim 1). The distributed storage controllers (RAID controller) receives a write request (program command) from the host, and transmit it to the corresponding memory.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein and Piszczek, for the reasons noted in claim 1 above.
Re claim 3, Klein and Piszczek discloses the system of claim 2 above, and Klein further discloses to write […] to the third address (¶ 39, 77-79, 82, 86 and 95). See claim 1 above.
Piszczek further discloses that the third plane is configured to write a result of XOR computation for the first sub-stripe data and the second sub-stripe data to the third [plane] (Figs. 6A-6D and associated text). The designated parity device (third plane) is configured to write the result of the XOR computation into the corresponding flash memory (third plane).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein and Piszczek, for the reasons noted in claim 1 above.
Re claim 5, Klein and Piszczek disclose the system of claim 1, and Klein further discloses to sequentially transmit a respective read command and a respective address to each plane of the plurality of planes except the third plane in a first order, and sequentially transmit the respective address and a respective output command of sub-stripe data corresponding to the respective address to each plane of the plurality of planes except the third plane in an second order, the first order being a same as the second order (¶ 77-79). The storage system sequentially sends out read commands to respective addresses, and sequentially reads data out of each of a plurality of planes.
Re claim 6, Klein and Piszczek disclose the system of claim 5, and Klein further discloses that the RAID controller is configured to transmit the second read command and the second address to the second plane before transmitting a first output command and the first address to the first plane (¶ 77-79). The data is read in a sequential order; no additional details are given about what distinguishes the first address/first plane from the second address/second plane; accordingly, whichever disk (plane) and address is accessed first is the second address/disk (plane), while the one that is accessed second is the first address/disk (plane).
Re claim 7 Klein and Piszczek disclose the system of claim 6, and Klein further discloses that the RAID controller is configured to transmit a second output command and the second address to the second plane after transmitting the first output command and the first address to the first plane (¶ 77-79). This limitation is indefinite, as noted above. Examiner interprets the order for reading and outputting to be the same, i.e. the same sequential order.
Re claim 13, Klein discloses the following:
a redundant array of inexpensive disk (RAID) system comprising (¶ 4). See claim 1 above;
a nonvolatile memory device including a first normal plane, a second normal plane, and a parity plane (¶ 22 and 34). The storage system includes a plurality of NAND flash (nonvolatile memory devices), each of which includes one or more dies, each of which includes one or more planes (¶ 34); however, it is noted that “a plurality of nonvolatile memory devices including a plurality of planes” does not actually require multiple planes per device; in fact, Applicant’s own example in the specification and drawings merely discloses a single plane for each device (Fig. 3). Klein discloses that the planes of the NAND devices are used for storing parity (parity plane) and data (first and second normal planes) (¶ 22);
a RAID controller configured to individually performing a read operation for each of the first normal plane, the second normal plane, and the parity plane, wherein the RAID controller is configured to (Fig. 1, controller 110; ¶ 50). During a process of updating parity, a read operation is individually performed for each disk (and the plane thereon), including both data and parity disks (and planes);
the XOR enable command being configured to activate XOR computation on the nonvolatile memory device (¶ 77-79). See claim 1 above;
read first sub-stripe data of the first normal plane and second sub-stripe data of the second normal plane (¶ 77-79 and 82). As part of a data recovery operation, the RAID controller transmits reads to each of the storage devices (including first and second data disks (and their normal planes) and reads the respective data (sub-stripes).
Klein does not explicitly disclose the controller transmitting XOR enable commands to the memory device, or transmitting first/second sub-stripe data to a parity plane.
Piszczek discloses the following:
the RAID controller is configured to: transmit an XOR enable command to the nonvolatile memory device, the XOR enable command being configured to activate XOR computation on the nonvolatile memory devices (col. 6, lines 6-9). See claim 1 above;
transmit the first sub-stripe data and the second sub-stripe data to the parity plane, and (Figs. 3 and 6A-6D and associated text). See claim 2 above;
write parity data obtained by XOR computation for the first sub-stripe data and the second sub-stripe data to the parity plane (Figs. 3 and 6A-6D and associated text). See claim 3 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein and Piszczek, for the reasons noted in claim 1 above.
Re claim 14, Klein and Piszczek disclose the RAID system of claim 13, and Klein further discloses the following:
transmit a first read command and a first address to the first normal plane for the first normal plane to read first sub-stripe data corresponding to the first address, and transmit a second read command and a second address to the second normal plane for the second normal plane to read the second sub-stripe data corresponding to the second address (¶ 77-79 and 82). See claim 1 above.
Re claim 15, Klein and Piszczek disclose the RAID system of claim 14, and Klein further discloses the following:
the RAID controller is configured to: transmit a first output command and a first address to the first normal plane for the first normal plane to output the first sub-stripe data corresponding to the first address, and (¶ 77-79 and 82). As noted above, it is unclear how the “[first/second] output command” is distinct from the “[first/second] read command”. Accordingly, Examiner interprets the read commands as including output commands, since they are requests to return (output) requested data.
transmit a first input command, a third address […] to the parity plane (¶ 39, 77-79, 82, 86 and 95). The RAID controller propagates a command to store (input) the requested data, along with addresses, across the planes, including a parity plane (¶ 39, 77-79 and 82).
Pisczcek discloses to transmit […] the first sub-stripe data to the parity plane (Figs. 6A-6D and associated text). See claim 1 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein and Piszczek, for the reasons noted in claim 1 above.
Re claim 16, Klein and Piszczek disclose the RAID system of claim 15, and Klein further discloses the following:
the RAID controller is configured to: transmit a second output command and a second address to the second normal plane for the second normal plane to output the second sub-stripe data corresponding to the second address, and (¶ 77-79 and 82). As noted above, it is unclear how the “[first/second] output command” is distinct from the “[first/second] read command”. Accordingly, Examiner interprets the read commands as including output commands, since they are requests to return (output) requested data.
transmit a second input command, a third address […] to the parity plane (¶ 39, 77-79, 82, 86 and 95). The RAID controller propagates a command to store (input) the requested data, along with addresses, across the planes, including a parity plane (¶ 39, 77-79 and 82).
Pisczcek discloses to transmit […] the second sub-stripe data to the parity plane (Figs. 6A-6D and associated text). See claim 1 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein and Piszczek, for the reasons noted in claim 1 above.
Claims 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Klein in view of Piszczek, and further in view of Yoshihara et al (US 2016/0259687 A1).
Re claim 4, Klein and Piszczek disclose the system of claim 2, and Piszczek further discloses to transmit, to the at least one of the plurality of nonvolatile memory devices, the program command based on the plurality of sub-stripe data of the data chunk being transmitted (Figs. 6A-6D and associated text). The controller transmits to at least one of the nonvolatile memory devices, a program command based on the input data (plurality of sub-stripe data) being transmitted to the parity storage (third plane), wherein the input data is XOR’d and stored as parity.
Klein and Piszczek both disclose distributed parity calculation across storage devices, and both disclose ultimately storing calculated parity data; however, they do not explicitly disclose an XOR disable command.
Yoshihara discloses to transmit an XOR disable command to the at least one of the plurality of nonvolatile memory devices, the XOR disable command being configured to instruct the at least one of the plurality of nonvolatile memory devices to complete the XOR computation (¶ 3). Yoshihara submits a commitment command (XOR disable command) to indicate to the storage that the parity calculation has completed, and that the XOR data should be committed to storage.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the RAID of Klein (combined with Piszczek) to send a parity commitment (XOR disable) command to the storage, as in Yoshihara, because it would be applying a known technique to improve a similar system in the same way. Klein (combined with Piszczek) discloses a RAID system which calculates and stores parity. Yoshihara also contains a RAID which calculates and stores parity, which has been improved in a similar way to the claimed invention, to send a parity commitment command. It would have been obvious to modify the RAID system of Klein (combined with Piszczek) to send a parity commitment command, as in Yoshihara, because it would yield the predictable improvement of committing the parity data so that it may be used for recovery if necessary.
Re claim 17, Klein and Piszczek disclose the system of claim 16, and Klein further discloses the following:
transmit a program command and the third address to the parity plane (¶ 77-79, 82, 89, and 95). The program command and destination address (third address) are sent to the nonvolatile drive buffer, and eventually the new storage (either of which can be considered the parity plane);
Store parity data at the third address in the parity plane (¶ 77-79, 82, 89, and 95). The calculated parity data is programmed to the non-volatile buffer, and ultimately the address in the new storage (either of which can be considered the parity plane).
Klein and Piszczek do not explicitly disclose an XOR disable command.
Yoshihara discloses outputting an XOR disable command to the nonvolatile memory device, the XOR disable command being configured to instruct the nonvolatile memory to complete the XOR computation (¶ 3). See claim 4 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein, Piszczek, and Yoshihara, for the reasons noted in claim 4 above.
Claims 8-12 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Klein in view of Piszczek, further in view of Gatto et al (US 2024/0070024 A1).
Re claim 8, Klein discloses the following:
a redundant array of inexpensive disk (RAID) system comprising (¶ 4). See claim 1 above;
a plurality of nonvolatile memory devices including a plurality of planes for storing data chunk and parity data the data chunk including a plurality of sub-stripe data, the plurality of sub-stripe data including first sub-stripe data and second sub-stripe data; and (¶ 22 and 34). See claim 1 above;
a RAID controller configured to access at least one of the plurality of nonvolatile memory devices, wherein the controller is configured to (Fig. 1, controller 110; ¶ 77-79). See claim 1 above;
[…] an XOR enable command, the XOR enable command being configured to activate XOR computation on the at least one of the plurality of nonvolatile memory devices (¶ 77-79). See claim 1 above;
transmit a first read command and a first address […], the first address corresponding to a first plane of the plurality of planes, output a first output command and the first address, transmit a second read command and a second address […], the second address corresponding to a second plane of the plurality of planes, output a second output command and the second address (¶ 77-79 and 82). As part of a data recovery operation (XOR enable command), the RAID controller transmits reads to each of the storage devices (including first and second ones) and reads (outputs) them into the drive buffer (at least one of the nonvolatile memory devices) (p.gf 77-79). The memory read requests (commands) use respective addresses to access the data (¶ 82);
receive the first sub-stripe data from the first plane and receive the second sub-stripe data from the second plane (¶ 34 and 77-79 and 82). The respective storage devices (and their respective planes) (¶ 34) each send the requested read data corresponding to the requested addresses to the RAID controller (¶ 77-79 and 82);
transmit an input command and a third address […] the third address corresponding to a third plane of the plurality of planes (¶ 39, 77-79, 82, 86 and 95). The RAID controller sends a command to store (input) the requested data into the drive buffer (at least one of the non-volatile memory devices) (¶ 39, 77-79 and 82). The recovered XOR data is written to the trans-XOR portion of the drive buffer, and ultimately to one of the NAND disks in the RAID array, wherein the recovered XOR data is associated with the address that the recovered data is to be stored (third address) (¶ 86 and 95).
Klein discloses serial parity (XOR) calculations across memory devices; while it also discloses that the calculations may be distributed, it does not go into extensive detail about how this works. Accordingly, Examiner has provided Piszczek.
Piszczek discloses that the RAID controller is configured to: transmit, to the at least one of the nonvolatile memory devices, an XOR enable command, the XOR enable command being configured to activate XOR computation on the at least one of the plurality of nonvolatile memory devices (col. 6, lines 6-9). See claim 1 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein and Piszczek, for the reasons noted in claim 1 above.
Klein and Piszczek disclose the functional language above; however, they do not explicitly mention specific command-address signal lines or data signal lines.
Gatto discloses a RAID controller configured to access at least one of the nonvolatile memory devices through an independent command-address signal line (CA) and a data signal line (DQ) (Figs. 1 and 3; ¶ 41 and 48). The memory controller (RAID controller) accesses the memory devices through one or more command-address signal buses (line (CA)) and one or more data signal buses (line (DQ)).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the RAID system of Klein (combined with Piszczek) to utilize separate command-address signal lines and data signal lines, as in Gatto, because it would be applying a known technique to improve a similar system in the same way. Klein (combined with Piszczek) discloses a RAID storage. Gatto also discloses a RAID storage, which has been improved in the same way as the claimed invention, to place the data and command/address signals on separate buses. It would have been obvious to modify the data and command/address signals of Klein (combined with Piszczek) to place them on separate buses, because it would yield the predictable improvement of isolating the signals from one another, reducing the chance of them interfering with one another.
Re claim 9, Klein, Piszczek, and Gatto disclose the system of claim 8, and Klein further discloses receiving the first sub-stripe data […] while transmitting the input command and the third address (Fig. 3B; ¶ 73). Klein discloses reading data using the address and input command, and inputting said data to the parity calculator, and further discloses that these steps may happen simultaneously (i.e. while).
Gatto discloses receiving the first sub-stripe data through the data signal line […] transmitting the input command and the third address through the command-address signal line (Figs. 1 and 3; ¶ 41 and 48). Gatto contains a CA bus (line) for transmitting/receiving commands and addresses, and a DQ bus (line) for transmitting/receiving data.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein Piszczek, and Gatto, for the reasons noted in claim 8 above.
Re claim 10, Klein, Piszczek, and Gatto disclose the system of claim 9, and Klein further discloses receiving the second sub-stripe data […] while transmitting the input command and the third address (Fig. 3B; ¶ 73). See claim 9 above.
Gatto discloses receiving the second sub-stripe data through the data signal line […] transmitting the input command and the third address through the command-address signal line (Figs. 1 and 3; ¶ 41 and 48). See claim 9 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein, Piszczek, and Gatto, for the reasons noted in claim 8 above.
Re claim 11, Klein, Piszczek, and Gatto disclose the system of claim 10; Klein further discloses that the RAID controller is configured to […] to transmit the third address to the third plane (¶ 39, 77-79, 82, 86 and 95). See claim 1 above.
Piszczek further discloses wherein the RAID controller is configured to: transmit the second sub-stripe data to the third plane (Figs. 3 and 6A-6D and associated text). See claim 2 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein and Piszczek, for the reasons noted in claim 1 above.
Gatto discloses to transmit the second sub-stripe data […] through the data signal line […] transmit the third address […] through the command-address signal line (Figs. 1 and 3; ¶ 41 and 48). Gatto contains a CA bus (line) for transmitting/receiving commands and addresses, and a DQ bus (line) for transmitting/receiving data.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein, Piszczek, and Gatto, for the reasons noted in claim 8 above.
Re claim 12, Klein, Piszczek, and Gallo disclose the system of claim 11 above, and Klein further discloses to write […] to the third address (¶ 39, 77-79, 82, 86 and 95). See claim 1 above.
Piszczek further discloses that the RAID controller is configured to write a result of XOR computation for the first sub-stripe data and the second sub-stripe data to the third [plane] (Figs. 6A-6D and associated text). See claim 3 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein, Piszczek, and Gallo, for the reasons noted in claim 8 above.
Re claim 18, Klein and Piszczek disclose the system of claim 13, and Klein further discloses the following:
transmit the XOR enable command to the nonvolatile […] transmit a first read command and a first address to the first normal plane […] output a first output command and the first address (¶ 77-79 and 82). See claim 8 above;
transmit a first input command and a third address to the parity plane […] (¶ 39, 77-79, 82, 86 and 95). The RAID controller sends a command to store (input) the requested data into the drive buffer (at least one of the non-volatile memory devices) (¶ 39, 77-79 and 82). The recovered XOR data is written to the trans-XOR portion of the drive buffer, and ultimately to one of the NAND disks in the RAID array, wherein the recovered XOR data is associated with the address that the recovered data is to be stored (third address) (¶ 86 and 95).
Klein discloses the functional language above; however, it does not explicitly mention specific command-address signal lines or data signal lines.
Gatto discloses a command-address signal line (Figs. 1 and 3; ¶ 41 and 48). See claim 8 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein, Piszczek, and Gatto, for the reasons noted in claim 8 above.
Re claim 19, Klein, Piszczek, and Gallo disclose the system of claim 18, and Klein further discloses the following:
transmit a second read command and a first address to the second normal plane […] output a second output command and the second address (¶ 77-79 and 82). See claim 8 above;
transmit a second input command and a third address to the parity plane […](¶ 39, 77-79, 82, 86 and 95). See claim 18 above.
Klein discloses the functional language above; however, it does not explicitly mention specific command-address signal lines or data signal lines.
Gatto discloses a command-address signal line (Figs. 1 and 3; ¶ 41 and 48). See claim 8 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein and Gatto, for the reasons noted in claim 8 above.
Re claim 20, Klein, Piszczek, and Gatto disclose the system of claim 19, and Klein further discloses the following:
the RAID controller is configured to transmit a program command and the third address to the parity plane (¶ 77-79, 82, 89, and 95). See claim 2 above;
wherein the parity plane is configured to generate the parity data by performing XOR computation for the first sub-stripe of data and the second sub-stripe of data, which are input in accordance with the first input command and the second input command, and program the parity data to the third address in accordance with the program command ((¶ 77-79, 82, 89, and 95). The recovered data is generated as the result of XOR computation of the first and second data (¶ 77-79 and 82). It is written to the drive buffer, and ultimately may be written to the corresponding address in the new storage device (third address) (¶ 89 and 95).
Gatto discloses to transmit a program command and a third address […] through the command-address signal line (Figs. 1 and 3; ¶ 41 and 48). See claim 9 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Klein, Piszczek, and Gatto, for the reasons noted in claim 8 above.
ACKNOWLEDGEMENT OF ISSUES RAISED BY THE APPLICANT
Response to Amendment
Applicant’s arguments with respect to claims 1-20 filed on 01/06/2026 have been fully considered, but are either not deemed persuasive, or are moot in view of new grounds for rejection.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING 112(b) REJECTIONS
Re claims 2-7 and 9-20, Applicant argues that the amended claims are sufficient to obviate Examiner’s prior rejections under 35 USC § 112(b). In response, Applicant’s argument has been fully considered. Re claims 7 and 15-16, Examiner’s prior rejections are maintained. All other claims rejected under 35 USC § 112(b) have been rendered moot, and are accordingly withdrawn.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Claims must be given the broadest reasonable interpretation during examination and limitations appearing in the specification but not recited in the claim are not read into the claim (See M.P.E.P. 2111 [R-1]).
Re claim 1, 8, and 13, Applicant argues that Klein does not disclose the newly amended limitation “a RAID controller configured to […] transmit, to the at least one of the plurality of non-volatile memory devices, an XOR enable command, the XOR enable command being configured to activate XOR computation on the at least one of the plurality of nonvolatile memory devices”. In response, Applicant’s argument has been fully considered, but is moot in view of new grounds for rejection. As previously noted, Klein discloses issuing a command to perform parity recalculation (XOR enable command). New reference Piszczek discloses that the distributed data storage controller which is designated to calculate parity (RAID controller) applies (transmits) an XOR logic function to the FPGA of the storage (at least one of the nonvolatile memory devices), which activates XOR computation (col. 6, lines 6-9).
Re claims 2-7, 9-12, and 14-20, Applicant argues that the claims are allowable by virtue of their dependence upon one of claims 1, 8, and 13 above, respectively.
All arguments by the Applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 01/06/2026.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Per the instant office action, claims 1-20 have received an action on the merits and are subject to a final rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132
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