Prosecution Insights
Last updated: October 26, 2026
Application No. 18/895,332

SELF-EXTENDABLE INTERCONNECT STRUCTURES FOR SURFACE MOUNT SEMICONDUCTOR DEVICES

Non-Final OA §103
Filed
Sep 24, 2024
Examiner
KHAN, IBRAHIM A
Art Unit
2628
Tech Center
2600 — Communications
Assignee
Avago Technologies International Sales Pte. Limited
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
472 granted / 574 resolved
+20.2% vs TC avg
Moderate +12% lift
Without
With
+12.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
6 currently pending
Career history
594
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
70.5%
+30.5% vs TC avg
§102
12.1%
-27.9% vs TC avg
§112
8.2%
-31.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 574 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION In the response to this office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application. ALLOWABLE SUBJECT MATTER Claims 9-12 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 9 is objected to because the cited references do not disclose “and a vent portion in the tubular portion, at least a portion of the solder reservoir space is inside the tubular portion, and the vent portion connects the solder reservoir space to an outside of the tubular portion“. Claims 10-12 are objected to because the cited references do not disclose “wherein each protruding structure comprises a plurality of prong elements extending in a first direction from the wiring substrate, and the solder reservoir space of each mounting post is between adjacent prong eleme1nts in a second direction perpendicular to the first direction“. Claim 18 is objected to because the cited references do not disclose “and a vent portion in the tubular portion, at least a portion of the solder reservoir space is inside the tubular portion, and the vent portion connects the solder reservoir space to an outside of the tubular portion”. INFORMATION DISCLOSURE STATEMENT The information disclosure statements filed 02/02/2026 and 09/25/2024, have been acknowledged and considered by the examiner. Initialed copies of the PTO-1449 forms are included in this correspondence. CLAIM REJECTIONS - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 , if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 1. Claims 1-8, 13-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 20230009506 in view of Lin et al. US 20250149414. Consider claim 1. Wu discloses a semiconductor device fig. 5B 300, comprising: a wiring substrate fig. 5B wiring substrate WS; a chip on a first surface of the wiring substrate fig. 5B Dies 302 and 304 connected to RDL is the chip; and a plurality of protruding structures on a second surface of the wiring substrate fig. 5B C’ and 400. Wu does not explicitly disclose wherein each protruding structure includes a solder reservoir space therein. Lin however discloses wherein each protruding structure includes a solder reservoir space therein [0034-0035] liquid metal 232 disposed in well 235 fig. 2B 235. Also see fig. 4A [0046] well 435 filled with liquid metal 432. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu to include wherein each protruding structure includes a solder reservoir space therein, as taught by Lin, to maintain low Z-height of pins and also insure no shorting between interconnects [0023][0049]. Consider claim 2. Wu as modified by Lin disclose the semiconductor device of claim 1, further comprising: a solder ball on a lower end of each protruding structure Wu fig. 5B solder 400, wherein the solder reservoir space contains solder Lin fig. 2A 232 fig. 4A 432 liquid metal. Motivation to combine is similar to motivation in claim 1. Consider claim 3. Wu as modified by Lin disclose the semiconductor device of claim 1, wherein each protruding structure comprises a tubular portion, and at least a portion of the solder reservoir space is inside the tubular portion Lin fig. 2A 235 fig. 4A 435 wells Motivation to combine is similar to motivation in claim 1. Consider claim 4. Wu as modified by Lin disclose the semiconductor device of claim 3, wherein each protruding structure further comprises a vent portion in the tubular portion, the vent portion connecting the solder reservoir space to an outside of the tubular portion Lin fig. 4A 439 gaps. Motivation to combine is similar to motivation in claim 1. Consider claim 5. Wu as modified by Lin disclose the semiconductor device of claim 1, wherein the plurality of protruding structures are copper WU [0023] conductive structures include copper. Also see Lin [0034] liquid metal may comprise any suitable alloying element (Note: this includes copper). Consider claim 6. Wu as modified by Lin disclose the semiconductor device of claim 1, wherein the plurality of protruding structures is in a regular array arrangement fig. 5B BGA. Consider claim 7. Wu as modified by Lin disclose the semiconductor device of claim 1, wherein each protruding structure extends outwardly away from the wiring substrate in a first direction fig. 5B C’ and 400. Consider claim 8. Wu as modified by Lin disclose the semiconductor device of claim 7, wherein each protruding structure comprises: a lower pad portion at an end of the protruding structure farthest from the wiring substrate in the first direction Lin fig. 4A Lower pads 424, and an upper pad portion at an end of the protruding structure closest to the wiring substrate Lin fig. 4A upper pads 411 Motivation to combine is similar to motivation in claim 1. Consider claim 13. Wu as modified by Lin disclose the semiconductor device of claim 1, wherein each protruding structure comprises a pair of plate elements extending in a first direction from the wiring substrate see Lin fig. 5C-5D plates 545., and the solder reservoir space of each protruding structure is the gap between the pair of plate elements in a second direction perpendicular to the first direction see Lin fig. 5C-5D the well 535 is between plates 545. Motivation to combine is similar to motivation in claim 1. Consider claim 14. Wu as modified by Lin disclose the semiconductor device of claim 13, wherein the plate elements are flat plates see Lin fig. 5C-5D flat plates 545. Motivation to combine is similar to motivation in claim 1. Consider claim 15. Wu as modified by Lin disclose the semiconductor device of claim 13, wherein the plate elements are plates see Lin fig. 5C-5D flat plates 545. However, Wu as modified by Lin do not expressly disclose curved plates. Before the effective filing date of the invention, it would have been an obvious matter of design choice to a person of ordinary skill the art to have a curved plate instead of a flat plate because Applicant does not disclose that the curved plate provides an advantage, is used for a particular purpose or solves a stated problem. One of ordinary skill in the art furthermore, would have expected Applicant’s invention to perform equally well with flat plates Therefore, it would have been obvious matter of design choice to modify Wu as modified by Lin to obtain the invention as specified in claim 15. Consider claim 16. Wu discloses a semiconductor device fig. 5B 300, comprising: a wiring substrate fig. 5B wiring substrate WS; a chip on a first surface of the wiring substrate fig. 5B Dies 302 and 304 connected to RDL is the chip on first surface of WS; and a plurality of mounting posts on a second surface of the wiring substrate fig. 5B C’ on second surface of WS, each mounting post extending from the second surface in a first direction substantially orthogonal to the second surface fig. 5B see C’ extension direction; and a solder ball on an end of each mounting post farthest from the wiring substrate in the first direction fig. 5B 400, wherein Wu does not explicitly disclose each mounting post has a solder reservoir space therein, and at least one solder reservoir space has solder therein. Lin however discloses each mounting post has a solder reservoir space therein, and at least one solder reservoir space has solder therein [0034-0035] liquid metal 232 disposed in well 235 fig. 2B 235. Also see fig. 4A [0046] well 435 filled with liquid metal 432. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu to include each mounting post has a solder reservoir space therein, and at least one solder reservoir space has solder therein, as taught by Lin, to maintain low Z-height of pins and also insure no shorting between interconnects [0023][0049]. Consider claim 17. Wu as modified by Lin disclose the semiconductor device of claim 16, wherein each mounting posts comprises a plurality of prong elements extending in the first direction from the wiring substrate see Lin fig. 5C-5D the well 535 is between plates 545., and the solder reservoir space of each mounting post is between adjacent prong elements in a second direction perpendicular to the first direction. see Lin fig. 5C-5D the well 535 is between plates 545. Motivation to combine is similar to motivation in claim 16. Consider claim 19. Wu discloses electronic device [0001] PC, cellphone, digital camera, electronic equipment etc. , comprising: wherein the semiconductor device fig. 5B 300, comprises: a wiring substrate fig. 5B wiring substrate WS; a chip on a first surface of the wiring substrate fig. 5B Dies 302 and 304 connected to RDL is the chip; and a plurality of protruding structures on a second surface of the wiring substrate fig. 5B C’ and 400. Wu does not explicitly disclose a circuit board with a plurality of mounting pads at a surface thereof; and a semiconductor device soldered to the plurality of mounting pads, and each protruding structure includes a solder reservoir space therein. Lin however, discloses a circuit board with a plurality of mounting pads at a surface thereof; and a semiconductor device soldered to the plurality of mounting pads fig. 4A-4B PCB 420 with pads 424, and each protruding structure includes a solder reservoir space therein [0034-0035] liquid metal 232 disposed in well 235 fig. 2B 235. Also see fig. 4A [0046] well 435 filled with liquid metal 432. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu to include a circuit board with a plurality of mounting pads at a surface thereof; and a semiconductor device soldered to the plurality of mounting pads, and each protruding structure includes a solder reservoir space therein, as taught by Lin, to maintain low Z-height of pins and also insure no shorting between interconnects [0023][0049]. Consider claim 20. Wu as modified by Lin disclose the electronic device of claim 19, wherein a solder level in a solder reservoir space of a first protruding structure in the plurality of protruding structures is different from a solder level in a solder reservoir space of a second protruding structure in the plurality of protruding structures see Lin fig. 4A the liquid metal level 432 in the different wells 435 is not the same. Motivation to combine is similar to motivation in claim 19. CONCLUSION Any inquiry concerning this communication or earlier communications from the examiner should be directed to IBRAHIM A KHAN whose telephone number is (571)270-7998. The examiner can normally be reached on 10am-6pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. IBRAHIM A. KHAN Primary Examiner Art Unit 2628 /IBRAHIM A KHAN/ 09/21/2026Primary Examiner, Art Unit 2628
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Prosecution Timeline

Sep 24, 2024
Application Filed
Sep 23, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
94%
With Interview (+12.1%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 574 resolved cases by this examiner. Grant probability derived from career allowance rate.

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