DETAILED ACTION
This FINAL action is in response to Application No. 18/895,374 originally filed 09/24/2024. The amendment presented on 05/14/2026 which provides amendments to claims 1 and 5 is hereby acknowledged.Currently Claim(s) 1-9 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 05/14/2026 have been fully considered but they are not persuasive.
Applicant asserts that the prior art is “entirely silent regarding any dynamic adjustment logic or mathematical relationship based on "compensating for disconnected data line capacitance"” however The Office respectfully disagrees. Morita teaches that the variable capacitance circuit 30 is a circuit, serving as a capacitance connected to the data voltage output node NVQ, whose capacitance value can be set in a variable manner. This variable manner in which the variable capacitance circuit 30 is set is expressly considered dynamic adjustment logic. Furthermore, Morita discloses examples of the data lines referenced as source lines SL1-SL1280 in Figure 13 being either connected or disconnected depending upon the driving period of the signal line groups as seen in timing diagram of Figure 14 and the particular time period itself. In the precharge time period, all lines are simultaneously turned on while only subsets of the data lines in each noted “output 1” through “output 3” are sequentially turned on during the driving period. Therefore, Morita does in fact disclose data lines being connected and/or disconnected during different periods. Morita teaches that capacitive driving is carried out by the capacitor circuit 10 and the capacitor driving circuit 20, and the data lines DL1 to DL8 are driven by data voltages SV1 to SV8 while the capacitance CA of the variable capacitance circuit 30 is a capacitance value set for the variable capacitance of the variable capacitance circuit 30. Therefore, The Office considers the claims still broad enough to read on the prior art of record and the rejection will be maintained.
The Office additionally notes that clarifications to claim 5 appear to overcome the prior art rejection and will be objected to herein.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4 and 6-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morita U.S. Patent Application Publication No. 2016/0111058 A1 hereinafter Morita.
Consider Claim 1:
Morita discloses a driver comprising: (Morita, See Abstract.)
a capacitor driving circuit configured to output first to n-th capacitor driving voltages, (Morita, [0050], “FIG. 1 illustrates a first example of the configuration of a driver according to this embodiment. This driver 100 includes a capacitor circuit 10, a capacitor driving circuit 20, and a data voltage output terminal TVQ. Note that in the following, the same sign as a sign for a capacitor is used as a sign indicating a capacitance value of that capacitor.”)
corresponding to grayscale data to first to n-th capacitor driving nodes, n being a natural number equal to or larger than 2; (Morita, [0005], [0011], [0054], “An ith bit GDi of tone data GD [10:1] is inputted into an input node of an ith driving unit DRi of the first to tenth driving units DR1 to DR10. An output node of the ith driving unit DRi corresponds to the ith capacitor driving node NDRi. The tone data GD [10:1] is constituted of first to tenth bits GD1 to GD10 (first to nth bits), where the bit GD1 corresponds to the LSB and the bit GD10 corresponds to the MSB.”)
a capacitor circuit including first to n-th capacitors provided between the first to n-th capacitor driving nodes and an output terminal; (Morita, [0052], “The capacitor circuit 10 includes first to nth capacitors C1 to Cn (where n is a natural number of 2 or more). The capacitor driving circuit 20 includes first to nth driving units DR1 to DRn. Although the following describes a case where n=10 as an example, n may be any natural number greater than or equal to 2. For example, n may be set to the same number as the bit number of tone data.”)
a variable capacitance circuit connected to the output terminal; and (Morita, [0069], “Note that in the case where the variable capacitance circuit 30 is provided, the variable capacitance circuit 30 serves as the load-side capacitance, and the rise in voltage is reduced to a certain extent. However, in the case where the electro-optical panel-side capacitance CP has decreased due to a connection defect, the load-side capacitance will decrease, and the voltage VQ during the capacitive driving will nevertheless rise. For example, Formula FD in FIG. 7B indicates a maximum value of the data voltage when the variable capacitance circuit 30 is provided. CA represents the capacitance of the variable capacitance circuit 30. As can be seen from the upper right side of Formula FD, the maximum value of the data voltage rises as CP drops.”)
a control circuit configured to set the variable capacitance circuit to a first capacitance value in a pixel driving period of an electro-optical panel and (Morita, [0074], “For example, in the case where CA1 is set to 1 pF, the capacitance of the variable capacitance circuit 30 is 1 pF while only the switching element SWA1 is on, whereas the capacitance of the variable capacitance circuit 30 is 63 pF (=1 pF+2 pF+ . . . +32 pF) while all the switching elements SWA1 to SWA6 are on. Because the capacitance values are weighted by a power of 2, the capacitance of the variable capacitance circuit 30 can be set from 1 pF to 63 pF in 1 pF (CA1) steps in accordance with whether the switching elements SWA1 to SWA6 are on or off.”)
to set the variable capacitance circuit to a second capacitance value smaller than the first capacitance value in a precharge period of the electro-optical panel, so that a capacitance other than the capacitor circuit is constant among the precharge period and the pixel driving period, (Morita, [0070-0074], [0075-100], [0144], “The precharge terminal TPR is connected to an output of the precharge amplifier circuit AMPR. The precharge D/A conversion circuit DAPR D/A-converts a precharge setting value (a register value, for example) and generates the precharge voltage VPR, and the precharge amplifier circuit AMPR drives the precharge terminal TPR using the precharge voltage VPR. The precharge voltage VPR is a voltage that is lower than the reset voltage VC, for example (within a data voltage range of 7.5 V to 2.5 V in negative-polarity driving).”)
wherein the first capacitance value is substantially equal to the second capacitance value plus a third capacitance value corresponding to a number of data lines in the electro-optical panel disconnected to the output terminal during the pixel driving period as compared to the precharge period. (Morita, [0164-0169], [0167], “In a first output period in the data voltage output period, the tone data corresponding to the source lines SL1 to SL8 are inputted into the data line driving circuits DD1 to DD8. Then, capacitive driving is carried out by the capacitor circuit 10 and the capacitor driving circuit 20, and the data lines DL1 to DL8 are driven by data voltages SV1 to SV8. After the capacitive driving starts, the signal ENBX goes to high-level, and the switching elements SWEP1 to SWEP8 turn on. Then, the source lines SL1 to SL8 are driven by the data voltages SV1 to SV8. At this time, a single gate line (horizontal scanning line) is selected by a gate driver (not shown), and the data voltages SV1 to SV8 are written into the pixel circuits connected to the selected gate line and the data lines DL1 to DL8. Note that FIG. 13 illustrates potentials of the data line DL1 and the source line SL1 as examples.”)
Consider Claim 2:
Morita discloses the driver according to claim 1, wherein the control circuit sets the first capacitance value and the second capacitance value to make CA + CLCD in the precharge period close to CA + CLCD in the pixel driving period, where CA is a capacitance value of the variable capacitance circuit and CLCD is a capacitance value of a side of the electro-optical panel-side capacitance. (Morita, [0079], “As illustrated in FIG. 4C, a desired data voltage range is assumed to be 5 V, for example. The maximum value of 12.5 V for the data voltage is realized in the case where, from Formula FD, CO/(CO+(CA+CP))=1/3, or in other words, in the case where CA+CP=2CO. CA is the capacitance of the variable capacitance circuit, and can thus be set freely, which in turn means that the CA can be set to 2CO−CP for the provided CP. In other words, regardless of the type of the electro-optical panel 200 connected to the driver 100, the design of the mounting board, or the like, the data voltage range can always be set to 7.5 V to 12.5 V.”)
Consider Claim 3:
Morita discloses the driver according to claim 1, wherein the control circuit sets the first capacitance value and the second capacitance value to make CA + CLCD in the pixel driving period and CA + CLCD in the precharge period constant, where CA is a capacitance value of the variable capacitance circuit and CLCD is a capacitance value of a side of the electro-optical panel-side capacitance. (Morita, [0058], [0060], [0074], “For example, in the case where CA1 is set to 1 pF, the capacitance of the variable capacitance circuit 30 is 1 pF while only the switching element SWA1 is on, whereas the capacitance of the variable capacitance circuit 30 is 63 pF (=1 pF+2 pF+ . . . +32 pF) while all the switching elements SWA1 to SWA6 are on. Because the capacitance values are weighted by a power of 2, the capacitance of the variable capacitance circuit 30 can be set from 1 pF to 63 pF in 1 pF (CA1) steps in accordance with whether the switching elements SWA1 to SWA6 are on or off.”)
Consider Claim 4:
Morita discloses the driver according to claim 1, wherein the variable capacitance circuit includes: first to m-th adjustment capacitors, m being a natural number equal to greater than 2; and first to m-th adjustment switches provided between the first to m-th adjustment capacitors and the output terminal. (Morita, [0071], “The variable capacitance circuit 30 is a circuit, serving as a capacitance connected to the data voltage output node NVQ, whose capacitance value can be set in a variable manner. Specifically, the variable capacitance circuit 30 includes first to mth switching elements SWA1 to SWAm (where m is a natural number of 2 or more), and first to mth adjusting capacitors CA1 to CAm. Note that the following will describe an example in which m=6.”)
Consider Claim 6:
Morita discloses an electro-optical device comprising: the driver according to claim 1, and the electro-optical panel, wherein the electro-optical panel includes: a signal supply line; first to p-th switches having one ends connected to the signal supply line, p being an integer that is equal to or larger than 2; and first to p-th data lines connected to other ends of the first to p-th switches. (Morita, [0161], “The electro-optical panel 200 includes the data lines DL1 to DL8 (first to kth data lines), switching elements SWEP1 to SWEP(tk), and source lines SL1 to SL(tk). t is a natural number of 2 or more, and the following will describe an example in which t=160 (in other words, tk=160×8=1,280 (WXGA)).”)
Consider Claim 7:
Morita discloses the electro-optical device according to claim 6, wherein the first to p-th switches are ON in the precharge period, and any one of the first to p-th switches is ON in the pixel driving period. (Morita, [0164-0169], [0147], “As illustrated in FIG. 11, the driving of the electro-optical panel 200 is carried out in the order of precharge, reset, data voltage output, and postcharge. This series of operations is carried out in a single horizontal scanning period, for example.”)
Consider Claim 8:
Morita discloses the electro-optical device according to claim 6, wherein first to p/2-th switches among the first to p-th switches are ON in the precharge period of a first horizontal scanning period, p being an even number equal to or larger than 2, and p/2+1-th to p-th switches among the first to p-th switches are ON in the precharge period of a second horizontal scanning period. (Morita, [0165], “In the precharge period, the signal ENBX goes to high-level, and all of the switching elements SWEP1 to SWEP1280 turn on. Then, all of the source lines SL1 to SL1280 are set to the precharge voltage VPR.”)
Consider Claim 9:
Morita discloses an electronic apparatus comprising: the driver according to claim 1. (Morita, See Abstract and rejection of claim 1.)
Allowable Subject Matter
Claim 5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Granting of After Final Interviews: “Interviews merely to restate arguments of record or to discuss new limitations which would require more than nominal reconsideration or new search should be denied.” See MPEP § 713.09.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J JANSEN II whose telephone number is (571)272-5604. The examiner can normally be reached Normally Available Monday-Friday 9am-4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached on 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626
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