DETAILED ACTION
This communication is in response to Application No. 18/895,374 originally filed 09/24/2024. The Request for Continued Examination and Amendment presented on 12/08/2025 which provides amendments to claims 1 is hereby acknowledged. Currently claims 1-9 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/08/2025 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/08/2025 have been fully considered but they are not persuasive. Morita teaches that FIG. 13 is an operational timing chart of the driver 100 and the electro-optical panel 200 illustrated in FIG. 12. The reference to the driver 100 is that which has been described by Fig. 3 which shows and describes the exact replica of applicants’ own capacitor circuit 10/20, variable capacitor 30, signal supply line capacitance CP1, and data line capacitance CP2. (see the instant application in Figure 4 and Morita in Figure 3) In at the very least, paragraphs [0070-0074] expressly teaches the use of this circuit during operation in a first example while paragraphs [0075-100] teach a second, in depth, example. It should be noted here that the driver 100 in Morita and the driver 100 of the instant application appear to be exactly the same (and is assigned to the same Applicant). Thus, the signal supply line and/or data line would be constant among other capacitances as these are clearly part of the device itself and don’t change. As these features are the ones generally being claimed, The Office finds no apparent difference between the claimed invention and the prior art. While the instant application may describe features beyond that considered in the Morita reference, Applicants claims are still generic enough to encompass that which has already been disclosed in the reference. In response to applicant's argument that the references fail to show certain features of applicant’s invention, claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, it is respectfully submitted the claims are a still broad enough to read on the prior art of record and will be currently maintained.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morita U.S. Patent Application Publication No. 2016/0111058 A1 hereinafter Morita.
Consider Claim 1:
Morita discloses a driver comprising: (Morita, See Abstract.)
a capacitor driving circuit configured to output first to n-th capacitor driving voltages, (Morita, [0050], “FIG. 1 illustrates a first example of the configuration of a driver according to this embodiment. This driver 100 includes a capacitor circuit 10, a capacitor driving circuit 20, and a data voltage output terminal TVQ. Note that in the following, the same sign as a sign for a capacitor is used as a sign indicating a capacitance value of that capacitor.”)
corresponding to grayscale data to first to n-th capacitor driving nodes, n being a natural number equal to or larger than 2; (Morita, [0005], [0011], [0054], “An ith bit GDi of tone data GD [10:1] is inputted into an input node of an ith driving unit DRi of the first to tenth driving units DR1 to DR10. An output node of the ith driving unit DRi corresponds to the ith capacitor driving node NDRi. The tone data GD [10:1] is constituted of first to tenth bits GD1 to GD10 (first to nth bits), where the bit GD1 corresponds to the LSB and the bit GD10 corresponds to the MSB.”)
a capacitor circuit including first to n-th capacitors provided between the first to n-th capacitor driving nodes and an output terminal; (Morita, [0052], “The capacitor circuit 10 includes first to nth capacitors C1 to Cn (where n is a natural number of 2 or more). The capacitor driving circuit 20 includes first to nth driving units DR1 to DRn. Although the following describes a case where n=10 as an example, n may be any natural number greater than or equal to 2. For example, n may be set to the same number as the bit number of tone data.”)
a variable capacitance circuit connected to the output terminal; and (Morita, [0069], “Note that in the case where the variable capacitance circuit 30 is provided, the variable capacitance circuit 30 serves as the load-side capacitance, and the rise in voltage is reduced to a certain extent. However, in the case where the electro-optical panel-side capacitance CP has decreased due to a connection defect, the load-side capacitance will decrease, and the voltage VQ during the capacitive driving will nevertheless rise. For example, Formula FD in FIG. 7B indicates a maximum value of the data voltage when the variable capacitance circuit 30 is provided. CA represents the capacitance of the variable capacitance circuit 30. As can be seen from the upper right side of Formula FD, the maximum value of the data voltage rises as CP drops.”)
a control circuit configured to set the variable capacitance circuit to a first capacitance value in a pixel driving period of an electro-optical panel and (Morita, [0074], “For example, in the case where CA1 is set to 1 pF, the capacitance of the variable capacitance circuit 30 is 1 pF while only the switching element SWA1 is on, whereas the capacitance of the variable capacitance circuit 30 is 63 pF (=1 pF+2 pF+ . . . +32 pF) while all the switching elements SWA1 to SWA6 are on. Because the capacitance values are weighted by a power of 2, the capacitance of the variable capacitance circuit 30 can be set from 1 pF to 63 pF in 1 pF (CA1) steps in accordance with whether the switching elements SWA1 to SWA6 are on or off.”)
to set the variable capacitance circuit to a second capacitance value smaller than the first capacitance value in a precharge period of the electro-optical panel, so that a capacitance other than the capacitor circuit is constant among the precharge period and the pixel driving period. (Morita, [0070-0074], [0075-100], [0144], “The precharge terminal TPR is connected to an output of the precharge amplifier circuit AMPR. The precharge D/A conversion circuit DAPR D/A-converts a precharge setting value (a register value, for example) and generates the precharge voltage VPR, and the precharge amplifier circuit AMPR drives the precharge terminal TPR using the precharge voltage VPR. The precharge voltage VPR is a voltage that is lower than the reset voltage VC, for example (within a data voltage range of 7.5 V to 2.5 V in negative-polarity driving).”)
Consider Claim 2:
Morita discloses the driver according to claim 1, wherein the control circuit sets the first capacitance value and the second capacitance value to make CA + CLCD in the precharge period close to CA + CLCD in the pixel driving period, where CA is a capacitance value of the variable capacitance circuit and CLCD is a capacitance value of a side of the electro-optical panel-side capacitance. (Morita, [0079], “As illustrated in FIG. 4C, a desired data voltage range is assumed to be 5 V, for example. The maximum value of 12.5 V for the data voltage is realized in the case where, from Formula FD, CO/(CO+(CA+CP))=1/3, or in other words, in the case where CA+CP=2CO. CA is the capacitance of the variable capacitance circuit, and can thus be set freely, which in turn means that the CA can be set to 2CO−CP for the provided CP. In other words, regardless of the type of the electro-optical panel 200 connected to the driver 100, the design of the mounting board, or the like, the data voltage range can always be set to 7.5 V to 12.5 V.”)
Consider Claim 3:
Morita discloses the driver according to claim 1, wherein the control circuit sets the first capacitance value and the second capacitance value to make CA + CLCD in the pixel driving period and CA + CLCD in the precharge period constant, where CA is a capacitance value of the variable capacitance circuit and CLCD is a capacitance value of a side of the electro-optical panel-side capacitance. (Morita, [0058], [0060], [0074], “For example, in the case where CA1 is set to 1 pF, the capacitance of the variable capacitance circuit 30 is 1 pF while only the switching element SWA1 is on, whereas the capacitance of the variable capacitance circuit 30 is 63 pF (=1 pF+2 pF+ . . . +32 pF) while all the switching elements SWA1 to SWA6 are on. Because the capacitance values are weighted by a power of 2, the capacitance of the variable capacitance circuit 30 can be set from 1 pF to 63 pF in 1 pF (CA1) steps in accordance with whether the switching elements SWA1 to SWA6 are on or off.”)
Consider Claim 4:
Morita discloses the driver according to claim 1, wherein the variable capacitance circuit includes: first to m-th adjustment capacitors, m being a natural number equal to greater than 2; and first to m-th adjustment switches provided between the first to m-th adjustment capacitors and the output terminal. (Morita, [0071], “The variable capacitance circuit 30 is a circuit, serving as a capacitance connected to the data voltage output node NVQ, whose capacitance value can be set in a variable manner. Specifically, the variable capacitance circuit 30 includes first to mth switching elements SWA1 to SWAm (where m is a natural number of 2 or more), and first to mth adjusting capacitors CA1 to CAm. Note that the following will describe an example in which m=6.”)
Consider Claim 5:
Morita discloses the driver according to claim 1, wherein the control circuit sets the variable capacitance circuit to a third capacitance value larger than the first capacitance value in a post charge period. (Morita, [0136], “As illustrated in FIG. 9B, in the case of “YES” in step S8 for the preliminary setting value CSW[6:1]=“1Fh”, VQ≧Vh2. In this case, it is necessary to lower the output voltage VQ. From Formula FD in FIG. 4B, it can be seen that the output voltage VQ will drop if the capacitance CA of the variable capacitance circuit 30 is increased, and thus the setting value CSW[6:1] is increased by “1” at a time. The setting value CSW[6:1] stops at “24h”, where VQ<Vh2 for the first time. Through this, the setting value CSW[6:1] at which the output voltage VQ nearest to the detection voltage Vh2 is obtained can be determined.”)
Consider Claim 6:
Morita discloses an electro-optical device comprising: the driver according to claim 1, and the electro-optical panel, wherein the electro-optical panel includes: a signal supply line; first to p-th switches having one ends connected to the signal supply line, p being an integer that is equal to or larger than 2; and first to p-th data lines connected to other ends of the first to p-th switches. (Morita, [0161], “The electro-optical panel 200 includes the data lines DL1 to DL8 (first to kth data lines), switching elements SWEP1 to SWEP(tk), and source lines SL1 to SL(tk). t is a natural number of 2 or more, and the following will describe an example in which t=160 (in other words, tk=160×8=1,280 (WXGA)).”)
Consider Claim 7:
Morita discloses the electro-optical device according to claim 6, wherein the first to p-th switches are ON in the precharge period, and any one of the first to p-th switches is ON in the pixel driving period. (Morita, [0164-0169], [0147], “As illustrated in FIG. 11, the driving of the electro-optical panel 200 is carried out in the order of precharge, reset, data voltage output, and postcharge. This series of operations is carried out in a single horizontal scanning period, for example.”)
Consider Claim 8:
Morita discloses the electro-optical device according to claim 6, wherein first to p/2-th switches among the first to p-th switches are ON in the precharge period of a first horizontal scanning period, p being an even number equal to or larger than 2, and p/2+1-th to p-th switches among the first to p-th switches are ON in the precharge period of a second horizontal scanning period. (Morita, [0165], “In the precharge period, the signal ENBX goes to high-level, and all of the switching elements SWEP1 to SWEP1280 turn on. Then, all of the source lines SL1 to SL1280 are set to the precharge voltage VPR.”)
Consider Claim 9:
Morita discloses an electronic apparatus comprising: the driver according to claim 1. (Morita, See Abstract and rejection of claim 1.)
Conclusion
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J JANSEN II whose telephone number is (571)272-5604. The examiner can normally be reached Normally Available Monday-Friday 9am-4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached on 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Michael J Jansen II/ Primary Examiner, Art Unit 2626