DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final communication in response to communication filed 9/25/24.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
With respect to claims 1, 8 and 15, the recitations “output of the DPLL” and “an output frequency of the DPLL,” it’s unclear if they are the same output or different and how they’re related. Since there is only one output of the DPLL [110] received by the fractional-N PLL [120]. The output of the DPLL is a filter output and described as a control voltage in the specification, it does not have a frequency. The DPLL does not even have a oscillator to output a frequency. Additionally, reciting the DPLL and the fractional N PLL as to separate loops when in fact they are interconnected is unclear. Therefore the structural relationship between the fractional-N phase locked loop and the DPLL is unclear.
With respect to claim 1, 8, and 15, it’s unclear how or where the “reading, calculating, accumulating, computing, and extracting” is done. Why is the fraction portion of the output of the DPLL able to be read while the integer portion of the output needs to be calculated?
With respect to claims 2, 9 and 16, the recitation “comprising: calculating a sample of the output of the DPLL; and computing the average value of the output frequency of the DPLL using the sample the output of the DPLL,” is indefinite because it’s unclear where the new method steps occur or if they replace steps with respect to claims 1, 8 and 15.
With respect to claims 2, 9 and 16, the recitation of “calculating a sample of the output of the DPLL,” is indefinite because a sample is just a value of a signal at a specific time.
Claim 4, 11, 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
In claims 4, 11 and 18, the input clock and monitoring have no connection or cooperation the other elements of the circuit.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ranganathan et al. 10908635.
Insofar as understood with respect to claim 1, 8 and 15 figures 2 and 4 of Ranganathan et al disclose a method, comprising:
reading a fractional portion of an output [ part of LF_OUT] of a digital phase locked loop (DPLL) [122,124,126];
calculating an integer portion [part of LF_OUT] of the output of the DPLL;
accumulating a predetermined number of samples of the fractional portion and the integer portion of the output of the DPLL;
computing an average value of an output frequency of the DPLL over the predetermined number of samples; [col. 4. Lines 1-26; col. 8, line 46- col. 9, line 8. Avg of past divider values used in hold over mode. ]
extracting a fractional portion and an integer portion of the average value of the output frequency of the DPLL; and [divider 118 is a fractional divider; therefore the digital signal LF-OUT] has a interger and fractional component.
loading the fractional portion and the integer portion of the average value of the output frequency of the DPLL as preset values in a fractional-N phase locked loop (PLL). [408 stores integer and fractional values for divider 118.]
Claim 15: Non-transitory computer readable medium [col. 9, lines 55-67]
Insofar as understood with respect to claim 2, 9 and 16 figures 2 and 4 of Ranganathan et al disclose the method of claim 1, comprising: calculating a sample of the output of the DPLL; and
computing the average value of the output frequency of the DPLL using the sample the output of the DPLL.
Insofar as understood with respect to claim 3, 10, and 17 figures 2 and 4 of Ranganathan et al disclose the method of claim 1, wherein the predetermined number of samples is based on an operating frequency of the DPLL. [the current number a cycles]
Insofar as understood with respect to claim 4, 11 and 18 figures 2 and 4 of Ranganathan et al disclose the method of claim 1, comprising: monitoring a frequency of an input clock; identifying a loss of a link to the input clock; and generating a link loss signal. [fig.3 and 4, 324, loss of signal events to place circuit in holdover mode.]
Insofar as understood with respect to claim 5, 12 and 19 figures 2 and 4 of Ranganathan et al disclose the method of claim 1, comprising outputting a clock signal [CLKOUT] based on the preset values in the fractional-N PLL. [col. 8, line 46 - col. 9, line 8]
Insofar as understood with respect to claim 6, 13 and 20 figures 2 and 4 of Ranganathan et al disclose the method of claim 1, comprising reading the fractional portion of the output of the DPLL at a predetermined interval. [the sample interval]
Insofar as understood with respect to claim 7, and 14 figures 2 and 4 of Ranganathan et al disclose the method of claim 1, wherein the predetermined number of samples is accumulated on a rolling basis. [each new sample is accumulated and averaged.]
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached on 571-27. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN JAGER/
Primary Examiner, Art Unit 2843
2/20/26