Office Action Predictor
Last updated: April 16, 2026
Application No. 18/895,535

LEVEL SHIFTER INCLUDING CAPACITOR AND METHOD OF OPERATING THE SAME

Non-Final OA §112
Filed
Sep 25, 2024
Examiner
HILTUNEN, THOMAS J
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., LTD.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
86%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
1003 granted / 1235 resolved
+13.2% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
30 currently pending
Career history
1265
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
44.4%
+4.4% vs TC avg
§102
39.7%
-0.3% vs TC avg
§112
10.9%
-29.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1235 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the method step of “turning on a first transistor connected between a first node and a power source voltage and turning off a second transistor between the first node and a first ground voltage in response to a voltage level of the input voltage transitioning from a low level to a high level” as recited in claim 13 and the method step of “wherein turning on the first transistor includes applying the input voltage boosted by charges previously stored in the input terminal and at least one capacitor to a gate electrode of the first transistor” as recited in claim 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. With respect to claim 13, the recitation of “turning off the first transistor and turning on the second transistor in response to the voltage level of the input voltage transitioning from the low level to the high level” (Examiner’s emphasis) as on lines 6-7 cannot be understood, since the instant specification and/or drawings fails to disclose such a first and third transistor operated as claimed. For instance, as far as can be understood, assuming that TR1 (of Fig. 1A) is interpreted as the first transistor and TR2 (of Fig. 1A) is interpreted as the second transistor. The specification provides support for turning on the first transistor and turning of the second transistor in response to the voltage level of the input voltage transitioning from the low to high level (i.e., the recitation of lines 6-7) in paragraph 0060 (“TR1 may be turned on”…”when the VIN transitions from a low level to a high level”) and paragraph 0063 (“when the voltage level of the input voltage VIN transitions from a low level to a high level, the second transistor TR2 may be turned off”) of the instant specification. The above recitation is essentially the claimed operations as recited in lines 3-5 of claim 13. However, paragraph 0087 of the instant specification states that “when the voltage level of the input voltage Vin transitions from a high level to a low level, the first transistor TR1 may be turned off” (Examiner’s emphasis). Furthermore, paragraph 0091 of the instant specification states “when the voltage level of the input voltage Vin transitions from a high level to a low level, the second transistor TR2 may be turned on” (Examiner’s emphasis). Therefore, as far as can be understood, the first transistor is not turned off and the second transistor is not turned on “in response to the voltage level of the input voltage transitioning from the low level to the high level” as recited in lines 6-7 of claim 13. Rather, as far as can be understood, the first transistor is turned off and the second transistor is turned on responsive to the voltage level of the input voltage transition from the high level to the low level. With further respect to claim 13, the recitation of “turning on the first transistor includes applying the input voltage boosted by charges previously stored in the input terminal and at least one capacitor to a gate electrode of the first transistor” (Examiner’s emphasis), on lines 10-12, cannot be understood, since such a limitation is not disclosed by the instant specification and/or drawings. As far as can be understood the gate of the first transistor TR1 is connected to voltage V2 on node N4 of Fig. 1A of the instant drawings. The voltage V2 on the node N4 does not include a boosted voltage that is boosted “by charges previously stored in the input terminal and at least one capacitor” to the gate of the first transistor TR1. Rather, capacitor C2 provides the boosted voltage to the gate of TR1, wherein the boosted voltage is based on a voltage having a phase that is reveres with respect to the input voltage (see paragraphs 0055 and 0088). Thus, C2 is not charged with charges previously stored in the input terminal. Rather, as far as can be understood, C2 is changed with charges previously stored in a terminal having a phase that is reversed with respect to the input terminal. Claims 14-15 are rejected for the same reasons as claim 13. Allowable Subject Matter Claims 1-12 and 16-20 are allowed. With respect to claims 13-15, allowable subject matter could not be determined due to the deficiencies as indicated in the above rejections of claims 13-15 under 35 USC section 112. It cannot be determined how the first transistor is turned on by “applying the input voltage boosted by charges previously stored in the input terminal and a least one capacitor to a gate electrode of the first transistor” as recited in claim 13, since there is no circuitry disclosed in the instant specification and drawings that is capable of being operated as claimed. Thus, allowability cannot be determined. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2849
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Prosecution Timeline

Sep 25, 2024
Application Filed
Dec 09, 2025
Non-Final Rejection — §112
Apr 07, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
86%
With Interview (+5.2%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 1235 resolved cases by this examiner. Grant probability derived from career allow rate.

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